[PATCH] D62492: [AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register.

[Michael Liao via Phabricator via llvm-commits]

hliao created this revision.
hliao added reviewers: rampitec, nhaehnle, arsenm, alex-t.
Herald added subscribers: llvm-commits, hiraditya, t-tye, tpr, dstuttard, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

- Don't treat the use of a scalar register as `vreg_1` an VGPR usage. Otherwise, that promotes that scalar register into vector one, which breaks the assumption that scalar register holds the lane mask.
- The issue is triggered in a complicated case, where if the uses of that (lane mask) scalar register is legalized firstly before its definition, e.g., due to the mismatch block placement and its topological order or loop. In that cases, the legalization of PHI introduces the use of that scalar register as `vreg_1`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62492

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir


Index: llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
+++ llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
@@ -16,3 +16,44 @@
     %6:sreg_32 = S_ADD_I32 %2:sreg_32, %5:sreg_32, implicit-def $scc
     %7:sreg_32 = S_ADDC_U32 %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $scc
 ...
+# GCN-LABEL: name: fix-sgpr-phi-copies
+# GCN: .8:
+# GCN-NOT: vreg_64 = PHI
+---
+name: fix-sgpr-phi-copies
+tracksRegLiveness: true
+body:               |
+  bb.9:
+    S_BRANCH %bb.0
+
+  bb.4:
+    S_CBRANCH_SCC1 %bb.6, implicit undef $scc
+
+  bb.5:
+    %3:vreg_1 = IMPLICIT_DEF
+
+  bb.6:
+    %4:vreg_1 = PHI %2:sreg_64, %bb.4, %3:vreg_1, %bb.5
+
+  bb.7:
+    %5:vreg_1 = PHI %2:sreg_64, %bb.3, %4:vreg_1, %bb.6
+    S_BRANCH %bb.8
+
+  bb.0:
+    S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+
+  bb.1:
+    %0:sreg_64 = S_MOV_B64 0
+    S_BRANCH %bb.3
+
+  bb.2:
+    %1:sreg_64 = S_MOV_B64 -1
+    S_BRANCH %bb.3
+
+  bb.3:
+    %2:sreg_64 = PHI %0:sreg_64, %bb.1, %1:sreg_64, %bb.2
+    S_CBRANCH_SCC1 %bb.7, implicit undef $scc
+    S_BRANCH %bb.4
+
+  bb.8:
+...
Index: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -588,7 +588,9 @@
             }
 
             if (UseMI->isPHI()) {
-              if (!TRI->isSGPRReg(MRI, Use.getReg()))
+              const TargetRegisterClass *UseRC = MRI.getRegClass(Use.getReg());
+              if (!TRI->isSGPRReg(MRI, Use.getReg()) &&
+                  UseRC != &AMDGPU::VReg_1RegClass)
                 hasVGPRUses++;
               continue;
             }
@@ -631,8 +633,10 @@
 
         if ((!TRI->isVGPR(MRI, PHIRes) && RC0 != &AMDGPU::VReg_1RegClass) &&
             (hasVGPRInput || hasVGPRUses > 1)) {
+          LLVM_DEBUG(dbgs() << "Fixing PHI: " << MI);
           TII->moveToVALU(MI);
         } else {
+          LLVM_DEBUG(dbgs() << "Legalizing PHI: " << MI);
           TII->legalizeOperands(MI, MDT);
         }
 


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