[PATCH] D62341: [DAGCombine][X86][AArch64][AMDGPU][MIPS][PPC] (sub x, c) -> (add x, -c) vector edition.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, craig.topper, spatel, t.p.northover, arsenm, atanasyan, hfinkel.
lebedev.ri added a project: LLVM.
Herald added subscribers: jsji, jrtc27, kristof.beyls, arichardson, t-tye, tpr, dstuttard, javed.absar, yaxunl, nhaehnle, wdng, jvesely, nemanjai, kzhuravl, sdardis.

Lots of diff. The entire `check-llvm-codegen` passes,
so only X86 had conflicting transform.

We want this transform because currently every single DAGCombine `add %x, C`
vector pattern needs to be written twice - for `add` and for `sub`.
Not good.

- AArch64 changes look neutral-positive. I'm not good with that asm, but i think `movi v1.2d` encodes the entire all-ones as an `imm0_255:$imm8`, so there should not be codesize penalty?
- AMDGPU seems to miss a fold: "if this is an `add`ition by an immediate, and immediate needs a load, and negated immediate won't need load if used in `add`, then transform `add` to `sub`" Looks neutral otherwise
- MIPS - bad, many regressions, same fold as AMDGPU seems missing.
- PowerPC - not great, some regressions, same fold as AMDGPU seems missing.
- X86 - in average looks like an improvement :) There are more deletions than additions. We delete 137 unfolded constant-pool loads, but add 56; delete 233 folded constant-pool loads, but add 350. Can't tell yet if there is some missing combines..


Repository:
  rL LLVM

https://reviews.llvm.org/D62341

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/sink-addsub-of-const.ll
  test/CodeGen/AArch64/vec_cttz.ll
  test/CodeGen/AMDGPU/sub.v2i16.ll
  test/CodeGen/Mips/msa/arithmetic.ll
  test/CodeGen/Mips/msa/i5-s.ll
  test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
  test/CodeGen/PowerPC/vec_add_sub_quadword.ll
  test/CodeGen/PowerPC/vec_splat.ll
  test/CodeGen/X86/avx-shift.ll
  test/CodeGen/X86/avx2-shift.ll
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/combine-sub.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/packss.ll
  test/CodeGen/X86/prefer-avx256-lzcnt.ll
  test/CodeGen/X86/sadd_sat_vec.ll
  test/CodeGen/X86/sink-addsub-of-const.ll
  test/CodeGen/X86/ssub_sat_vec.ll
  test/CodeGen/X86/vec_ctbits.ll
  test/CodeGen/X86/vector-fshl-128.ll
  test/CodeGen/X86/vector-fshl-256.ll
  test/CodeGen/X86/vector-idiv-sdiv-128.ll
  test/CodeGen/X86/vector-idiv-sdiv-256.ll
  test/CodeGen/X86/vector-idiv-sdiv-512.ll
  test/CodeGen/X86/vector-lzcnt-128.ll
  test/CodeGen/X86/vector-lzcnt-256.ll
  test/CodeGen/X86/vector-lzcnt-512.ll
  test/CodeGen/X86/vector-shift-ashr-128.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll
  test/CodeGen/X86/vector-shift-ashr-512.ll
  test/CodeGen/X86/vector-shift-ashr-sub128-widen.ll
  test/CodeGen/X86/vector-shift-ashr-sub128.ll
  test/CodeGen/X86/vector-trunc-math-widen.ll
  test/CodeGen/X86/vector-trunc-math.ll
  test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
  test/CodeGen/X86/widen_arith-4.ll
  test/CodeGen/X86/widen_arith-5.ll
  test/CodeGen/X86/widen_cast-4.ll
  test/CodeGen/X86/x86-shifts.ll

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