[PATCH] D62355: AMDGPU: Activate all lanes when spilling CSR VGPR for SGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

If some lanes weren't active on entry to the function, this could
clobber their VGPR values.


https://reviews.llvm.org/D62355

Files:
  lib/Target/AMDGPU/SIFrameLowering.cpp
  test/CodeGen/AMDGPU/byval-frame-setup.ll
  test/CodeGen/AMDGPU/call-preserved-registers.ll
  test/CodeGen/AMDGPU/callee-frame-setup.ll
  test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  test/CodeGen/AMDGPU/nested-calls.ll
  test/CodeGen/AMDGPU/sibling-call.ll

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