[PATCH] D62223: [DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: craig.topper, RKSimon, spatel, arsenm.
lebedev.ri added a project: LLVM.
Herald added subscribers: kristof.beyls, t-tye, tpr, dstuttard, javed.absar, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.

The main motivation is shown by all these `neg` instructions that are now created.
In particular, the `@reg32_lshr_by_negated_unfolded_sub_b` test.

AArch64 test changes all look good (`neg` created), or neutral.

X86 changes look neutral (vectors), or good (`neg` / `xor eax, eax` created).

I'm not sure about `X86/ragreedy-hoist-spill.ll`, it looks like the spill
is now hoisted into preheader (which should still be good?),
2 4-byte reloads become 1 8-byte reload, and are elsewhere,
but i'm not sure how that affects that loop.

I'm unable to interpret AMDGPU change, looks neutral-ish?

This is hopefully a step towards solving PR41952 <https://bugs.llvm.org/show_bug.cgi?id=41952>.

https://rise4fun.com/Alive/pkdq (we are missing more patterns, i'll submit them later)


Repository:
  rL LLVM

https://reviews.llvm.org/D62223

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/shift-amount-mod.ll
  test/CodeGen/AArch64/sink-addsub-of-const.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
  test/CodeGen/X86/combine-add.ll
  test/CodeGen/X86/ragreedy-hoist-spill.ll
  test/CodeGen/X86/shift-amount-mod.ll
  test/CodeGen/X86/sink-addsub-of-const.ll
  test/CodeGen/X86/zext-sext.ll

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