[PATCH] D62024: [InstCombine] fold shuffles of insert_subvectors

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D62024#1508980 <https://reviews.llvm.org/D62024#1508980>, @efriedma wrote:

> > So IIUC, this is always the 1st option that you listed: legal destination type with vector widening, so the backend shouldn't ever see a difference.
>
> Did you try any testcases with integer types?  floats can't be "promoted", but integers can.


Yes - looks like the same concat_vectors pattern to me:

    t9: v4i32 = concat_vectors t6, undef:v2i32
    t8: v4i32 = concat_vectors t5, undef:v2i32
  t10: v4i32 = vector_shuffle<1,5,4,0> t9, t8
  
    t9: v8i16 = concat_vectors t7, undef:v4i16
    t10: v8i16 = concat_vectors t6, undef:v4i16
  t11: v8i16 = vector_shuffle<1,9,10,0,1,1,11,3> t9, t10

I also tried with an odd input type (<3 x i32>) to a legal type (<4x i32>), and that has extra ops on initial DAG, but it's still identical between the 2 proposed IR variants:

        t7: v3i32 = extract_subvector t4, Constant:i64<0>
      t9: v6i32 = concat_vectors t7, undef:v3i32
        t6: v3i32 = extract_subvector t2, Constant:i64<0>
      t10: v6i32 = concat_vectors t6, undef:v3i32
    t11: v6i32 = vector_shuffle<1,7,6,0,u,u> t9, t10
  t12: v4i32 = extract_subvector t11, Constant:i64<0>

I need to update my local repo to confirm, but this case exposes an existing crash for AArch64 codegen.


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