[PATCH] D61812: [AMDGPU] Fixed handling of imemdiate i1 literals

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:2526
   switch (Imm.getBitWidth()) {
+  case 1: // This likely will be a condition code mask.
+    return false;
----------------
arsenm wrote:
> rampitec wrote:
> > arsenm wrote:
> > > I don’t understand where this is coming from. There should be no 1-bit immediates anywhere?
> > Combiner sometimes produces "xor x, true", and even "add x, true". This is not the first time we hit it, we have even implemented lowering.
> I would expect this to be extended to the wavesize during selection
I guess that wouldn't provide much benefit, but this should always be true?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61812/new/

https://reviews.llvm.org/D61812