[PATCH] D61882: [ARM] Don't use the Machine Scheduler for cortex-m at minsize

Tue May 14 04:19:04 PDT 2019

fhahn added a comment.

This looks like an interesting case! I think there are 2 things going wrong (see input to the scheduler below)

1. The scheduler does not know it would be beneficial to keep things in the lower registers (the instructions mostly use the GPR/GPRNOPC classes). We could tweak the RegPressureSetLimits for Oz.
2. We add nodes that reduce register pressure to the available queue too late, because currently we only move from pending to available when we reached the ReadyCycle for in-order CPUs. This means we end up in a situation in which we have to schedule a node that further increases reg pressure.

While the patch is a quick fix, I think we should properly address those issues. Would you mind creating a bug report?

  bb.0.entry:
    liveins: $r0, $r1
    %1:rgpr = COPY $r1
    %0:gpr = COPY $r0
    %2:rgpr = t2LSRri %1:rgpr, 8, 14, $noreg, $noreg
    %3:gprnopc = t2LDRi12 %0:gpr, 16, 14, $noreg :: (load 4 from %ir.msg_out)
    %4:rgpr = t2LDRHi12 %0:gpr, 20, 14, $noreg :: (load 2 from %ir.options_out_len, align 4)
    %5:rgpr = t2ADDri %4:rgpr, 1, 14, $noreg, $noreg
    t2STRHi12 %5:rgpr, %0:gpr, 20, 14, $noreg :: (store 2 into %ir.options_out_len, align 4)
    %6:gprnopc = t2ADDrr %3:gprnopc, %4:rgpr, 14, $noreg, $noreg
    t2STRBi12 %2:rgpr, %6:gprnopc, 240, 14, $noreg :: (store 1 into %ir.arrayidx)
    %7:gprnopc = t2LDRi12 %0:gpr, 16, 14, $noreg :: (load 4 from %ir.msg_out)
    %8:rgpr = t2LDRHi12 %0:gpr, 20, 14, $noreg :: (load 2 from %ir.options_out_len, align 4)
    %9:rgpr = t2ADDri %8:rgpr, 1, 14, $noreg, $noreg
    t2STRHi12 %9:rgpr, %0:gpr, 20, 14, $noreg :: (store 2 into %ir.options_out_len, align 4)
    %10:gprnopc = t2ADDrr %7:gprnopc, %8:rgpr, 14, $noreg, $noreg
    t2STRBi12 %1:rgpr, %10:gprnopc, 240, 14, $noreg :: (store 1 into %ir.arrayidx10)
    tBX_RET 14, $noreg

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61882/new/

https://reviews.llvm.org/D61882