[PATCH] D61887: [SelectionDAG] computeKnownBits - support constant pool values from target

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: spatel, efriedma, craig.topper, niravd, andreadb, nikic.
Herald added a project: LLVM.

This patch adds the overridable TargetLowering::getTargetConstantFromLoad function which allows targets to return any constant value loaded by a LoadSDNode node - only X86 makes use of this so far but everything should be in place for other targets.

computeKnownBits then uses this function to improve codegen, notably vector code after legalization.

A future commit will do the same for ComputeNumSignBits but computeKnownBits sees the bigger benefit.

This required a couple of fixes:

- SimplifyDemandedBits must early-out for getTargetConstantFromLoad cases to prevent infinite loops of constant regeneration (similar to what we already do for BUILD_VECTOR).
- Fix a AVX512 regression as we had trunc(shl(v8i32),v8i16) <-> shl(trunc(v8i16),v8i32) infinite loops after legalization.


Repository:
  rL LLVM

https://reviews.llvm.org/D61887

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/X86/avx512-vec-cmp.ll
  test/CodeGen/X86/bitreverse.ll
  test/CodeGen/X86/combine-bitreverse.ll
  test/CodeGen/X86/combine-shl.ll
  test/CodeGen/X86/movmsk-cmp.ll
  test/CodeGen/X86/sadd_sat_vec.ll
  test/CodeGen/X86/ssub_sat_vec.ll
  test/CodeGen/X86/vector-bitreverse.ll
  test/CodeGen/X86/vector-pcmp.ll
  test/CodeGen/X86/vector-reduce-mul-widen.ll
  test/CodeGen/X86/vector-reduce-mul.ll
  test/CodeGen/X86/vector-shift-lshr-sub128.ll
  test/CodeGen/X86/vector-zext.ll

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