[llvm] r360588 - [X86] Add SimplifyDemandedBits support for PEXTRB/PEXTRW (PR39709)

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon May 13 08:31:27 2019
New Revision: 360588

URL: http://llvm.org/viewvc/llvm-project?rev=360588&view=rev
Log:
[X86] Add SimplifyDemandedBits support for PEXTRB/PEXTRW (PR39709)

Test case will be included in a followup - its being used but its tricky to show a case that isn't caught at a later stage anyway.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=360588&r1=360587&r2=360588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 13 08:31:27 2019
@@ -35112,8 +35112,13 @@ static SDValue combineExtractVectorElt(S
   // X86ISD::PEXTRW/X86ISD::PEXTRB in:
   // XFormVExtractWithShuffleIntoLoad, combineHorizontalPredicateResult and
   // combineBasicSADPattern.
-  if (IsPextr)
+  if (IsPextr) {
+    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+    if (TLI.SimplifyDemandedBits(
+            SDValue(N, 0), APInt::getAllOnesValue(VT.getSizeInBits()), DCI))
+      return SDValue(N, 0);
     return SDValue();
+  }
 
   if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
     return NewOp;