[PATCH] D61843: [DAGCombine] Match a pattern where a wide type scalar value is stored by several narrow stores

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added a comment.

That was discussed widely when https://reviews.llvm.org/D26149 is reviewed. This is the commit log saying something about the delay.

  This optimization was discussed on llvm-dev some time ago in "Load combine pass" thread. We came to the conclusion that we want to do
  this transformation late in the pipeline because in presence of atomic loads load widening is irreversible transformation and it might hinder other optimizations.
      
  Eventually we'd like to support folding patterns like this where the offset has a variable and a constant part:
  i32 val = a[i] | (a[i + 1] << 8) | (a[i + 2] << 16) | (a[i + 3] << 24)
  
  Matching the pattern above is easier at SelectionDAG level since address reassociation has already happened and the fact that the loads are adjacent is clear. Understanding that these loads are adjacent at IR level would have involved looking through geps/zexts/adds while looking at the addresses.
  
  The general scheme is to match OR expressions by recursively calculating the origin of individual bytes which constitute the resulting OR value. If all the OR bytes come from memory verify that they are adjacent and match with little or big endian encoding of a wider value. If so and the load of the wider type (and bswap if needed) is allowed by the target generate a load and a bswap if needed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61843/new/

https://reviews.llvm.org/D61843