[PATCH] D60052: Add Connex vector processor back end

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

This still needs a lot of work before it will be in a committable state. All of the parts touching generic code need to be reviewed and committed separately at an absolute minimum. The backend also could use some breaking up.

In particular the Value*/SDNode map doesn't in general make sense. What is it used for? It's certainly not the correct solution to whatever problem you're solving with it.



================
Comment at: include/llvm/Analysis/ScalarEvolutionExpander.h:264-272
+    Instruction *getInsertPoint() {
+      return &(*Builder.GetInsertPoint());
+    }
+
+    void setInsertPoint(BasicBlock *bb, BasicBlock::iterator ip) {
+      Builder.SetInsertPoint(bb, ip);
+    }
----------------
SCEV changes need to be split to separate patches


================
Comment at: include/llvm/CodeGen/SelectionDAG.h:273-277
+  DenseMap<const Value*, SDValue> *crtNodeMapPtr;
+
+  void SetNodeMap(DenseMap<const Value *, SDValue> *aCrtNodeMapPtr);
+
+  void UpdateNodeMapSDValue(SDNode *oldSDN, SDValue &newSDV);
----------------
This still needs to be dropped


================
Comment at: lib/CodeGen/LiveRangeCalc.cpp:25-38
+// Alex: new code
+// Assuming current include folder is llvm/lib/CodeGen (NOT in include)
+// NOT working: #include "ConnexGenInstrInfo.inc"
+#define GET_INSTRINFO_ENUM
+#include "/home/asusu/LLVM/llvm2019_03_29/llvm/lib/Target/Connex/ConnexGenInstrInfo.inc" // small-MEGA-TODO: this include is specific to my desktop...
+// NOT really good: #include "../Target/Connex/ConnexGenInstrInfo.inc" // This uses a temporary file
+/*
----------------
This needs to be removed


================
Comment at: lib/CodeGen/RegAllocGreedy.cpp:1223-1224
       }
-
+// Alex: new code
+// Alex: END new code
       // Abort if the spill cannot be inserted at the MBB' start
----------------
Needs to be removed


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1472-1473
 
+    // Replacing SDNode N with RV in crtNodeMap
+    DAG.UpdateNodeMapSDValue(N, RV);
+
----------------
Needs to be removed


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:85
 
+void SelectionDAG::SetNodeMap(DenseMap<const Value *, SDValue> *aCrtNodeMapPtr) {
+  crtNodeMapPtr = aCrtNodeMapPtr;
----------------
Ditto


================
Comment at: lib/Target/Connex/ConnexAsmPrinter.cpp:79-86
+  /*
+  (From http://llvm.org/docs/doxygen/html/classllvm_1_1MachineFunctionPass.html
+     we see SelectionDAGISel and AsmPrinter were the only passes that inherit
+     MachineFunctionPass, from this back end.)
+  From http://llvm.org/docs/doxygen/html/AsmPrinter_8h_source.html:
+    /// Set up the AsmPrinter when we are working on a new module. If your pass
+    /// overrides this, it must make sure to explicitly call this implementation.
----------------
These various places linking to other documentation should be removed. Doxygen generates the appropriate links


================
Comment at: lib/Target/Connex/ConnexAsmPrinter.cpp:104-117
+    /*
+    const char *str = strRef.data();
+
+    if ((strncmp(str, STR_VECTOR_BODY,
+                              strlen(STR_VECTOR_BODY)) == 0) &&
+        (strncmp(str + strlen(str) - strlen(STR_VECTOR_BODY_PREHEADER),
+                          STR_VECTOR_BODY_PREHEADER,
----------------
Remove commented out code


================
Comment at: lib/Target/Connex/ConnexAsmPrinter.cpp:780-782
+//#define TRY_DFS
+#ifdef TRY_DFS
+#define RPO
----------------
More macros to remove


================
Comment at: lib/Target/Connex/Select_SUBi32_OpincaaCodeGen.h:1-6
+//===-- Select_SUBi32_OpincaaCodeGen.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
----------------
This file needs to be dropped. There should be no committed, generated code. You should have table gen emit this, or manually write the code in ISelDAGToDAG


Repository:
  rL LLVM

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  https://reviews.llvm.org/D60052/new/

https://reviews.llvm.org/D60052