[PATCH] D61515: [AArch64][SVE2] Asm: add SQRDMLAH/SQRDMLSH instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


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Comment at: test/MC/AArch64/SVE2/sqrdmlah-diagnostics.s:8
+sqrdmlah z0.h, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqrdmlah z0.h, z1.h, z8.h[0]
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rovka wrote:
> Why not "error: Invalid restricted vector register, expected z0.h..z7.h" ?
This is being parsed as the vector form of the instruction where everything until the index is invalid, I guess it's hitting that error first. I agree it's a poor diagnostic, I'll see if this can be improved.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D61515/new/

https://reviews.llvm.org/D61515