[llvm] r360123 - AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand

[Nicolai Haehnle via llvm-commits]

Author: nha
Date: Tue May  7 02:19:09 2019
New Revision: 360123

URL: http://llvm.org/viewvc/llvm-project?rev=360123&view=rev
Log:
AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand

Summary:
No test case because I don't know of a way to trigger this, but I
accidentally caused this to fail while working on a different change.

Change-Id: I8015aa447fe27163cc4e4902205a203bd44bf7e3

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61490

Added:
    llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=360123&r1=360122&r2=360123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Tue May  7 02:19:09 2019
@@ -3191,6 +3191,24 @@ bool SIInstrInfo::verifyInstruction(cons
     }
   }
 
+  if (isSOP2(MI) || isSOPC(MI)) {
+    const MachineOperand &Src0 = MI.getOperand(Src0Idx);
+    const MachineOperand &Src1 = MI.getOperand(Src1Idx);
+    unsigned Immediates = 0;
+
+    if (!Src0.isReg() &&
+        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
+      Immediates++;
+    if (!Src1.isReg() &&
+        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
+      Immediates++;
+
+    if (Immediates > 1) {
+      ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
+      return false;
+    }
+  }
+
   if (isSOPK(MI)) {
     auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
     if (Desc.isBranch()) {

Added: llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir?rev=360123&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir Tue May  7 02:19:09 2019
@@ -0,0 +1,21 @@
+# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: S_CMP_EQ_U32
+
+# CHECK-NOT: Bad machine code
+
+---
+name: sop2_sopc
+tracksRegLiveness: true
+body: |
+  bb.0:
+    %0:sreg_32_xm0 = S_ADD_I32 2011, -113, implicit-def $scc
+    S_CMP_EQ_U32 2011, -113, implicit-def $scc
+
+    %1:sreg_32_xm0 = S_SUB_I32 2011, 10, implicit-def $scc
+    S_CMP_LG_U32 -5, 2011, implicit-def $scc
+...