[PATCH] D61575: AMDGPU: Select VOP3 form of add

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

The VOP3 form should always be the preferred selection form to be
shrunk later. This should only be an optimization issue, but this
partially works around a problem from clobbering VCC when
IFixSGPRCopies rewrites an SCC defining operation directly to VCC.

      

3 of the testcases are regressions from failing to fold the immediate
in cases it should. These can be avoided by improving the VCC liveness
handling in SIFoldOperands. Simply increasing the threshold to
computeRegisterLiveness works, although this is common enough that VCC
liveness should probably be tracked throughout the pass. The hack of
leaving behind an implicit_def instruction to avoid breaking iterator
wastes instruction count, which inhibits finding the VCC def in long
chains of adds. Doing this however exposes different, worse looking
regressions from poor scheduling behavior. This could probably be
avoided around by forcing the shrink of the addc here, but the
scheduler should probably be fixed.

      

The r600 add test needs to be split out because it asserts on the
arguments in the new test during the calling convention lowering.


https://reviews.llvm.org/D61575

Files:
  lib/Target/AMDGPU/VOP2Instructions.td
  test/CodeGen/AMDGPU/add.ll
  test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
  test/CodeGen/AMDGPU/fence-barrier.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
  test/CodeGen/AMDGPU/r600.add.ll
  test/CodeGen/AMDGPU/salu-to-valu.ll

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