[PATCH] D57857: [PowerPC] custom lower `v2f64 fpext v2f32`

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

Other than a few minor nits that can be addressed on the commit, LGTM.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9599
+  switch (Op0.getOpcode()) {
+  default:
+    return SDValue();
----------------
In a subsequent patch, we should probably add FP unary operations here as well.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9619
+    }
+    SDValue newOp = DAG.getNode(Op0.getOpcode(), SDLoc(Op0), MVT::v4f32,
+                              NewLoad[0], NewLoad[1],
----------------
nit: naming convention (`NewOp`).


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:3307
+  def : Pat<(v4f32 (PPCldvsxlh xaddr:$src)),
+            (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VRRC)>;
+  def : Pat<(v4f32 (PPCldvsxlh ixaddr:$src)),
----------------
These should copy into `VSRC` rather than `VRRC` so as to avoid unnecessary copies. It is very important to get these into the right register class as the extra copies will certainly reduce the performance impact of this transformation.


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  https://reviews.llvm.org/D57857/new/

https://reviews.llvm.org/D57857