[PATCH] D61472: [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

INC/DEC is really a special case of a more generic issue. We should also turn leas into add reg/reg or add reg/imm regardless of the slow lea flags.

This also supports LEA64_32 which has 64 bit input registers and 32 bit output registers. So we need to convert the 64 bit inputs to their 32 bit equivalents to check if they are equal to base reg.

One thing to note, the original code preserved the kill flags by adding operands to the new instruction instead of using addReg. But I think tied operands aren't supposed to have the kill flag set. I dropped the kill flags, but I could probably try to preserve it in the add reg/reg case if we think its important. Not sure which operand its supposed to go on for the LEA64_32r instruction due to the super reg implicit uses. Though I'm also not sure those are needed since they were probably just created by an INSERT_SUBREG from a 32-bit input.


https://reviews.llvm.org/D61472

Files:
  llvm/lib/Target/X86/X86FixupLEAs.cpp
  llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
  llvm/test/CodeGen/X86/GlobalISel/callingconv.ll
  llvm/test/CodeGen/X86/GlobalISel/gep.ll
  llvm/test/CodeGen/X86/GlobalISel/memop-scalar.ll
  llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
  llvm/test/CodeGen/X86/atomic-unordered.ll
  llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/bswap_tree2.ll
  llvm/test/CodeGen/X86/bypass-slow-division-32.ll
  llvm/test/CodeGen/X86/combine-srem.ll
  llvm/test/CodeGen/X86/dagcombine-shifts.ll
  llvm/test/CodeGen/X86/fixup-bw-copy.ll
  llvm/test/CodeGen/X86/fixup-lea.ll
  llvm/test/CodeGen/X86/imul.ll
  llvm/test/CodeGen/X86/leaFixup32.mir
  llvm/test/CodeGen/X86/leaFixup64.mir
  llvm/test/CodeGen/X86/mul-constant-i16.ll
  llvm/test/CodeGen/X86/mul-constant-i32.ll
  llvm/test/CodeGen/X86/mul-constant-i64.ll
  llvm/test/CodeGen/X86/mul-constant-i8.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/reverse_branches.ll
  llvm/test/CodeGen/X86/rotate-extract.ll
  llvm/test/CodeGen/X86/sat-add.ll
  llvm/test/CodeGen/X86/twoaddr-lea.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/win_coreclr_chkstk.ll
  llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll

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