[PATCH] D61398: [SDAG][AArch64] Boolean and/or reduce to umax/min reduce (PR41635)

[Nikita Popov via Phabricator via llvm-commits]

nikic created this revision.
nikic added reviewers: RKSimon, sdesmalen, aemerson, efriedma.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This addresses one half of https://bugs.llvm.org/show_bug.cgi?id=41635 by combining a VECREDUCE_AND into VECREDUCE_UMIN (if latter legal but former not) for zero-or-all-ones boolean reductions. I'm using sign bits to detect that, is there a better way to do that?


Repository:
  rL LLVM

https://reviews.llvm.org/D61398

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/vecreduce-bool.ll

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