[llvm] r359406 - [X86][SSE] combineExtractVectorElt - add early-out to return zero/undef for out-of-range extraction indices.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Apr 28 12:12:58 2019
New Revision: 359406

URL: http://llvm.org/viewvc/llvm-project?rev=359406&view=rev
Log:
[X86][SSE] combineExtractVectorElt - add early-out to return zero/undef for out-of-range extraction indices.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=359406&r1=359405&r2=359406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Apr 28 12:12:58 2019
@@ -34838,9 +34838,11 @@ static SDValue combineExtractVectorElt(S
   SDLoc dl(InputVector);
   bool IsPextr = N->getOpcode() != ISD::EXTRACT_VECTOR_ELT;
 
+  if (CIdx && CIdx->getAPIntValue().uge(SrcVT.getVectorNumElements()))
+    return IsPextr ? DAG.getConstant(0, dl, VT) : DAG.getUNDEF(VT);
+
   // Integer Constant Folding.
-  if (VT.isInteger() && CIdx &&
-      CIdx->getAPIntValue().ult(SrcVT.getVectorNumElements())) {
+  if (CIdx && VT.isInteger()) {
     APInt UndefVecElts;
     SmallVector<APInt, 16> EltBits;
     unsigned VecEltBitWidth = SrcVT.getScalarSizeInBits();