[PATCH] D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


================
Comment at: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:128
+  // %pcrel_lo, so they can be safely resolved.
+  for (const MCFixup *Fixup : UnknownFixups) {
+    EvaluatedFixups[Fixup] = true;
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rogfer01 wrote:
> Would this hold if the resolution of https://github.com/riscv/riscv-elf-psabi-doc/issues/90 is that a `%pcrel_lo` can cross sections?
> 
> Perhaps I got this wrong, but I understand that this process is currently section-wise, so we can't say much about a `%pcrel_hi` not being referenced by any `%pcrel_lo` in the same section, can we?
Sorry for the delay, yes this is a completely section-wise process. If the resolution allowed the pcrel to cross sections this patch would not be sufficient and the fix would require storing references to fixups between sections, which couldn't really be done in a neat way.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D58843/new/

https://reviews.llvm.org/D58843