[llvm] r359013 - [AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode

[Jessica Paquette via llvm-commits]

Author: paquette
Date: Tue Apr 23 10:17:06 2019
New Revision: 359013

URL: http://llvm.org/viewvc/llvm-project?rev=359013&view=rev
Log:
[AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode

Noticed an unnecessary fallback in arm64-vmul caused by this.

Also add a regbankselect test for G_FMA.

Added:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=359013&r1=359012&r2=359013&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Tue Apr 23 10:17:06 2019
@@ -389,6 +389,7 @@ static bool isPreISelGenericFloatingPoin
   case TargetOpcode::G_FADD:
   case TargetOpcode::G_FSUB:
   case TargetOpcode::G_FMUL:
+  case TargetOpcode::G_FMA:
   case TargetOpcode::G_FDIV:
   case TargetOpcode::G_FCONSTANT:
   case TargetOpcode::G_FPEXT:

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir?rev=359013&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir Tue Apr 23 10:17:06 2019
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
+
+...
+---
+
+name:            fma_f32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $s0, $s1, $s2
+
+    ; CHECK-LABEL: name: fma_f32
+    ; CHECK: liveins: $s0, $s1, $s2
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s1
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s2
+    ; CHECK: %3:fpr(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: $s0 = COPY %3(s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:_(s32) = COPY $s0
+    %1:_(s32) = COPY $s1
+    %2:_(s32) = COPY $s2
+    %3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
+    $s0 = COPY %3(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
+name:            fma_f64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0, $d1, $d2
+
+    ; CHECK-LABEL: name: fma_f64
+    ; CHECK: liveins: $d0, $d1, $d2
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d1
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d2
+    ; CHECK: %3:fpr(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: $d0 = COPY %3(s64)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %0:_(s64) = COPY $d0
+    %1:_(s64) = COPY $d1
+    %2:_(s64) = COPY $d2
+    %3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
+    $d0 = COPY %3(s64)
+    RET_ReallyLR implicit $d0
+
+...