[PATCH] D61019: [AggressiveAntiDepBreaker] Handle predicate operands better

[James Molloy via Phabricator via llvm-commits]

jmolloy created this revision.
jmolloy added a reviewer: hfinkel.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

[note: I tried hard to make a test for this. I thought Hexagon might be a good target, but alas it has a control register that aliases all of its predicate registers, which makes AggressiveAntiDependencyBreaker bail out even after this patch]

For targets that have a predicate register class, we want to be able to break antidepedencies in that regclass. This patch enhances AggressiveAntiDepBreaker to understand that even though an instruction is predicated, it may still unconditionally read the predicate operand and so can be handled by the existing logic.

To do this, a target hook is created. No test as no targets have this functionality.


Repository:
  rL LLVM

https://reviews.llvm.org/D61019

Files:
  include/llvm/CodeGen/TargetInstrInfo.h
  lib/CodeGen/AggressiveAntiDepBreaker.cpp


Index: lib/CodeGen/AggressiveAntiDepBreaker.cpp
===================================================================
--- lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -463,8 +463,8 @@
   // instruction which may not be executed. The second R6 def may or may not
   // re-define R6 so it's not safe to change it since the last R6 use cannot be
   // changed.
-  bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() ||
-                 TII->isPredicated(MI) || MI.isInlineAsm();
+  bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() || MI.isInlineAsm();
+  bool IsPredicated = TII->isPredicated(MI);
 
   // Scan the register uses for this instruction and update
   // live-ranges, groups and RegRefs.
@@ -486,6 +486,10 @@
       LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
       State->UnionGroups(Reg, 0);
     }
+    if (IsPredicated && !TII->isOperandUseGuaranteed(MI, Reg)) {
+      LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(predicated)");
+      State->UnionGroups(Reg, 0);
+    }
 
     // Note register reference...
     const TargetRegisterClass *RC = nullptr;
Index: include/llvm/CodeGen/TargetInstrInfo.h
===================================================================
--- include/llvm/CodeGen/TargetInstrInfo.h
+++ include/llvm/CodeGen/TargetInstrInfo.h
@@ -1246,6 +1246,14 @@
     return MI.getDesc().isPredicable();
   }
 
+  /// Reg is used in MI. Return true if Reg is always guaranteed to be read by
+  /// MI. For example, a predicated instruction may not use its operand
+  /// registers if the predicate is false. But a predicated instruction would
+  /// always use its predicate operand.
+  virtual bool isOperandUseGuaranteed(const MachineInstr &MI, unsigned Reg) {
+    return false;
+  }
+
   /// Return true if it's safe to move a machine
   /// instruction that defines the specified register class.
   virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {


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