[PATCH] D60999: AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle created this revision.
nhaehnle added a reviewer: llvm-commits.
Herald added subscribers: t-tye, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

When an LCSSA phi survives through instruction selection, the pass
ends up removing that phi entirely because it is dominated by the
logic that does the lanemask merging.

This then used to trigger an assertion when processing a dependent
phi instruction.

Change-Id: Id4949719f8298062fe476a25718acccc109113b6


Repository:
  rL LLVM

https://reviews.llvm.org/D60999

Files:
  lib/Target/AMDGPU/SILowerI1Copies.cpp
  test/CodeGen/AMDGPU/si-lower-i1-copies.mir


Index: test/CodeGen/AMDGPU/si-lower-i1-copies.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/si-lower-i1-copies.mir
@@ -0,0 +1,33 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s
+
+# GCN-LABEL: name: lcssa_phi
+---
+name:              lcssa_phi
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %0:sreg_64 = S_MOV_B64 0
+    %8:vreg_1 = IMPLICIT_DEF
+    %10:sreg_64 = IMPLICIT_DEF
+    %11:sreg_64 = SI_IF %10, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1:
+    %1:sreg_64 = PHI %0, %bb.0, %3, %bb.1
+    %2:sreg_64 = IMPLICIT_DEF
+    %3:sreg_64 = SI_IF_BREAK %2, %1, implicit-def dead $scc
+    %4:sreg_64 = IMPLICIT_DEF
+    %5:vreg_1 = COPY %4
+    SI_LOOP %3, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+
+  bb.2:
+    %6:vreg_1 = PHI %5, %bb.1
+    SI_END_CF %3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+
+  bb.3:
+    %7:vreg_1 = PHI %6, %bb.2, %8, %bb.0
+    SI_END_CF %11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_ENDPGM 0
+
+...
Index: lib/Target/AMDGPU/SILowerI1Copies.cpp
===================================================================
--- lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -504,6 +504,9 @@
   SmallVector<MachineBasicBlock *, 4> IncomingBlocks;
   SmallVector<unsigned, 4> IncomingRegs;
   SmallVector<unsigned, 4> IncomingUpdated;
+#ifndef NDEBUG
+  DenseSet<unsigned> PhiRegisters;
+#endif
 
   for (MachineBasicBlock &MBB : *MF) {
     LF.initialize(MBB);
@@ -531,13 +534,17 @@
         } else if (IncomingDef->getOpcode() == AMDGPU::IMPLICIT_DEF) {
           continue;
         } else {
-          assert(IncomingDef->isPHI());
+          assert(IncomingDef->isPHI() || PhiRegisters.count(IncomingReg));
         }
 
         IncomingBlocks.push_back(IncomingMBB);
         IncomingRegs.push_back(IncomingReg);
       }
 
+#ifndef NDEBUG
+      PhiRegisters.insert(DstReg);
+#endif
+
       // Phis in a loop that are observed outside the loop receive a simple but
       // conservatively correct treatment.
       MachineBasicBlock *PostDomBound = &MBB;


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