[PATCH] D60214: [DAGCombiner] move splat-shuffle after binop with splat constant

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 195593.
spatel added a comment.
This revision is now accepted and ready to land.

Patch updated:
Made ARM test checks more exact, so we can see there actually is an extra instruction here (vext.32). That seems like a regression, but I'm not sure if it's important and/or another known shortcoming for folding shuffles.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60214/new/

https://reviews.llvm.org/D60214

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/ARM/reg_sequence.ll
  llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
  llvm/test/CodeGen/X86/scalarize-fp.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umin.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128-widen.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-sub128-widen.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll

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