[llvm] r358552 - Revert "Temporarily Revert "Add basic loop fusion pass.""
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 16 21:53:01 PDT 2019
Added: llvm/trunk/test/Transforms/InstCombine/or-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or-fcmp.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/or-fcmp.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/or-fcmp.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1556 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i1 @PR1738(double %x, double %y) {
+; CHECK-LABEL: @PR1738(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp1 = fcmp uno double %x, 0.0
+ %cmp2 = fcmp uno double %y, 0.0
+ %or = or i1 %cmp1, %cmp2
+ ret i1 %or
+}
+
+define <2 x i1> @PR1738_vec_undef(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: @PR1738_vec_undef(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <2 x double> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+;
+ %cmp1 = fcmp uno <2 x double> %x, <double 0.0, double undef>
+ %cmp2 = fcmp uno <2 x double> %y, <double undef, double 0.0>
+ %or = or <2 x i1> %cmp1, %cmp2
+ ret <2 x i1> %or
+}
+
+define i1 @PR41069(double %a, double %b, double %c, double %d) {
+; CHECK-LABEL: @PR41069(
+; CHECK-NEXT: [[UNO1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[D:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[TMP1]], [[UNO1]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %uno1 = fcmp uno double %a, %b
+ %uno2 = fcmp uno double %c, 0.0
+ %or = or i1 %uno1, %uno2
+ %uno3 = fcmp uno double %d, 0.0
+ %r = or i1 %or, %uno3
+ ret i1 %r
+}
+
+define i1 @PR41069_commute(double %a, double %b, double %c, double %d) {
+; CHECK-LABEL: @PR41069_commute(
+; CHECK-NEXT: [[UNO1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[D:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[TMP1]], [[UNO1]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %uno1 = fcmp uno double %a, %b
+ %uno2 = fcmp uno double %c, 0.0
+ %or = or i1 %uno1, %uno2
+ %uno3 = fcmp uno double %d, 0.0
+ %r = or i1 %uno3, %or
+ ret i1 %r
+}
+
+define <2 x i1> @PR41069_vec(<2 x i1> %z, <2 x float> %c, <2 x float> %d) {
+; CHECK-LABEL: @PR41069_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <2 x float> [[D:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[TMP1]], [[Z:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %uno1 = fcmp uno <2 x float> %c, zeroinitializer
+ %or = or <2 x i1> %uno1, %z
+ %uno2 = fcmp uno <2 x float> %d, <float 0.0, float undef>
+ %r = or <2 x i1> %or, %uno2
+ ret <2 x i1> %r
+}
+
+define <2 x i1> @PR41069_vec_commute(<2 x i1> %z, <2 x float> %c, <2 x float> %d) {
+; CHECK-LABEL: @PR41069_vec_commute(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <2 x float> [[D:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[TMP1]], [[Z:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %uno1 = fcmp uno <2 x float> %c, zeroinitializer
+ %or = or <2 x i1> %uno1, %z
+ %uno2 = fcmp uno <2 x float> %d, <float 0.0, float undef>
+ %r = or <2 x i1> %uno2, %or
+ ret <2 x i1> %r
+}
+
+define i1 @fcmp_uno_nonzero(float %x, float %y) {
+; CHECK-LABEL: @fcmp_uno_nonzero(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno float [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp1 = fcmp uno float %x, 1.0
+ %cmp2 = fcmp uno float %y, 2.0
+ %or = or i1 %cmp1, %cmp2
+ ret i1 %or
+}
+
+define <3 x i1> @fcmp_uno_nonzero_vec(<3 x float> %x, <3 x float> %y) {
+; CHECK-LABEL: @fcmp_uno_nonzero_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <3 x float> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+;
+ %cmp1 = fcmp uno <3 x float> %x, <float 1.0, float 2.0, float 3.0>
+ %cmp2 = fcmp uno <3 x float> %y, <float 3.0, float 2.0, float 1.0>
+ %or = or <3 x i1> %cmp1, %cmp2
+ ret <3 x i1> %or
+}
+
+define i1 @auto_gen_0(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_0(
+; CHECK-NEXT: ret i1 false
+;
+ %cmp = fcmp false double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_1(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_1(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp oeq double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_2(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_2(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp oeq double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_3(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_3(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp ogt double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_4(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_4(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ogt double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_5(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_5(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ogt double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_6(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_6(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp oge double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_7(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_7(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp oge double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_8(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_8(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp oge double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_9(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_9(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp oge double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_10(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_10(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp olt double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_11(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_11(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp olt double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_12(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_12(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp olt double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_13(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_13(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp olt double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_14(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_14(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp olt double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_15(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_15(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp ole double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_16(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_16(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ole double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_17(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_17(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ole double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_18(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_18(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ole double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_19(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_19(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ole double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_20(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_20(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ole double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_21(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_21(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp one double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_22(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_22(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp one double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_23(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_23(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp one double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_24(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_24(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp one double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_25(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_25(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp one double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_26(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_26(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp one double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_27(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_27(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp one double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_28(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_28(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_29(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_29(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_30(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_30(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_31(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_31(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_32(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_32(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_33(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_33(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_34(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_34(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_35(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_35(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ord double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_36(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_36(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_37(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_37(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_38(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_38(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_39(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_39(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_40(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_40(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_41(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_41(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_42(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_42(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_43(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_43(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_44(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_44(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ueq double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_45(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_45(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_46(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_46(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_47(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_47(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_48(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_48(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_49(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_49(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_50(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_50(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_51(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_51(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_52(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_52(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_53(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_53(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_54(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_54(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ugt double %a, %b
+ %cmp1 = fcmp ugt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_55(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_55(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_56(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_56(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_57(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_57(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_58(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_58(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_59(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_59(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_60(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_60(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_61(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_61(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_62(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_62(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_63(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_63(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_64(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_64(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp ugt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_65(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_65(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uge double %a, %b
+ %cmp1 = fcmp uge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_66(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_66(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_67(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_67(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_68(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_68(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_69(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_69(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_70(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_70(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_71(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_71(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_72(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_72(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_73(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_73(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_74(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_74(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_75(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_75(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp ugt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_76(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_76(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp uge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_77(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_77(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ult double %a, %b
+ %cmp1 = fcmp ult double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_78(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_78(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_79(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_79(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_80(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_80(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_81(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_81(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_82(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_82(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_83(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_83(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_84(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_84(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_85(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_85(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_86(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_86(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_87(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_87(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp ugt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_88(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_88(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp uge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_89(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_89(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp ult double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_90(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_90(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp ule double %a, %b
+ %cmp1 = fcmp ule double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_91(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_91(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_92(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_92(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_93(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_93(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_94(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_94(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_95(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_95(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_96(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_96(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_97(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_97(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_98(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_98(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_99(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_99(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_100(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_100(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp ugt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_101(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_101(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp uge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_102(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_102(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp ult double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_103(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_103(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp ule double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_104(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_104(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp une double %a, %b
+ %cmp1 = fcmp une double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_105(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_105(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_106(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_106(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_107(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_107(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_108(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_108(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_109(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_109(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_110(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_110(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_111(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_111(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_112(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_112(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_113(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_113(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_114(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_114(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp ugt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_115(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_115(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp uge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_116(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_116(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp ult double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_117(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_117(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp ule double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_118(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_118(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp une double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_119(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_119(
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %cmp = fcmp uno double %a, %b
+ %cmp1 = fcmp uno double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_120(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_120(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp false double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_121(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_121(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp oeq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_122(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_122(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp ogt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_123(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_123(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp oge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_124(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_124(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp olt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_125(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_125(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp ole double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_126(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_126(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp one double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_127(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_127(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp ord double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_128(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_128(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp ueq double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_129(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_129(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp ugt double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_130(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_130(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp uge double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_131(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_131(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp ult double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_132(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_132(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp ule double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_133(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_133(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp une double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_134(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_134(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp uno double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
+
+define i1 @auto_gen_135(double %a, double %b) {
+; CHECK-LABEL: @auto_gen_135(
+; CHECK-NEXT: ret i1 true
+;
+ %cmp = fcmp true double %a, %b
+ %cmp1 = fcmp true double %a, %b
+ %retval = or i1 %cmp, %cmp1
+ ret i1 %retval
+}
Added: llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,221 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define i32 @or_and_shifts1(i32 %x) {
+; CHECK-LABEL: @or_and_shifts1(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 8
+; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 32
+; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %1 = shl i32 %x, 3
+ %2 = and i32 %1, 15
+ %3 = shl i32 %x, 5
+ %4 = and i32 %3, 60
+ %5 = or i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @or_and_shifts2(i32 %x) {
+; CHECK-LABEL: @or_and_shifts2(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 896
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 %x, 4
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 7
+; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %1 = shl i32 %x, 3
+ %2 = and i32 %1, 896
+ %3 = lshr i32 %x, 4
+ %4 = and i32 %3, 7
+ %5 = or i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @or_and_shift_shift_and(i32 %x) {
+; CHECK-LABEL: @or_and_shift_shift_and(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 56
+; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 2
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 28
+; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %1 = and i32 %x, 7
+ %2 = shl i32 %1, 3
+ %3 = shl i32 %x, 2
+ %4 = and i32 %3, 28
+ %5 = or i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @multiuse1(i32 %x) {
+; CHECK-LABEL: @multiuse1(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 6
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 384
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 3
+; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %1 = and i32 %x, 2
+ %2 = and i32 %x, 4
+ %3 = shl nuw nsw i32 %1, 6
+ %4 = lshr exact i32 %1, 1
+ %5 = shl nuw nsw i32 %2, 6
+ %6 = lshr exact i32 %2, 1
+ %7 = or i32 %3, %5
+ %8 = or i32 %4, %6
+ %9 = or i32 %8, %7
+ ret i32 %9
+}
+
+define i32 @multiuse2(i32 %x) {
+; CHECK-LABEL: @multiuse2(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 12
+; CHECK-NEXT: [[TMP3:%.*]] = shl i32 %x, 8
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 24576
+; CHECK-NEXT: [[TMP5:%.*]] = shl i32 %x, 8
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 7680
+; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP4]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = shl i32 %x, 1
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 240
+; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP2]], [[TMP9]]
+; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP7]], [[TMP10]]
+; CHECK-NEXT: ret i32 [[TMP11]]
+;
+ %1 = and i32 %x, 6
+ %2 = shl nuw nsw i32 %1, 8
+ %3 = shl nuw nsw i32 %1, 1
+ %4 = and i32 %x, 24
+ %5 = shl nuw nsw i32 %4, 8
+ %6 = shl nuw nsw i32 %4, 1
+ %7 = and i32 %x, 96
+ %8 = shl nuw nsw i32 %7, 8
+ %9 = shl nuw nsw i32 %7, 1
+ %10 = or i32 %2, %5
+ %11 = or i32 %8, %10
+ %12 = or i32 %9, %6
+ %13 = or i32 %3, %12
+ %14 = or i32 %11, %13
+ ret i32 %14
+}
+
+define i32 @multiuse3(i32 %x) {
+; CHECK-LABEL: @multiuse3(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 96
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 6
+; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = shl i32 %x, 6
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1920
+; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP2]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 15
+; CHECK-NEXT: [[TMP9:%.*]] = or i32 [[TMP3]], [[TMP8]]
+; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP6]]
+; CHECK-NEXT: ret i32 [[TMP10]]
+;
+ %1 = and i32 %x, 96
+ %2 = shl nuw nsw i32 %1, 6
+ %3 = lshr exact i32 %1, 1
+ %4 = shl i32 %x, 6
+ %5 = and i32 %4, 1920
+ %6 = or i32 %2, %5
+ %7 = lshr i32 %x, 1
+ %8 = and i32 %7, 15
+ %9 = or i32 %3, %8
+ %10 = or i32 %9, %6
+ ret i32 %10
+}
+
+define i32 @multiuse4(i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: @multiuse4(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 100663296
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 %x, -1
+; CHECK-NEXT: br i1 [[TMP2]], label %if, label %else
+; CHECK: {{.*}}if:{{.*}}
+; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP1]], 22
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 %x, 22
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 480
+; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}else:{{.*}}
+; CHECK-NEXT: [[TMP7:%.*]] = lshr exact i32 [[TMP1]], 17
+; CHECK-NEXT: [[TMP8:%.*]] = lshr i32 %x, 17
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 15360
+; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP7]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}end{{.*}}
+; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], %if ], [ [[TMP10]], %else ]
+; CHECK-NEXT: ret i32 [[TMP11]]
+;
+ %1 = and i32 %x, 100663296
+ %2 = icmp sgt i32 %x, -1
+ br i1 %2, label %if, label %else
+
+if:
+ %3 = lshr exact i32 %1, 22
+ %4 = lshr i32 %x, 22
+ %5 = and i32 %4, 480
+ %6 = or i32 %5, %3
+ br label %end
+
+else:
+ %7 = lshr exact i32 %1, 17
+ %8 = lshr i32 %x, 17
+ %9 = and i32 %8, 15360
+ %10 = or i32 %9, %7
+ br label %end
+
+end:
+ %11 = phi i32 [ %6, %if ], [ %10, %else ]
+ ret i32 %11
+}
+
+define i32 @multiuse5(i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: @multiuse5(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 %x, -1
+; CHECK-NEXT: br i1 [[TMP2]], label %if, label %else
+; CHECK: {{.*}}if:{{.*}}
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 21760
+; CHECK-NEXT: [[TMP4:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 43520
+; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}else:{{.*}}
+; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP1]], 5570560
+; CHECK-NEXT: [[TMP8:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 11141120
+; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP7]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}end{{.*}}
+; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], %if ], [ [[TMP10]], %else ]
+; CHECK-NEXT: ret i32 [[TMP11]]
+;
+ %1 = shl i32 %x, 5
+ %2 = icmp sgt i32 %x, -1
+ br i1 %2, label %if, label %else
+
+if:
+ %3 = and i32 %1, 21760
+ %4 = and i32 %x, 1360
+ %5 = shl nuw nsw i32 %4, 5
+ %6 = or i32 %5, %3
+ br label %end
+
+else:
+ %7 = and i32 %1, 5570560
+ %8 = and i32 %x, 348160
+ %9 = shl nuw nsw i32 %8, 5
+ %10 = or i32 %9, %7
+ br label %end
+
+end:
+ %11 = phi i32 [ %6, %if ], [ %10, %else ]
+ ret i32 %11
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/or-xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or-xor.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/or-xor.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/or-xor.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,416 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+; X | ~(X | Y) --> X | ~Y
+
+define i32 @test1(i32 %x, i32 %y) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[Y_NOT:%.*]] = xor i32 [[Y:%.*]], -1
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y_NOT]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %or = or i32 %x, %y
+ %not = xor i32 %or, -1
+ %z = or i32 %x, %not
+ ret i32 %z
+}
+
+; Commute (rename) the inner 'or' operands:
+; Y | ~(X | Y) --> ~X | Y
+
+define i32 @test2(i32 %x, i32 %y) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[X_NOT]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %or = or i32 %x, %y
+ %not = xor i32 %or, -1
+ %z = or i32 %y, %not
+ ret i32 %z
+}
+
+; X | ~(X ^ Y) --> X | ~Y
+
+define i32 @test3(i32 %x, i32 %y) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[Y_NOT:%.*]] = xor i32 [[Y:%.*]], -1
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y_NOT]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %xor = xor i32 %x, %y
+ %not = xor i32 %xor, -1
+ %z = or i32 %x, %not
+ ret i32 %z
+}
+
+; Commute (rename) the 'xor' operands:
+; Y | ~(X ^ Y) --> ~X | Y
+
+define i32 @test4(i32 %x, i32 %y) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[X_NOT]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %xor = xor i32 %x, %y
+ %not = xor i32 %xor, -1
+ %z = or i32 %y, %not
+ ret i32 %z
+}
+
+define i32 @test5(i32 %x, i32 %y) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: ret i32 -1
+;
+ %and = and i32 %x, %y
+ %not = xor i32 %and, -1
+ %z = or i32 %x, %not
+ ret i32 %z
+}
+
+define i32 @test6(i32 %x, i32 %y) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: ret i32 -1
+;
+ %and = and i32 %x, %y
+ %not = xor i32 %and, -1
+ %z = or i32 %y, %not
+ ret i32 %z
+}
+
+define i32 @test7(i32 %x, i32 %y) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %xor = xor i32 %x, %y
+ %z = or i32 %y, %xor
+ ret i32 %z
+}
+
+define i32 @test8(i32 %x, i32 %y) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: [[X_NOT:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[X_NOT]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %not = xor i32 %y, -1
+ %xor = xor i32 %x, %not
+ %z = or i32 %y, %xor
+ ret i32 %z
+}
+
+define i32 @test9(i32 %x, i32 %y) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: [[Y_NOT:%.*]] = xor i32 [[Y:%.*]], -1
+; CHECK-NEXT: [[Z:%.*]] = or i32 [[Y_NOT]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %not = xor i32 %x, -1
+ %xor = xor i32 %not, %y
+ %z = or i32 %x, %xor
+ ret i32 %z
+}
+
+define i32 @test10(i32 %A, i32 %B) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: ret i32 -1
+;
+ %xor1 = xor i32 %B, %A
+ %not = xor i32 %A, -1
+ %xor2 = xor i32 %not, %B
+ %or = or i32 %xor1, %xor2
+ ret i32 %or
+}
+
+define i32 @test10_commuted(i32 %A, i32 %B) {
+; CHECK-LABEL: @test10_commuted(
+; CHECK-NEXT: ret i32 -1
+;
+ %xor1 = xor i32 %B, %A
+ %not = xor i32 %A, -1
+ %xor2 = xor i32 %not, %B
+ %or = or i32 %xor2, %xor1
+ ret i32 %or
+}
+
+; (x | y) & ((~x) ^ y) -> (x & y)
+define i32 @test11(i32 %x, i32 %y) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[AND]]
+;
+ %or = or i32 %x, %y
+ %neg = xor i32 %x, -1
+ %xor = xor i32 %neg, %y
+ %and = and i32 %or, %xor
+ ret i32 %and
+}
+
+; ((~x) ^ y) & (x | y) -> (x & y)
+define i32 @test12(i32 %x, i32 %y) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[AND]]
+;
+ %neg = xor i32 %x, -1
+ %xor = xor i32 %neg, %y
+ %or = or i32 %x, %y
+ %and = and i32 %xor, %or
+ ret i32 %and
+}
+
+define i32 @test12_commuted(i32 %x, i32 %y) {
+; CHECK-LABEL: @test12_commuted(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[AND]]
+;
+ %neg = xor i32 %x, -1
+ %xor = xor i32 %neg, %y
+ %or = or i32 %y, %x
+ %and = and i32 %xor, %or
+ ret i32 %and
+}
+
+; ((x | y) ^ (x ^ y)) -> (x & y)
+define i32 @test13(i32 %x, i32 %y) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %1 = xor i32 %y, %x
+ %2 = or i32 %y, %x
+ %3 = xor i32 %2, %1
+ ret i32 %3
+}
+
+; ((x | ~y) ^ (~x | y)) -> x ^ y
+define i32 @test14(i32 %x, i32 %y) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %or1 = or i32 %x, %noty
+ %or2 = or i32 %notx, %y
+ %xor = xor i32 %or1, %or2
+ ret i32 %xor
+}
+
+define i32 @test14_commuted(i32 %x, i32 %y) {
+; CHECK-LABEL: @test14_commuted(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %or1 = or i32 %noty, %x
+ %or2 = or i32 %notx, %y
+ %xor = xor i32 %or1, %or2
+ ret i32 %xor
+}
+
+; ((x & ~y) ^ (~x & y)) -> x ^ y
+define i32 @test15(i32 %x, i32 %y) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %and1 = and i32 %x, %noty
+ %and2 = and i32 %notx, %y
+ %xor = xor i32 %and1, %and2
+ ret i32 %xor
+}
+
+define i32 @test15_commuted(i32 %x, i32 %y) {
+; CHECK-LABEL: @test15_commuted(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %and1 = and i32 %noty, %x
+ %and2 = and i32 %notx, %y
+ %xor = xor i32 %and1, %and2
+ ret i32 %xor
+}
+
+define i32 @test16(i32 %a, i32 %b) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 1
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %or = xor i32 %a, %b
+ %and1 = and i32 %or, 1
+ %and2 = and i32 %b, -2
+ %xor = or i32 %and1, %and2
+ ret i32 %xor
+}
+
+define i8 @not_or(i8 %x) {
+; CHECK-LABEL: @not_or(
+; CHECK-NEXT: [[NOTX:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[OR:%.*]] = xor i8 [[NOTX]], -8
+; CHECK-NEXT: ret i8 [[OR]]
+;
+ %notx = xor i8 %x, -1
+ %or = or i8 %notx, 7
+ ret i8 %or
+}
+
+define i8 @not_or_xor(i8 %x) {
+; CHECK-LABEL: @not_or_xor(
+; CHECK-NEXT: [[NOTX:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[NOTX]], -12
+; CHECK-NEXT: ret i8 [[XOR]]
+;
+ %notx = xor i8 %x, -1
+ %or = or i8 %notx, 7
+ %xor = xor i8 %or, 12
+ ret i8 %xor
+}
+
+define i8 @xor_or(i8 %x) {
+; CHECK-LABEL: @xor_or(
+; CHECK-NEXT: [[XOR:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[OR:%.*]] = xor i8 [[XOR]], 32
+; CHECK-NEXT: ret i8 [[OR]]
+;
+ %xor = xor i8 %x, 32
+ %or = or i8 %xor, 7
+ ret i8 %or
+}
+
+define i8 @xor_or2(i8 %x) {
+; CHECK-LABEL: @xor_or2(
+; CHECK-NEXT: [[XOR:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[OR:%.*]] = xor i8 [[XOR]], 32
+; CHECK-NEXT: ret i8 [[OR]]
+;
+ %xor = xor i8 %x, 33
+ %or = or i8 %xor, 7
+ ret i8 %or
+}
+
+define i8 @xor_or_xor(i8 %x) {
+; CHECK-LABEL: @xor_or_xor(
+; CHECK-NEXT: [[XOR1:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[XOR1]], 44
+; CHECK-NEXT: ret i8 [[XOR2]]
+;
+ %xor1 = xor i8 %x, 33
+ %or = or i8 %xor1, 7
+ %xor2 = xor i8 %or, 12
+ ret i8 %xor2
+}
+
+define i8 @or_xor_or(i8 %x) {
+; CHECK-LABEL: @or_xor_or(
+; CHECK-NEXT: [[XOR:%.*]] = or i8 [[X:%.*]], 39
+; CHECK-NEXT: [[OR2:%.*]] = xor i8 [[XOR]], 8
+; CHECK-NEXT: ret i8 [[OR2]]
+;
+ %or1 = or i8 %x, 33
+ %xor = xor i8 %or1, 12
+ %or2 = or i8 %xor, 7
+ ret i8 %or2
+}
+
+define i8 @test17(i8 %A, i8 %B) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
+; CHECK-NEXT: [[OR:%.*]] = or i8 [[XOR1]], 33
+; CHECK-NEXT: [[RES:%.*]] = mul i8 [[OR]], [[XOR2]]
+; CHECK-NEXT: ret i8 [[RES]]
+;
+ %xor1 = xor i8 %B, %A
+ %not = xor i8 %A, 33
+ %xor2 = xor i8 %not, %B
+ %or = or i8 %xor1, %xor2
+ %res = mul i8 %or, %xor2 ; to increase the use count for the xor
+ ret i8 %res
+}
+
+define i8 @test18(i8 %A, i8 %B) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
+; CHECK-NEXT: [[OR:%.*]] = or i8 [[XOR1]], 33
+; CHECK-NEXT: [[RES:%.*]] = mul i8 [[OR]], [[XOR2]]
+; CHECK-NEXT: ret i8 [[RES]]
+;
+ %xor1 = xor i8 %B, %A
+ %not = xor i8 %A, 33
+ %xor2 = xor i8 %not, %B
+ %or = or i8 %xor2, %xor1
+ %res = mul i8 %or, %xor2 ; to increase the use count for the xor
+ ret i8 %res
+}
+
+; ((x | y) ^ (~x | ~y)) -> ~(x ^ y)
+define i32 @test19(i32 %x, i32 %y) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %or1 = or i32 %x, %y
+ %or2 = or i32 %notx, %noty
+ %xor = xor i32 %or1, %or2
+ ret i32 %xor
+}
+
+; ((x | y) ^ (~y | ~x)) -> ~(x ^ y)
+define i32 @test20(i32 %x, i32 %y) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %or1 = or i32 %x, %y
+ %or2 = or i32 %noty, %notx
+ %xor = xor i32 %or1, %or2
+ ret i32 %xor
+}
+
+; ((~x | ~y) ^ (x | y)) -> ~(x ^ y)
+define i32 @test21(i32 %x, i32 %y) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %or1 = or i32 %notx, %noty
+ %or2 = or i32 %x, %y
+ %xor = xor i32 %or1, %or2
+ ret i32 %xor
+}
+
+; ((~x | ~y) ^ (y | x)) -> ~(x ^ y)
+define i32 @test22(i32 %x, i32 %y) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[XOR]]
+;
+ %noty = xor i32 %y, -1
+ %notx = xor i32 %x, -1
+ %or1 = or i32 %notx, %noty
+ %or2 = or i32 %y, %x
+ %xor = xor i32 %or1, %or2
+ ret i32 %xor
+}
Added: llvm/trunk/test/Transforms/InstCombine/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/or.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/or.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,843 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+define i32 @test12(i32 %A) {
+ ; Should be eliminated
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: [[C:%.*]] = and i32 [[A:%.*]], 8
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = or i32 %A, 4
+ %C = and i32 %B, 8
+ ret i32 %C
+}
+
+define i32 @test13(i32 %A) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: ret i32 8
+;
+ %B = or i32 %A, 12
+ ; Always equal to 8
+ %C = and i32 %B, 8
+ ret i32 %C
+}
+
+define i1 @test14(i32 %A, i32 %B) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %C1 = icmp ult i32 %A, %B
+ %C2 = icmp ugt i32 %A, %B
+ ; (A < B) | (A > B) === A != B
+ %D = or i1 %C1, %C2
+ ret i1 %D
+}
+
+define i1 @test15(i32 %A, i32 %B) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %C1 = icmp ult i32 %A, %B
+ %C2 = icmp eq i32 %A, %B
+ ; (A < B) | (A == B) === A <= B
+ %D = or i1 %C1, %C2
+ ret i1 %D
+}
+
+define i32 @test16(i32 %A) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: ret i32 [[A:%.*]]
+;
+ %B = and i32 %A, 1
+ ; -2 = ~1
+ %C = and i32 %A, -2
+ ; %D = and int %B, -1 == %B
+ %D = or i32 %B, %C
+ ret i32 %D
+}
+
+define i32 @test17(i32 %A) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[D:%.*]] = and i32 [[A:%.*]], 5
+; CHECK-NEXT: ret i32 [[D]]
+;
+ %B = and i32 %A, 1
+ %C = and i32 %A, 4
+ ; %D = and int %B, 5
+ %D = or i32 %B, %C
+ ret i32 %D
+}
+
+define i1 @test18(i32 %A) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: [[A_OFF:%.*]] = add i32 [[A:%.*]], -50
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[A_OFF]], 49
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %B = icmp sge i32 %A, 100
+ %C = icmp slt i32 %A, 50
+ %D = or i1 %B, %C
+ ret i1 %D
+}
+
+; FIXME: Vectors should fold too.
+define <2 x i1> @test18vec(<2 x i32> %A) {
+; CHECK-LABEL: @test18vec(
+; CHECK-NEXT: [[B:%.*]] = icmp sgt <2 x i32> [[A:%.*]], <i32 99, i32 99>
+; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[A]], <i32 50, i32 50>
+; CHECK-NEXT: [[D:%.*]] = or <2 x i1> [[B]], [[C]]
+; CHECK-NEXT: ret <2 x i1> [[D]]
+;
+ %B = icmp sge <2 x i32> %A, <i32 100, i32 100>
+ %C = icmp slt <2 x i32> %A, <i32 50, i32 50>
+ %D = or <2 x i1> %B, %C
+ ret <2 x i1> %D
+}
+
+define i32 @test20(i32 %x) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT: ret i32 [[X:%.*]]
+;
+ %y = and i32 %x, 123
+ %z = or i32 %y, %x
+ ret i32 %z
+}
+
+define i32 @test21(i32 %tmp.1) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT: [[TMP_1_MASK1:%.*]] = add i32 [[TMP_1:%.*]], 2
+; CHECK-NEXT: ret i32 [[TMP_1_MASK1]]
+;
+ %tmp.1.mask1 = add i32 %tmp.1, 2
+ %tmp.3 = and i32 %tmp.1.mask1, -2
+ %tmp.5 = and i32 %tmp.1, 1
+ ;; add tmp.1, 2
+ %tmp.6 = or i32 %tmp.5, %tmp.3
+ ret i32 %tmp.6
+}
+
+define i32 @test22(i32 %B) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT: ret i32 [[B:%.*]]
+;
+ %ELIM41 = and i32 %B, 1
+ %ELIM7 = and i32 %B, -2
+ %ELIM5 = or i32 %ELIM41, %ELIM7
+ ret i32 %ELIM5
+}
+
+define i16 @test23(i16 %A) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT: [[B:%.*]] = lshr i16 [[A:%.*]], 1
+; CHECK-NEXT: [[D:%.*]] = xor i16 [[B]], -24575
+; CHECK-NEXT: ret i16 [[D]]
+;
+ %B = lshr i16 %A, 1
+ ;; fold or into xor
+ %C = or i16 %B, -32768
+ %D = xor i16 %C, 8193
+ ret i16 %D
+}
+
+define <2 x i16> @test23vec(<2 x i16> %A) {
+; CHECK-LABEL: @test23vec(
+; CHECK-NEXT: [[B:%.*]] = lshr <2 x i16> [[A:%.*]], <i16 1, i16 1>
+; CHECK-NEXT: [[D:%.*]] = xor <2 x i16> [[B]], <i16 -24575, i16 -24575>
+; CHECK-NEXT: ret <2 x i16> [[D]]
+;
+ %B = lshr <2 x i16> %A, <i16 1, i16 1>
+ ;; fold or into xor
+ %C = or <2 x i16> %B, <i16 -32768, i16 -32768>
+ %D = xor <2 x i16> %C, <i16 8193, i16 8193>
+ ret <2 x i16> %D
+}
+
+; PR3266 & PR5276
+define i1 @test25(i32 %A, i32 %B) {
+; CHECK-LABEL: @test25(
+; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A:%.*]], 0
+; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[B:%.*]], 57
+; CHECK-NEXT: [[F:%.*]] = and i1 [[D]], [[C]]
+; CHECK-NEXT: ret i1 [[F]]
+;
+ %C = icmp eq i32 %A, 0
+ %D = icmp eq i32 %B, 57
+ %E = or i1 %C, %D
+ %F = xor i1 %E, -1
+ ret i1 %F
+}
+
+; PR5634
+define i1 @test26(i32 %A, i32 %B) {
+; CHECK-LABEL: @test26(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %C1 = icmp eq i32 %A, 0
+ %C2 = icmp eq i32 %B, 0
+ ; (A == 0) & (A == 0) --> (A|B) == 0
+ %D = and i1 %C1, %C2
+ ret i1 %D
+}
+
+define i1 @test27(i32* %A, i32* %B) {
+; CHECK-LABEL: @test27(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32* [[A:%.*]], null
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32* [[B:%.*]], null
+; CHECK-NEXT: [[E:%.*]] = and i1 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[E]]
+;
+ %C1 = ptrtoint i32* %A to i32
+ %C2 = ptrtoint i32* %B to i32
+ %D = or i32 %C1, %C2
+ %E = icmp eq i32 %D, 0
+ ret i1 %E
+}
+
+define <2 x i1> @test27vec(<2 x i32*> %A, <2 x i32*> %B) {
+; CHECK-LABEL: @test27vec(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32*> [[A:%.*]], zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32*> [[B:%.*]], zeroinitializer
+; CHECK-NEXT: [[E:%.*]] = and <2 x i1> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret <2 x i1> [[E]]
+;
+ %C1 = ptrtoint <2 x i32*> %A to <2 x i32>
+ %C2 = ptrtoint <2 x i32*> %B to <2 x i32>
+ %D = or <2 x i32> %C1, %C2
+ %E = icmp eq <2 x i32> %D, zeroinitializer
+ ret <2 x i1> %E
+}
+
+; PR5634
+define i1 @test28(i32 %A, i32 %B) {
+; CHECK-LABEL: @test28(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %C1 = icmp ne i32 %A, 0
+ %C2 = icmp ne i32 %B, 0
+ ; (A != 0) | (A != 0) --> (A|B) != 0
+ %D = or i1 %C1, %C2
+ ret i1 %D
+}
+
+define i1 @test29(i32* %A, i32* %B) {
+; CHECK-LABEL: @test29(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32* [[A:%.*]], null
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32* [[B:%.*]], null
+; CHECK-NEXT: [[E:%.*]] = or i1 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[E]]
+;
+ %C1 = ptrtoint i32* %A to i32
+ %C2 = ptrtoint i32* %B to i32
+ %D = or i32 %C1, %C2
+ %E = icmp ne i32 %D, 0
+ ret i1 %E
+}
+
+define <2 x i1> @test29vec(<2 x i32*> %A, <2 x i32*> %B) {
+; CHECK-LABEL: @test29vec(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32*> [[A:%.*]], zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32*> [[B:%.*]], zeroinitializer
+; CHECK-NEXT: [[E:%.*]] = or <2 x i1> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret <2 x i1> [[E]]
+;
+ %C1 = ptrtoint <2 x i32*> %A to <2 x i32>
+ %C2 = ptrtoint <2 x i32*> %B to <2 x i32>
+ %D = or <2 x i32> %C1, %C2
+ %E = icmp ne <2 x i32> %D, zeroinitializer
+ ret <2 x i1> %E
+}
+
+; PR4216
+define i32 @test30(i32 %A) {
+; CHECK-LABEL: @test30(
+; CHECK-NEXT: [[D:%.*]] = and i32 [[A:%.*]], -58312
+; CHECK-NEXT: [[E:%.*]] = or i32 [[D]], 32962
+; CHECK-NEXT: ret i32 [[E]]
+;
+ %B = or i32 %A, 32962
+ %C = and i32 %A, -65536
+ %D = and i32 %B, 40186
+ %E = or i32 %D, %C
+ ret i32 %E
+}
+
+define <2 x i32> @test30vec(<2 x i32> %A) {
+; CHECK-LABEL: @test30vec(
+; CHECK-NEXT: [[C:%.*]] = and <2 x i32> [[A:%.*]], <i32 -65536, i32 -65536>
+; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[A]], <i32 7224, i32 7224>
+; CHECK-NEXT: [[D:%.*]] = or <2 x i32> [[B]], <i32 32962, i32 32962>
+; CHECK-NEXT: [[E:%.*]] = or <2 x i32> [[D]], [[C]]
+; CHECK-NEXT: ret <2 x i32> [[E]]
+;
+ %B = or <2 x i32> %A, <i32 32962, i32 32962>
+ %C = and <2 x i32> %A, <i32 -65536, i32 -65536>
+ %D = and <2 x i32> %B, <i32 40186, i32 40186>
+ %E = or <2 x i32> %D, %C
+ ret <2 x i32> %E
+}
+
+; PR4216
+define i64 @test31(i64 %A) {
+; CHECK-LABEL: @test31(
+; CHECK-NEXT: [[E:%.*]] = and i64 [[A:%.*]], 4294908984
+; CHECK-NEXT: [[F:%.*]] = or i64 [[E]], 32962
+; CHECK-NEXT: ret i64 [[F]]
+;
+ %B = or i64 %A, 194
+ %D = and i64 %B, 250
+
+ %C = or i64 %A, 32768
+ %E = and i64 %C, 4294941696
+
+ %F = or i64 %D, %E
+ ret i64 %F
+}
+
+define <2 x i64> @test31vec(<2 x i64> %A) {
+; CHECK-LABEL: @test31vec(
+; CHECK-NEXT: [[E:%.*]] = and <2 x i64> [[A:%.*]], <i64 4294908984, i64 4294908984>
+; CHECK-NEXT: [[F:%.*]] = or <2 x i64> [[E]], <i64 32962, i64 32962>
+; CHECK-NEXT: ret <2 x i64> [[F]]
+;
+ %B = or <2 x i64> %A, <i64 194, i64 194>
+ %D = and <2 x i64> %B, <i64 250, i64 250>
+
+ %C = or <2 x i64> %A, <i64 32768, i64 32768>
+ %E = and <2 x i64> %C, <i64 4294941696, i64 4294941696>
+
+ %F = or <2 x i64> %D, %E
+ ret <2 x i64> %F
+}
+
+; codegen is mature enough to handle vector selects.
+define <4 x i32> @test32(<4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191) {
+; CHECK-LABEL: @test32(
+; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[AND_I1352:%.*]], <4 x i32> [[VECINIT6_I176:%.*]], <4 x i32> [[VECINIT6_I191:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+;
+ %and.i135 = sext <4 x i1> %and.i1352 to <4 x i32>
+ %and.i129 = and <4 x i32> %vecinit6.i176, %and.i135
+ %neg.i = xor <4 x i32> %and.i135, <i32 -1, i32 -1, i32 -1, i32 -1>
+ %and.i = and <4 x i32> %vecinit6.i191, %neg.i
+ %or.i = or <4 x i32> %and.i, %and.i129
+ ret <4 x i32> %or.i
+}
+
+define i1 @test33(i1 %X, i1 %Y) {
+; CHECK-LABEL: @test33(
+; CHECK-NEXT: [[B:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[B]]
+;
+ %a = or i1 %X, %Y
+ %b = or i1 %a, %X
+ ret i1 %b
+}
+
+define i32 @test34(i32 %X, i32 %Y) {
+; CHECK-LABEL: @test34(
+; CHECK-NEXT: [[B:%.*]] = or i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %a = or i32 %X, %Y
+ %b = or i32 %Y, %a
+ ret i32 %b
+}
+
+define i32 @test35(i32 %a, i32 %b) {
+; CHECK-LABEL: @test35(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 1135
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %1 = or i32 %a, 1135
+ %2 = or i32 %1, %b
+ ret i32 %2
+}
+
+define i1 @test36(i32 %x) {
+; CHECK-LABEL: @test36(
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -23
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %cmp1 = icmp eq i32 %x, 23
+ %cmp2 = icmp eq i32 %x, 24
+ %ret1 = or i1 %cmp1, %cmp2
+ %cmp3 = icmp eq i32 %x, 25
+ %ret2 = or i1 %ret1, %cmp3
+ ret i1 %ret2
+}
+
+define i32 @orsext_to_sel(i32 %x, i1 %y) {
+; CHECK-LABEL: @orsext_to_sel(
+; CHECK-NEXT: [[OR:%.*]] = select i1 [[Y:%.*]], i32 -1, i32 [[X:%.*]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %sext = sext i1 %y to i32
+ %or = or i32 %sext, %x
+ ret i32 %or
+}
+
+define i32 @orsext_to_sel_swap(i32 %x, i1 %y) {
+; CHECK-LABEL: @orsext_to_sel_swap(
+; CHECK-NEXT: [[OR:%.*]] = select i1 [[Y:%.*]], i32 -1, i32 [[X:%.*]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %sext = sext i1 %y to i32
+ %or = or i32 %x, %sext
+ ret i32 %or
+}
+
+define i32 @orsext_to_sel_multi_use(i32 %x, i1 %y) {
+; CHECK-LABEL: @orsext_to_sel_multi_use(
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[Y:%.*]] to i32
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEXT]], [[X:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[OR]], [[SEXT]]
+; CHECK-NEXT: ret i32 [[ADD]]
+;
+ %sext = sext i1 %y to i32
+ %or = or i32 %sext, %x
+ %add = add i32 %sext, %or
+ ret i32 %add
+}
+
+define <2 x i32> @orsext_to_sel_vec(<2 x i32> %x, <2 x i1> %y) {
+; CHECK-LABEL: @orsext_to_sel_vec(
+; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> [[Y:%.*]], <2 x i32> <i32 -1, i32 -1>, <2 x i32> [[X:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[OR]]
+;
+ %sext = sext <2 x i1> %y to <2 x i32>
+ %or = or <2 x i32> %sext, %x
+ ret <2 x i32> %or
+}
+
+define <2 x i132> @orsext_to_sel_vec_swap(<2 x i132> %x, <2 x i1> %y) {
+; CHECK-LABEL: @orsext_to_sel_vec_swap(
+; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> [[Y:%.*]], <2 x i132> <i132 -1, i132 -1>, <2 x i132> [[X:%.*]]
+; CHECK-NEXT: ret <2 x i132> [[OR]]
+;
+ %sext = sext <2 x i1> %y to <2 x i132>
+ %or = or <2 x i132> %x, %sext
+ ret <2 x i132> %or
+}
+
+; (~A & B) | A --> A | B
+
+define i32 @test39a(i32 %a, float %b) {
+; CHECK-LABEL: @test39a(
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %a1 = mul i32 %a, 42 ; thwart complexity-based ordering
+ %b1 = bitcast float %b to i32 ; thwart complexity-based ordering
+ %nota = xor i32 %a1, -1
+ %and = and i32 %nota, %b1
+ %or = or i32 %and, %a1
+ ret i32 %or
+}
+
+; Commute 'and' operands:
+; (B & ~A) | A --> A | B
+
+define i32 @test39b(i32 %a, float %b) {
+; CHECK-LABEL: @test39b(
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %a1 = mul i32 %a, 42 ; thwart complexity-based ordering
+ %b1 = bitcast float %b to i32 ; thwart complexity-based ordering
+ %nota = xor i32 %a1, -1
+ %and = and i32 %b1, %nota
+ %or = or i32 %and, %a1
+ ret i32 %or
+}
+
+; Commute 'or' operands:
+; A | (~A & B) --> A | B
+
+define i32 @test39c(i32 %a, float %b) {
+; CHECK-LABEL: @test39c(
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %a1 = mul i32 %a, 42 ; thwart complexity-based ordering
+ %b1 = bitcast float %b to i32 ; thwart complexity-based ordering
+ %nota = xor i32 %a1, -1
+ %and = and i32 %nota, %b1
+ %or = or i32 %a1, %and
+ ret i32 %or
+}
+
+; Commute 'and' operands:
+; A | (B & ~A) --> A | B
+
+define i32 @test39d(i32 %a, float %b) {
+; CHECK-LABEL: @test39d(
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %a1 = mul i32 %a, 42 ; thwart complexity-based ordering
+ %b1 = bitcast float %b to i32 ; thwart complexity-based ordering
+ %nota = xor i32 %a1, -1
+ %and = and i32 %b1, %nota
+ %or = or i32 %a1, %and
+ ret i32 %or
+}
+
+define i32 @test40(i32 %a, i32 %b) {
+; CHECK-LABEL: @test40(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %and = and i32 %a, %b
+ %xor = xor i32 %a, -1
+ %or = or i32 %and, %xor
+ ret i32 %or
+}
+
+define i32 @test40b(i32 %a, i32 %b) {
+; CHECK-LABEL: @test40b(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %and = and i32 %b, %a
+ %xor = xor i32 %a, -1
+ %or = or i32 %and, %xor
+ ret i32 %or
+}
+
+define i32 @test40c(i32 %a, i32 %b) {
+; CHECK-LABEL: @test40c(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %and = and i32 %b, %a
+ %xor = xor i32 %a, -1
+ %or = or i32 %xor, %and
+ ret i32 %or
+}
+
+define i32 @test40d(i32 %a, i32 %b) {
+; CHECK-LABEL: @test40d(
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %and = and i32 %a, %b
+ %xor = xor i32 %a, -1
+ %or = or i32 %xor, %and
+ ret i32 %or
+}
+
+define i32 @test45(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @test45(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[OR1]]
+;
+ %or = or i32 %y, %z
+ %and = and i32 %x, %or
+ %or1 = or i32 %and, %y
+ ret i32 %or1
+}
+
+define i1 @test46(i8 signext %c) {
+; CHECK-LABEL: @test46(
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
+; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 26
+; CHECK-NEXT: ret i1 [[TMP3]]
+;
+ %c.off = add i8 %c, -97
+ %cmp1 = icmp ult i8 %c.off, 26
+ %c.off17 = add i8 %c, -65
+ %cmp2 = icmp ult i8 %c.off17, 26
+ %or = or i1 %cmp1, %cmp2
+ ret i1 %or
+}
+
+define i1 @test47(i8 signext %c) {
+; CHECK-LABEL: @test47(
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
+; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 27
+; CHECK-NEXT: ret i1 [[TMP3]]
+;
+ %c.off = add i8 %c, -65
+ %cmp1 = icmp ule i8 %c.off, 26
+ %c.off17 = add i8 %c, -97
+ %cmp2 = icmp ule i8 %c.off17, 26
+ %or = or i1 %cmp1, %cmp2
+ ret i1 %or
+}
+
+define i32 @test49(i1 %C) {
+; CHECK-LABEL: @test49(
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 1019, i32 123
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %A = select i1 %C, i32 1000, i32 10
+ %V = or i32 %A, 123
+ ret i32 %V
+}
+
+define <2 x i32> @test49vec(i1 %C) {
+; CHECK-LABEL: @test49vec(
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1019, i32 1019>, <2 x i32> <i32 123, i32 123>
+; CHECK-NEXT: ret <2 x i32> [[V]]
+;
+ %A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10>
+ %V = or <2 x i32> %A, <i32 123, i32 123>
+ ret <2 x i32> %V
+}
+
+define <2 x i32> @test49vec2(i1 %C) {
+; CHECK-LABEL: @test49vec2(
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1019, i32 2509>, <2 x i32> <i32 123, i32 351>
+; CHECK-NEXT: ret <2 x i32> [[V]]
+;
+ %A = select i1 %C, <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
+ %V = or <2 x i32> %A, <i32 123, i32 333>
+ ret <2 x i32> %V
+}
+
+define i32 @test50(i1 %which) {
+; CHECK-LABEL: @test50(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
+; CHECK: delay:
+; CHECK-NEXT: br label [[FINAL]]
+; CHECK: final:
+; CHECK-NEXT: [[A:%.*]] = phi i32 [ 1019, [[ENTRY:%.*]] ], [ 123, [[DELAY]] ]
+; CHECK-NEXT: ret i32 [[A]]
+;
+entry:
+ br i1 %which, label %final, label %delay
+
+delay:
+ br label %final
+
+final:
+ %A = phi i32 [ 1000, %entry ], [ 10, %delay ]
+ %value = or i32 %A, 123
+ ret i32 %value
+}
+
+define <2 x i32> @test50vec(i1 %which) {
+; CHECK-LABEL: @test50vec(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
+; CHECK: delay:
+; CHECK-NEXT: br label [[FINAL]]
+; CHECK: final:
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1019, i32 1019>, [[ENTRY:%.*]] ], [ <i32 123, i32 123>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
+;
+entry:
+ br i1 %which, label %final, label %delay
+
+delay:
+ br label %final
+
+final:
+ %A = phi <2 x i32> [ <i32 1000, i32 1000>, %entry ], [ <i32 10, i32 10>, %delay ]
+ %value = or <2 x i32> %A, <i32 123, i32 123>
+ ret <2 x i32> %value
+}
+
+define <2 x i32> @test50vec2(i1 %which) {
+; CHECK-LABEL: @test50vec2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
+; CHECK: delay:
+; CHECK-NEXT: br label [[FINAL]]
+; CHECK: final:
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1019, i32 2509>, [[ENTRY:%.*]] ], [ <i32 123, i32 351>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
+;
+entry:
+ br i1 %which, label %final, label %delay
+
+delay:
+ br label %final
+
+final:
+ %A = phi <2 x i32> [ <i32 1000, i32 2500>, %entry ], [ <i32 10, i32 30>, %delay ]
+ %value = or <2 x i32> %A, <i32 123, i32 333>
+ ret <2 x i32> %value
+}
+
+; In the next 4 tests, vary the types and predicates for extra coverage.
+; (X | (Y & ~X)) -> (X | Y), where 'not' is an inverted cmp
+
+define i1 @or_andn_cmp_1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @or_andn_cmp_1(
+; CHECK-NEXT: [[X:%.*]] = icmp sgt i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42
+; CHECK-NEXT: [[OR:%.*]] = or i1 [[X]], [[Y]]
+; CHECK-NEXT: ret i1 [[OR]]
+;
+ %x = icmp sgt i32 %a, %b
+ %x_inv = icmp sle i32 %a, %b
+ %y = icmp ugt i32 %c, 42 ; thwart complexity-based ordering
+ %and = and i1 %y, %x_inv
+ %or = or i1 %x, %and
+ ret i1 %or
+}
+
+; Commute the 'or':
+; ((Y & ~X) | X) -> (X | Y), where 'not' is an inverted cmp
+
+define <2 x i1> @or_andn_cmp_2(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; CHECK-LABEL: @or_andn_cmp_2(
+; CHECK-NEXT: [[X:%.*]] = icmp sge <2 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt <2 x i32> [[C:%.*]], <i32 42, i32 47>
+; CHECK-NEXT: [[OR:%.*]] = or <2 x i1> [[Y]], [[X]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
+;
+ %x = icmp sge <2 x i32> %a, %b
+ %x_inv = icmp slt <2 x i32> %a, %b
+ %y = icmp ugt <2 x i32> %c, <i32 42, i32 47> ; thwart complexity-based ordering
+ %and = and <2 x i1> %y, %x_inv
+ %or = or <2 x i1> %and, %x
+ ret <2 x i1> %or
+}
+
+; Commute the 'and':
+; (X | (~X & Y)) -> (X | Y), where 'not' is an inverted cmp
+
+define i1 @or_andn_cmp_3(i72 %a, i72 %b, i72 %c) {
+; CHECK-LABEL: @or_andn_cmp_3(
+; CHECK-NEXT: [[X:%.*]] = icmp ugt i72 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt i72 [[C:%.*]], 42
+; CHECK-NEXT: [[OR:%.*]] = or i1 [[X]], [[Y]]
+; CHECK-NEXT: ret i1 [[OR]]
+;
+ %x = icmp ugt i72 %a, %b
+ %x_inv = icmp ule i72 %a, %b
+ %y = icmp ugt i72 %c, 42 ; thwart complexity-based ordering
+ %and = and i1 %x_inv, %y
+ %or = or i1 %x, %and
+ ret i1 %or
+}
+
+; Commute the 'or':
+; ((~X & Y) | X) -> (X | Y), where 'not' is an inverted cmp
+
+define <3 x i1> @or_andn_cmp_4(<3 x i32> %a, <3 x i32> %b, <3 x i32> %c) {
+; CHECK-LABEL: @or_andn_cmp_4(
+; CHECK-NEXT: [[X:%.*]] = icmp eq <3 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt <3 x i32> [[C:%.*]], <i32 42, i32 43, i32 -1>
+; CHECK-NEXT: [[OR:%.*]] = or <3 x i1> [[Y]], [[X]]
+; CHECK-NEXT: ret <3 x i1> [[OR]]
+;
+ %x = icmp eq <3 x i32> %a, %b
+ %x_inv = icmp ne <3 x i32> %a, %b
+ %y = icmp ugt <3 x i32> %c, <i32 42, i32 43, i32 -1> ; thwart complexity-based ordering
+ %and = and <3 x i1> %x_inv, %y
+ %or = or <3 x i1> %and, %x
+ ret <3 x i1> %or
+}
+
+; In the next 4 tests, vary the types and predicates for extra coverage.
+; (~X | (Y & X)) -> (~X | Y), where 'not' is an inverted cmp
+
+define i1 @orn_and_cmp_1(i37 %a, i37 %b, i37 %c) {
+; CHECK-LABEL: @orn_and_cmp_1(
+; CHECK-NEXT: [[X_INV:%.*]] = icmp sle i37 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt i37 [[C:%.*]], 42
+; CHECK-NEXT: [[OR:%.*]] = or i1 [[X_INV]], [[Y]]
+; CHECK-NEXT: ret i1 [[OR]]
+;
+ %x = icmp sgt i37 %a, %b
+ %x_inv = icmp sle i37 %a, %b
+ %y = icmp ugt i37 %c, 42 ; thwart complexity-based ordering
+ %and = and i1 %y, %x
+ %or = or i1 %x_inv, %and
+ ret i1 %or
+}
+
+; Commute the 'or':
+; ((Y & X) | ~X) -> (~X | Y), where 'not' is an inverted cmp
+
+define i1 @orn_and_cmp_2(i16 %a, i16 %b, i16 %c) {
+; CHECK-LABEL: @orn_and_cmp_2(
+; CHECK-NEXT: [[X_INV:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt i16 [[C:%.*]], 42
+; CHECK-NEXT: [[OR:%.*]] = or i1 [[Y]], [[X_INV]]
+; CHECK-NEXT: ret i1 [[OR]]
+;
+ %x = icmp sge i16 %a, %b
+ %x_inv = icmp slt i16 %a, %b
+ %y = icmp ugt i16 %c, 42 ; thwart complexity-based ordering
+ %and = and i1 %y, %x
+ %or = or i1 %and, %x_inv
+ ret i1 %or
+}
+
+; Commute the 'and':
+; (~X | (X & Y)) -> (~X | Y), where 'not' is an inverted cmp
+
+define <4 x i1> @orn_and_cmp_3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: @orn_and_cmp_3(
+; CHECK-NEXT: [[X_INV:%.*]] = icmp ule <4 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt <4 x i32> [[C:%.*]], <i32 42, i32 0, i32 1, i32 -1>
+; CHECK-NEXT: [[OR:%.*]] = or <4 x i1> [[X_INV]], [[Y]]
+; CHECK-NEXT: ret <4 x i1> [[OR]]
+;
+ %x = icmp ugt <4 x i32> %a, %b
+ %x_inv = icmp ule <4 x i32> %a, %b
+ %y = icmp ugt <4 x i32> %c, <i32 42, i32 0, i32 1, i32 -1> ; thwart complexity-based ordering
+ %and = and <4 x i1> %x, %y
+ %or = or <4 x i1> %x_inv, %and
+ ret <4 x i1> %or
+}
+
+; Commute the 'or':
+; ((X & Y) | ~X) -> (~X | Y), where 'not' is an inverted cmp
+
+define i1 @orn_and_cmp_4(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @orn_and_cmp_4(
+; CHECK-NEXT: [[X_INV:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = icmp ugt i32 [[C:%.*]], 42
+; CHECK-NEXT: [[OR:%.*]] = or i1 [[Y]], [[X_INV]]
+; CHECK-NEXT: ret i1 [[OR]]
+;
+ %x = icmp eq i32 %a, %b
+ %x_inv = icmp ne i32 %a, %b
+ %y = icmp ugt i32 %c, 42 ; thwart complexity-based ordering
+ %and = and i1 %x, %y
+ %or = or i1 %and, %x_inv
+ ret i1 %or
+}
+
+; The constant vectors are inverses. Make sure we can turn this into a select without crashing trying to truncate the constant to 16xi1.
+define <16 x i1> @test51(<16 x i1> %arg, <16 x i1> %arg1) {
+; CHECK-LABEL: @test51(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i1> [[ARG:%.*]], <16 x i1> [[ARG1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 23, i32 24, i32 9, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT: ret <16 x i1> [[TMP1]]
+;
+ %tmp = and <16 x i1> %arg, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
+ %tmp2 = and <16 x i1> %arg1, <i1 false, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true>
+ %tmp3 = or <16 x i1> %tmp, %tmp2
+ ret <16 x i1> %tmp3
+}
Added: llvm/trunk/test/Transforms/InstCombine/osx-names.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/osx-names.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/osx-names.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/osx-names.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,30 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+; <rdar://problem/9815881>
+; On OSX x86-32, fwrite and fputs aren't called fwrite and fputs.
+; Make sure we use the correct names.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.7.2"
+
+%struct.__sFILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__sbuf = type { i8*, i32 }
+%struct.__sFILEX = type opaque
+
+ at .str = private unnamed_addr constant [13 x i8] c"Hello world\0A\00", align 1
+ at .str2 = private unnamed_addr constant [3 x i8] c"%s\00", align 1
+
+define void @test1(%struct.__sFILE* %stream) nounwind {
+; CHECK-LABEL: define void @test1(
+; CHECK: call i32 @"fwrite$UNIX2003"
+ %call = tail call i32 (%struct.__sFILE*, i8*, ...) @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0)) nounwind
+ ret void
+}
+
+define void @test2(%struct.__sFILE* %stream, i8* %str) nounwind ssp {
+; CHECK-LABEL: define void @test2(
+; CHECK: call i32 @"fputs$UNIX2003"
+ %call = tail call i32 (%struct.__sFILE*, i8*, ...) @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str2, i32 0, i32 0), i8* %str) nounwind
+ ret void
+}
+
+declare i32 @fprintf(%struct.__sFILE*, i8*, ...) nounwind
Added: llvm/trunk/test/Transforms/InstCombine/out-of-bounds-indexes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/out-of-bounds-indexes.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/out-of-bounds-indexes.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/out-of-bounds-indexes.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+; Check that we don't crash on unreasonable constant indexes
+
+define i32 @test_out_of_bounds(i32 %a, i1 %x, i1 %y) {
+; CHECK-LABEL: @test_out_of_bounds(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
+; CHECK-NEXT: tail call void @llvm.assume(i1 false)
+; CHECK-NEXT: ret i32 [[AND1]]
+;
+entry:
+ %and1 = and i32 %a, 3
+ %B = lshr i32 %and1, -2147483648
+ %cmp = icmp eq i32 %B, 1
+ tail call void @llvm.assume(i1 %cmp)
+ ret i32 %and1
+}
+
+define i128 @test_non64bit(i128 %a) {
+; CHECK-LABEL: @test_non64bit(
+; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
+; CHECK-NEXT: tail call void @llvm.assume(i1 false)
+; CHECK-NEXT: ret i128 [[AND1]]
+;
+ %and1 = and i128 %a, 3
+ %B = lshr i128 %and1, -1
+ %cmp = icmp eq i128 %B, 1
+ tail call void @llvm.assume(i1 %cmp)
+ ret i128 %and1
+}
+
+declare void @llvm.assume(i1)
+
+define <4 x double> @inselt_bad_index(<4 x double> %a) {
+; CHECK-LABEL: @inselt_bad_index(
+; CHECK-NEXT: ret <4 x double> undef
+;
+ %I = insertelement <4 x double> %a, double 0.0, i64 4294967296
+ ret <4 x double> %I
+}
Added: llvm/trunk/test/Transforms/InstCombine/overflow-mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/overflow-mul.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/overflow-mul.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/overflow-mul.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,199 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+; return mul(zext x, zext y) > MAX
+define i32 @pr4917_1(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4917_1(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+; CHECK-NOT: zext i32
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %overflow = icmp ugt i64 %mul64, 4294967295
+; CHECK: extractvalue { i32, i1 } [[MUL]], 1
+ %retval = zext i1 %overflow to i32
+ ret i32 %retval
+}
+
+; return mul(zext x, zext y) >= MAX+1
+define i32 @pr4917_1a(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4917_1a(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+; CHECK-NOT: zext i32
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %overflow = icmp uge i64 %mul64, 4294967296
+; CHECK: extractvalue { i32, i1 } [[MUL]], 1
+ %retval = zext i1 %overflow to i32
+ ret i32 %retval
+}
+
+; mul(zext x, zext y) > MAX
+; mul(x, y) is used
+define i32 @pr4917_2(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4917_2(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+; CHECK-NOT: zext i32
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %overflow = icmp ugt i64 %mul64, 4294967295
+; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
+ %mul32 = trunc i64 %mul64 to i32
+; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
+ %retval = select i1 %overflow, i32 %mul32, i32 111
+; CHECK: select i1 [[OVFL]], i32 [[VAL]]
+ ret i32 %retval
+}
+
+; return mul(zext x, zext y) > MAX
+; mul is used in non-truncate
+define i64 @pr4917_3(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4917_3(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+ %mul64 = mul i64 %l, %r
+; CHECK-NOT: umul.with.overflow.i32
+ %overflow = icmp ugt i64 %mul64, 4294967295
+ %retval = select i1 %overflow, i64 %mul64, i64 111
+ ret i64 %retval
+}
+
+; return mul(zext x, zext y) <= MAX
+define i32 @pr4917_4(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4917_4(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+; CHECK-NOT: zext i32
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %overflow = icmp ule i64 %mul64, 4294967295
+; CHECK: extractvalue { i32, i1 } [[MUL]], 1
+; CHECK: xor
+ %retval = zext i1 %overflow to i32
+ ret i32 %retval
+}
+
+; return mul(zext x, zext y) < MAX+1
+define i32 @pr4917_4a(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4917_4a(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+; CHECK-NOT: zext i32
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %overflow = icmp ult i64 %mul64, 4294967296
+; CHECK: extractvalue { i32, i1 } [[MUL]], 1
+; CHECK: xor
+ %retval = zext i1 %overflow to i32
+ ret i32 %retval
+}
+
+; operands of mul are of different size
+define i32 @pr4917_5(i32 %x, i8 %y) nounwind {
+; CHECK-LABEL: @pr4917_5(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i8 %y to i64
+; CHECK: [[Y:%.*]] = zext i8 %y to i32
+ %mul64 = mul i64 %l, %r
+ %overflow = icmp ugt i64 %mul64, 4294967295
+ %mul32 = trunc i64 %mul64 to i32
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 [[Y]])
+; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
+; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
+ %retval = select i1 %overflow, i32 %mul32, i32 111
+; CHECK: select i1 [[OVFL]], i32 [[VAL]]
+ ret i32 %retval
+}
+
+; mul(zext x, zext y) != zext trunc mul
+define i32 @pr4918_1(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4918_1(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %part32 = trunc i64 %mul64 to i32
+ %part64 = zext i32 %part32 to i64
+ %overflow = icmp ne i64 %mul64, %part64
+; CHECK: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL:%.*]], 1
+ %retval = zext i1 %overflow to i32
+ ret i32 %retval
+}
+
+; mul(zext x, zext y) == zext trunc mul
+define i32 @pr4918_2(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4918_2(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %part32 = trunc i64 %mul64 to i32
+ %part64 = zext i32 %part32 to i64
+ %overflow = icmp eq i64 %mul64, %part64
+; CHECK: extractvalue { i32, i1 } [[MUL]]
+ %retval = zext i1 %overflow to i32
+; CHECK: xor
+ ret i32 %retval
+}
+
+; zext trunc mul != mul(zext x, zext y)
+define i32 @pr4918_3(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: @pr4918_3(
+entry:
+ %l = zext i32 %x to i64
+ %r = zext i32 %y to i64
+ %mul64 = mul i64 %l, %r
+; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
+ %part32 = trunc i64 %mul64 to i32
+ %part64 = zext i32 %part32 to i64
+ %overflow = icmp ne i64 %part64, %mul64
+; CHECK: extractvalue { i32, i1 } [[MUL]], 1
+ %retval = zext i1 %overflow to i32
+ ret i32 %retval
+}
+
+define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-LABEL: @pr20113
+; CHECK-NOT: mul.with.overflow
+; CHECK: ret
+ %vmovl.i.i726 = zext <4 x i16> %a to <4 x i32>
+ %vmovl.i.i712 = zext <4 x i16> %b to <4 x i32>
+ %mul.i703 = mul <4 x i32> %vmovl.i.i712, %vmovl.i.i726
+ %tmp = icmp sge <4 x i32> %mul.i703, zeroinitializer
+ %vcgez.i = sext <4 x i1> %tmp to <4 x i32>
+ ret <4 x i32> %vcgez.i
+}
+
+
+; The last test needs this weird datalayout.
+target datalayout = "i32:8:8"
+; Without it, InstCombine will align the pointed on 4 Bytes
+; The KnownBitsZero that result from the alignment allows to
+; turn:
+; and i32 %mul, 255
+; to:
+; and i32 %mul, 252
+; The mask is no longer in the form 2^n-1 and this prevents the transformation.
+
+ at pr21445_data = external global i32
+define i1 @pr21445(i8 %a) {
+; CHECK-LABEL: @pr21445(
+; CHECK-NEXT: %[[umul:.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 ptrtoint (i32* @pr21445_data to i8))
+; CHECK-NEXT: %[[cmp:.*]] = extractvalue { i8, i1 } %[[umul]], 1
+; CHECK-NEXT: ret i1 %[[cmp]]
+ %ext = zext i8 %a to i32
+ %mul = mul i32 %ext, zext (i8 ptrtoint (i32* @pr21445_data to i8) to i32)
+ %and = and i32 %mul, 255
+ %cmp = icmp ne i32 %mul, %and
+ ret i1 %cmp
+}
Added: llvm/trunk/test/Transforms/InstCombine/overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/overflow.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/overflow.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/overflow.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+; <rdar://problem/8558713>
+
+declare void @throwAnExceptionOrWhatever()
+
+define i32 @test1(i32 %a, i32 %b) nounwind ssp {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SADD:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[B:%.*]], i32 [[A:%.*]])
+; CHECK-NEXT: [[SADD_RESULT:%.*]] = extractvalue { i32, i1 } [[SADD]], 0
+; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { i32, i1 } [[SADD]], 1
+; CHECK-NEXT: br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: ret i32 [[SADD_RESULT]]
+;
+entry:
+ %conv = sext i32 %a to i64
+ %conv2 = sext i32 %b to i64
+ %add = add nsw i64 %conv2, %conv
+ %add.off = add i64 %add, 2147483648
+ %0 = icmp ugt i64 %add.off, 4294967295
+ br i1 %0, label %if.then, label %if.end
+
+if.then:
+ tail call void @throwAnExceptionOrWhatever() nounwind
+ br label %if.end
+
+if.end:
+ %conv9 = trunc i64 %add to i32
+ ret i32 %conv9
+}
+
+; This form should not be promoted for two reasons: 1) it is unprofitable to
+; promote it since the add.off instruction has another use, and 2) it is unsafe
+; because the add-with-off makes the high bits of the original add live.
+
+define i32 @test2(i32 %a, i32 %b, i64* %P) nounwind ssp {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[B:%.*]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV2]], [[CONV]]
+; CHECK-NEXT: [[ADD_OFF:%.*]] = add nsw i64 [[ADD]], 2147483648
+; CHECK-NEXT: store i64 [[ADD_OFF]], i64* [[P:%.*]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[ADD_OFF]], 4294967295
+; CHECK-NEXT: br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
+; CHECK-NEXT: ret i32 [[CONV9]]
+;
+entry:
+ %conv = sext i32 %a to i64
+ %conv2 = sext i32 %b to i64
+ %add = add nsw i64 %conv2, %conv
+ %add.off = add i64 %add, 2147483648
+ store i64 %add.off, i64* %P
+ %0 = icmp ugt i64 %add.off, 4294967295
+ br i1 %0, label %if.then, label %if.end
+
+if.then:
+ tail call void @throwAnExceptionOrWhatever() nounwind
+ br label %if.end
+
+if.end:
+ %conv9 = trunc i64 %add to i32
+ ret i32 %conv9
+}
+
+; PR8816
+; This is illegal to transform because the high bits of the original add are
+; live out.
+define i64 @test3(i32 %a, i32 %b) nounwind ssp {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[B:%.*]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV2]], [[CONV]]
+; CHECK-NEXT: [[ADD_OFF:%.*]] = add nsw i64 [[ADD]], 2147483648
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[ADD_OFF]], 4294967295
+; CHECK-NEXT: br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: ret i64 [[ADD]]
+;
+entry:
+ %conv = sext i32 %a to i64
+ %conv2 = sext i32 %b to i64
+ %add = add nsw i64 %conv2, %conv
+ %add.off = add i64 %add, 2147483648
+ %0 = icmp ugt i64 %add.off, 4294967295
+ br i1 %0, label %if.then, label %if.end
+
+if.then:
+ tail call void @throwAnExceptionOrWhatever() nounwind
+ br label %if.end
+
+if.end:
+ ret i64 %add
+}
+
+; Should be able to form an i8 sadd computed in an i32.
+
+define zeroext i8 @test4(i8 signext %a, i8 signext %b) nounwind ssp {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SADD:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[B:%.*]], i8 [[A:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = extractvalue { i8, i1 } [[SADD]], 1
+; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT: unreachable
+; CHECK: if.end:
+; CHECK-NEXT: [[SADD_RESULT:%.*]] = extractvalue { i8, i1 } [[SADD]], 0
+; CHECK-NEXT: ret i8 [[SADD_RESULT]]
+;
+entry:
+ %conv = sext i8 %a to i32
+ %conv2 = sext i8 %b to i32
+ %add = add nsw i32 %conv2, %conv
+ %add4 = add nsw i32 %add, 128
+ %cmp = icmp ugt i32 %add4, 255
+ br i1 %cmp, label %if.then, label %if.end
+if.then:
+ tail call void @throwAnExceptionOrWhatever() nounwind
+ unreachable
+
+if.end:
+ %conv7 = trunc i32 %add to i8
+ ret i8 %conv7
+}
+
+; PR11438
+; This is @test1, but the operands are not sign-extended. Make sure
+; we don't transform this case.
+
+define i32 @test8(i64 %a, i64 %b) nounwind ssp {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADD:%.*]] = add i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[ADD_OFF:%.*]] = add i64 [[ADD]], 2147483648
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[ADD_OFF]], 4294967295
+; CHECK-NEXT: br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
+; CHECK-NEXT: ret i32 [[CONV9]]
+;
+entry:
+ %add = add i64 %a, %b
+ %add.off = add i64 %add, 2147483648
+ %0 = icmp ugt i64 %add.off, 4294967295
+ br i1 %0, label %if.then, label %if.end
+
+if.then:
+ tail call void @throwAnExceptionOrWhatever() nounwind
+ br label %if.end
+
+if.end:
+ %conv9 = trunc i64 %add to i32
+ ret i32 %conv9
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-2.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-2.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-2.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,30 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+declare void @bar()
+declare void @baz()
+
+; Check that dereferenceable metadata is combined
+; CHECK-LABEL: cont:
+; CHECK: load i32*, i32**
+; CHECK-SAME: !dereferenceable ![[DEREF:[0-9]+]]
+define i32* @test_phi_combine_load_metadata(i1 %c, i32** dereferenceable(8) %p1, i32** dereferenceable(8) %p2) {
+ br i1 %c, label %t, label %f
+t:
+ call void @bar()
+ %v1 = load i32*, i32** %p1, align 8, !dereferenceable !0
+ br label %cont
+
+f:
+ call void @baz()
+ %v2 = load i32*, i32** %p2, align 8, !dereferenceable !1
+ br label %cont
+
+cont:
+ %res = phi i32* [ %v1, %t ], [ %v2, %f ]
+ ret i32* %res
+}
+
+; CHECK: ![[DEREF]] = !{i64 8}
+
+!0 = !{i64 8}
+!1 = !{i64 16}
Added: llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-3.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-3.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-3.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,30 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+declare void @bar()
+declare void @baz()
+
+; Check that dereferenceable_or_null metadata is combined
+; CHECK-LABEL: cont:
+; CHECK: load i32*, i32**
+; CHECK-SAME: !dereferenceable_or_null ![[DEREF:[0-9]+]]
+define i32* @test_phi_combine_load_metadata(i1 %c, i32** dereferenceable(8) %p1, i32** dereferenceable(8) %p2) {
+ br i1 %c, label %t, label %f
+t:
+ call void @bar()
+ %v1 = load i32*, i32** %p1, align 8, !dereferenceable_or_null !0
+ br label %cont
+
+f:
+ call void @baz()
+ %v2 = load i32*, i32** %p2, align 8, !dereferenceable_or_null !1
+ br label %cont
+
+cont:
+ %res = phi i32* [ %v1, %t ], [ %v2, %f ]
+ ret i32* %res
+}
+
+; CHECK: ![[DEREF]] = !{i64 8}
+
+!0 = !{i64 8}
+!1 = !{i64 16}
Added: llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-dominance.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-dominance.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-dominance.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-load-metadata-dominance.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,26 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+declare void @bar()
+declare void @baz()
+
+; Check that nonnull metadata is from non-dominating loads is not propagated.
+; CHECK-LABEL: cont:
+; CHECK-NOT: !nonnull
+define i32* @test_combine_metadata_dominance(i1 %c, i32** dereferenceable(8) %p1, i32** dereferenceable(8) %p2) {
+ br i1 %c, label %t, label %f
+t:
+ call void @bar()
+ %v1 = load i32*, i32** %p1, align 8, !nonnull !0
+ br label %cont
+
+f:
+ call void @baz()
+ %v2 = load i32*, i32** %p2, align 8
+ br label %cont
+
+cont:
+ %res = phi i32* [ %v1, %t ], [ %v2, %f ]
+ ret i32* %res
+}
+
+!0 = !{}
Added: llvm/trunk/test/Transforms/InstCombine/phi-load-metadata.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-load-metadata.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-load-metadata.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-load-metadata.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,30 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+declare void @bar()
+declare void @baz()
+
+; Check that align metadata is combined
+; CHECK-LABEL: cont:
+; CHECK: load i32*, i32**
+; CHECK-SAME: !align ![[ALIGN:[0-9]+]]
+define i32* @test_phi_combine_load_metadata(i1 %c, i32** dereferenceable(8) %p1, i32** dereferenceable(8) %p2) {
+ br i1 %c, label %t, label %f
+t:
+ call void @bar()
+ %v1 = load i32*, i32** %p1, align 8, !align !0
+ br label %cont
+
+f:
+ call void @baz()
+ %v2 = load i32*, i32** %p2, align 8, !align !1
+ br label %cont
+
+cont:
+ %res = phi i32* [ %v1, %t ], [ %v2, %f ]
+ ret i32* %res
+}
+
+; CHECK: ![[ALIGN]] = !{i64 8}
+
+!0 = !{i64 8}
+!1 = !{i64 16}
Added: llvm/trunk/test/Transforms/InstCombine/phi-merge-gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-merge-gep.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-merge-gep.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-merge-gep.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,102 @@
+; RUN: opt < %s -S -instcombine > %t
+; RUN: grep "= getelementptr" %t | count 20
+; RUN: grep "= phi" %t | count 13
+
+; Don't push the geps through these phis, because they would require
+; two phis each, which burdens the loop with high register pressure.
+
+define void @foo(float* %Ar, float* %Ai, i64 %As, float* %Cr, float* %Ci, i64 %Cs, i64 %n) nounwind {
+entry:
+ %0 = getelementptr inbounds float, float* %Ar, i64 0 ; <float*> [#uses=1]
+ %1 = getelementptr inbounds float, float* %Ai, i64 0 ; <float*> [#uses=1]
+ %2 = mul i64 %n, %As ; <i64> [#uses=1]
+ %3 = getelementptr inbounds float, float* %Ar, i64 %2 ; <float*> [#uses=1]
+ %4 = mul i64 %n, %As ; <i64> [#uses=1]
+ %5 = getelementptr inbounds float, float* %Ai, i64 %4 ; <float*> [#uses=1]
+ %6 = mul i64 %n, 2 ; <i64> [#uses=1]
+ %7 = mul i64 %6, %As ; <i64> [#uses=1]
+ %8 = getelementptr inbounds float, float* %Ar, i64 %7 ; <float*> [#uses=1]
+ %9 = mul i64 %n, 2 ; <i64> [#uses=1]
+ %10 = mul i64 %9, %As ; <i64> [#uses=1]
+ %11 = getelementptr inbounds float, float* %Ai, i64 %10 ; <float*> [#uses=1]
+ %12 = getelementptr inbounds float, float* %Cr, i64 0 ; <float*> [#uses=1]
+ %13 = getelementptr inbounds float, float* %Ci, i64 0 ; <float*> [#uses=1]
+ %14 = mul i64 %n, %Cs ; <i64> [#uses=1]
+ %15 = getelementptr inbounds float, float* %Cr, i64 %14 ; <float*> [#uses=1]
+ %16 = mul i64 %n, %Cs ; <i64> [#uses=1]
+ %17 = getelementptr inbounds float, float* %Ci, i64 %16 ; <float*> [#uses=1]
+ %18 = mul i64 %n, 2 ; <i64> [#uses=1]
+ %19 = mul i64 %18, %Cs ; <i64> [#uses=1]
+ %20 = getelementptr inbounds float, float* %Cr, i64 %19 ; <float*> [#uses=1]
+ %21 = mul i64 %n, 2 ; <i64> [#uses=1]
+ %22 = mul i64 %21, %Cs ; <i64> [#uses=1]
+ %23 = getelementptr inbounds float, float* %Ci, i64 %22 ; <float*> [#uses=1]
+ br label %bb13
+
+bb: ; preds = %bb13
+ %24 = load float, float* %A0r.0, align 4 ; <float> [#uses=1]
+ %25 = load float, float* %A0i.0, align 4 ; <float> [#uses=1]
+ %26 = load float, float* %A1r.0, align 4 ; <float> [#uses=2]
+ %27 = load float, float* %A1i.0, align 4 ; <float> [#uses=2]
+ %28 = load float, float* %A2r.0, align 4 ; <float> [#uses=2]
+ %29 = load float, float* %A2i.0, align 4 ; <float> [#uses=2]
+ %30 = fadd float %26, %28 ; <float> [#uses=2]
+ %31 = fadd float %27, %29 ; <float> [#uses=2]
+ %32 = fsub float %26, %28 ; <float> [#uses=1]
+ %33 = fsub float %27, %29 ; <float> [#uses=1]
+ %34 = fadd float %24, %30 ; <float> [#uses=2]
+ %35 = fadd float %25, %31 ; <float> [#uses=2]
+ %36 = fmul float %30, -1.500000e+00 ; <float> [#uses=1]
+ %37 = fmul float %31, -1.500000e+00 ; <float> [#uses=1]
+ %38 = fadd float %34, %36 ; <float> [#uses=2]
+ %39 = fadd float %35, %37 ; <float> [#uses=2]
+ %40 = fmul float %32, 0x3FEBB67AE0000000 ; <float> [#uses=2]
+ %41 = fmul float %33, 0x3FEBB67AE0000000 ; <float> [#uses=2]
+ %42 = fadd float %38, %41 ; <float> [#uses=1]
+ %43 = fsub float %39, %40 ; <float> [#uses=1]
+ %44 = fsub float %38, %41 ; <float> [#uses=1]
+ %45 = fadd float %39, %40 ; <float> [#uses=1]
+ store float %34, float* %C0r.0, align 4
+ store float %35, float* %C0i.0, align 4
+ store float %42, float* %C1r.0, align 4
+ store float %43, float* %C1i.0, align 4
+ store float %44, float* %C2r.0, align 4
+ store float %45, float* %C2i.0, align 4
+ %46 = getelementptr inbounds float, float* %A0r.0, i64 %As ; <float*> [#uses=1]
+ %47 = getelementptr inbounds float, float* %A0i.0, i64 %As ; <float*> [#uses=1]
+ %48 = getelementptr inbounds float, float* %A1r.0, i64 %As ; <float*> [#uses=1]
+ %49 = getelementptr inbounds float, float* %A1i.0, i64 %As ; <float*> [#uses=1]
+ %50 = getelementptr inbounds float, float* %A2r.0, i64 %As ; <float*> [#uses=1]
+ %51 = getelementptr inbounds float, float* %A2i.0, i64 %As ; <float*> [#uses=1]
+ %52 = getelementptr inbounds float, float* %C0r.0, i64 %Cs ; <float*> [#uses=1]
+ %53 = getelementptr inbounds float, float* %C0i.0, i64 %Cs ; <float*> [#uses=1]
+ %54 = getelementptr inbounds float, float* %C1r.0, i64 %Cs ; <float*> [#uses=1]
+ %55 = getelementptr inbounds float, float* %C1i.0, i64 %Cs ; <float*> [#uses=1]
+ %56 = getelementptr inbounds float, float* %C2r.0, i64 %Cs ; <float*> [#uses=1]
+ %57 = getelementptr inbounds float, float* %C2i.0, i64 %Cs ; <float*> [#uses=1]
+ %58 = add nsw i64 %i.0, 1 ; <i64> [#uses=1]
+ br label %bb13
+
+bb13: ; preds = %bb, %entry
+ %i.0 = phi i64 [ 0, %entry ], [ %58, %bb ] ; <i64> [#uses=2]
+ %C2i.0 = phi float* [ %23, %entry ], [ %57, %bb ] ; <float*> [#uses=2]
+ %C2r.0 = phi float* [ %20, %entry ], [ %56, %bb ] ; <float*> [#uses=2]
+ %C1i.0 = phi float* [ %17, %entry ], [ %55, %bb ] ; <float*> [#uses=2]
+ %C1r.0 = phi float* [ %15, %entry ], [ %54, %bb ] ; <float*> [#uses=2]
+ %C0i.0 = phi float* [ %13, %entry ], [ %53, %bb ] ; <float*> [#uses=2]
+ %C0r.0 = phi float* [ %12, %entry ], [ %52, %bb ] ; <float*> [#uses=2]
+ %A2i.0 = phi float* [ %11, %entry ], [ %51, %bb ] ; <float*> [#uses=2]
+ %A2r.0 = phi float* [ %8, %entry ], [ %50, %bb ] ; <float*> [#uses=2]
+ %A1i.0 = phi float* [ %5, %entry ], [ %49, %bb ] ; <float*> [#uses=2]
+ %A1r.0 = phi float* [ %3, %entry ], [ %48, %bb ] ; <float*> [#uses=2]
+ %A0i.0 = phi float* [ %1, %entry ], [ %47, %bb ] ; <float*> [#uses=2]
+ %A0r.0 = phi float* [ %0, %entry ], [ %46, %bb ] ; <float*> [#uses=2]
+ %59 = icmp slt i64 %i.0, %n ; <i1> [#uses=1]
+ br i1 %59, label %bb, label %bb14
+
+bb14: ; preds = %bb13
+ br label %return
+
+return: ; preds = %bb14
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/phi-preserve-ir-flags.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-preserve-ir-flags.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-preserve-ir-flags.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-preserve-ir-flags.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,89 @@
+; RUN: opt < %s -instcombine -S -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+
+; CHECK-LABEL: define float @func1(
+define float @func1(float %a, float %b, float %c, i1 %cond) {
+entry:
+ br i1 %cond, label %cond.true, label %cond.false
+
+cond.true:
+ %sub0 = fsub fast float %a, %b
+ br label %cond.end
+
+cond.false:
+ %sub1 = fsub fast float %a, %c
+ br label %cond.end
+
+; The fast-math flags should always be transfered if possible.
+; CHECK-LABEL: cond.end
+; CHECK [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ]
+; CHECK fsub fast float %a, [[PHI]]
+cond.end:
+ %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
+ ret float %e
+}
+
+; CHECK-LABEL: define float @func2(
+define float @func2(float %a, float %b, float %c, i1 %cond) {
+entry:
+ br i1 %cond, label %cond.true, label %cond.false
+
+cond.true:
+ %sub0 = fsub fast float %a, %b
+ br label %cond.end
+
+cond.false:
+ %sub1 = fsub float %a, %c
+ br label %cond.end
+
+; The fast-math flags should always be transfered if possible.
+; CHECK-LABEL: cond.end
+; CHECK [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ]
+; CHECK fsub float %a, [[PHI]]
+cond.end:
+ %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
+ ret float %e
+}
+
+; CHECK-LABEL: define float @func3(
+define float @func3(float %a, float %b, float %c, i1 %cond) {
+entry:
+ br i1 %cond, label %cond.true, label %cond.false
+
+cond.true:
+ %sub0 = fsub fast float %a, 2.0
+ br label %cond.end
+
+cond.false:
+ %sub1 = fsub fast float %b, 2.0
+ br label %cond.end
+
+; CHECK-LABEL: cond.end
+; CHECK [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ]
+; CHECK fadd fast float %a, [[PHI]]
+cond.end:
+ %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
+ ret float %e
+}
+
+; CHECK-LABEL: define float @func4(
+define float @func4(float %a, float %b, float %c, i1 %cond) {
+entry:
+ br i1 %cond, label %cond.true, label %cond.false
+
+cond.true:
+ %sub0 = fsub fast float %a, 2.0
+ br label %cond.end
+
+cond.false:
+ %sub1 = fsub float %b, 2.0
+ br label %cond.end
+
+; CHECK-LABEL: cond.end
+; CHECK [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ]
+; CHECK fadd float %a, [[PHI]]
+cond.end:
+ %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
+ ret float %e
+}
Added: llvm/trunk/test/Transforms/InstCombine/phi-select-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-select-constant.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-select-constant.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-select-constant.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -S -instcombine | FileCheck %s
+ at A = extern_weak global i32, align 4
+ at B = extern_weak global i32, align 4
+
+define i32 @foo(i1 %which) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
+; CHECK: delay:
+; CHECK-NEXT: br label [[FINAL]]
+; CHECK: final:
+; CHECK-NEXT: [[USE2:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ select (i1 icmp eq (i32* @A, i32* @B), i32 2, i32 1), [[DELAY]] ]
+; CHECK-NEXT: ret i32 [[USE2]]
+;
+entry:
+ br i1 %which, label %final, label %delay
+
+delay:
+ br label %final
+
+final:
+ %use2 = phi i1 [ false, %entry ], [ icmp eq (i32* @A, i32* @B), %delay ]
+ %value = select i1 %use2, i32 2, i32 1
+ ret i32 %value
+}
+
+
+; test folding of select into phi for vectors.
+define <4 x i64> @vec1(i1 %which) {
+; CHECK-LABEL: @vec1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
+; CHECK: delay:
+; CHECK-NEXT: br label [[FINAL]]
+; CHECK: final:
+; CHECK-NEXT: [[PHINODE:%.*]] = phi <4 x i64> [ zeroinitializer, [[ENTRY:%.*]] ], [ <i64 0, i64 0, i64 126, i64 127>, [[DELAY]] ]
+; CHECK-NEXT: ret <4 x i64> [[PHINODE]]
+;
+entry:
+ br i1 %which, label %final, label %delay
+
+delay:
+ br label %final
+
+final:
+ %phinode = phi <4 x i1> [ <i1 true, i1 true, i1 true, i1 true>, %entry ], [ <i1 true, i1 true, i1 false, i1 false>, %delay ]
+ %sel = select <4 x i1> %phinode, <4 x i64> zeroinitializer, <4 x i64> <i64 124, i64 125, i64 126, i64 127>
+ ret <4 x i64> %sel
+}
+
+define <4 x i64> @vec2(i1 %which) {
+; CHECK-LABEL: @vec2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
+; CHECK: delay:
+; CHECK-NEXT: br label [[FINAL]]
+; CHECK: final:
+; CHECK-NEXT: [[PHINODE:%.*]] = phi <4 x i64> [ <i64 124, i64 125, i64 126, i64 127>, [[ENTRY:%.*]] ], [ <i64 0, i64 125, i64 0, i64 127>, [[DELAY]] ]
+; CHECK-NEXT: ret <4 x i64> [[PHINODE]]
+;
+entry:
+ br i1 %which, label %final, label %delay
+
+delay:
+ br label %final
+
+final:
+ %phinode = phi <4 x i1> [ <i1 false, i1 false, i1 false, i1 false>, %entry ], [ <i1 true, i1 false, i1 true, i1 false>, %delay ]
+ %sel = select <4 x i1> %phinode, <4 x i64> zeroinitializer, <4 x i64> <i64 124, i64 125, i64 126, i64 127>
+ ret <4 x i64> %sel
+}
+
+; Test PR33364
+; Insert the generated select into the same block as the incoming phi value.
+; phi has constant vectors along with a single non-constant vector as operands.
+define <2 x i8> @vec3(i1 %cond1, i1 %cond2, <2 x i1> %x, <2 x i8> %y, <2 x i8> %z) {
+; CHECK-LABEL: @vec3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[PHITMP1:%.*]] = shufflevector <2 x i8> [[Z:%.*]], <2 x i8> [[Y:%.*]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT: br i1 [[COND1:%.*]], label [[IF1:%.*]], label [[ELSE:%.*]]
+; CHECK: if1:
+; CHECK-NEXT: [[PHITMP2:%.*]] = shufflevector <2 x i8> [[Y]], <2 x i8> [[Z]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT: br i1 [[COND2:%.*]], label [[IF2:%.*]], label [[ELSE]]
+; CHECK: if2:
+; CHECK-NEXT: [[PHITMP:%.*]] = select <2 x i1> [[X:%.*]], <2 x i8> [[Y]], <2 x i8> [[Z]]
+; CHECK-NEXT: br label [[ELSE]]
+; CHECK: else:
+; CHECK-NEXT: [[PHI:%.*]] = phi <2 x i8> [ [[PHITMP]], [[IF2]] ], [ [[PHITMP1]], [[ENTRY:%.*]] ], [ [[PHITMP2]], [[IF1]] ]
+; CHECK-NEXT: ret <2 x i8> [[PHI]]
+;
+entry:
+ br i1 %cond1, label %if1, label %else
+
+if1:
+ br i1 %cond2, label %if2, label %else
+
+if2:
+ br label %else
+
+else:
+ %phi = phi <2 x i1> [ %x, %if2 ], [ <i1 0, i1 1>, %entry ], [ <i1 1, i1 0>, %if1 ]
+ %sel = select <2 x i1> %phi, <2 x i8> %y, <2 x i8> %z
+ ret <2 x i8> %sel
+}
Added: llvm/trunk/test/Transforms/InstCombine/phi-timeout.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi-timeout.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi-timeout.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi-timeout.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S 2>&1 | FileCheck %s
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+
+; We are really checking that this doesn't loop forever. We would never
+; actually get to the checks here if it did.
+
+define void @timeout(i16* nocapture readonly %cinfo) {
+; CHECK-LABEL: @timeout(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i16, i16* [[CINFO:%.*]], i32 2
+; CHECK-NEXT: [[L:%.*]] = load i16, i16* [[ARRAYIDX15]], align 2
+; CHECK-NEXT: [[CMP17:%.*]] = icmp eq i16 [[L]], 0
+; CHECK-NEXT: [[EXTRACT_T1:%.*]] = trunc i16 [[L]] to i8
+; CHECK-NEXT: br i1 [[CMP17]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[DOTPRE:%.*]] = load i16, i16* [[ARRAYIDX15]], align 2
+; CHECK-NEXT: [[EXTRACT_T:%.*]] = trunc i16 [[DOTPRE]] to i8
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[P_OFF0:%.*]] = phi i8 [ [[EXTRACT_T]], [[IF_THEN]] ], [ [[EXTRACT_T1]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[SUB:%.*]] = add i8 [[P_OFF0]], -1
+; CHECK-NEXT: store i8 [[SUB]], i8* undef, align 1
+; CHECK-NEXT: br label [[FOR_BODY]]
+;
+entry:
+ br label %for.body
+
+for.body:
+ %arrayidx15 = getelementptr inbounds i16, i16* %cinfo, i32 2
+ %l = load i16, i16* %arrayidx15, align 2
+ %cmp17 = icmp eq i16 %l, 0
+ br i1 %cmp17, label %if.then, label %if.end
+
+if.then:
+ %.pre = load i16, i16* %arrayidx15, align 2
+ br label %if.end
+
+if.end:
+ %p = phi i16 [ %.pre, %if.then ], [ %l, %for.body ]
+ %conv19 = trunc i16 %p to i8
+ %sub = add i8 %conv19, -1
+ store i8 %sub, i8* undef, align 1
+ br label %for.body
+}
Added: llvm/trunk/test/Transforms/InstCombine/phi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/phi.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/phi.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,881 @@
+; This test makes sure that these instructions are properly eliminated.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128:n8:16:32:64"
+
+define i32 @test1(i32 %A, i1 %b) {
+BB0:
+ br i1 %b, label %BB1, label %BB2
+
+BB1:
+ ; Combine away one argument PHI nodes
+ %B = phi i32 [ %A, %BB0 ]
+ ret i32 %B
+
+BB2:
+ ret i32 %A
+; CHECK-LABEL: @test1(
+; CHECK: BB1:
+; CHECK-NEXT: ret i32 %A
+}
+
+define i32 @test2(i32 %A, i1 %b) {
+BB0:
+ br i1 %b, label %BB1, label %BB2
+
+BB1:
+ br label %BB2
+
+BB2:
+ ; Combine away PHI nodes with same values
+ %B = phi i32 [ %A, %BB0 ], [ %A, %BB1 ]
+ ret i32 %B
+; CHECK-LABEL: @test2(
+; CHECK: BB2:
+; CHECK-NEXT: ret i32 %A
+}
+
+define i32 @test3(i32 %A, i1 %b) {
+BB0:
+ br label %Loop
+
+Loop:
+ ; PHI has same value always.
+ %B = phi i32 [ %A, %BB0 ], [ %B, %Loop ]
+ br i1 %b, label %Loop, label %Exit
+
+Exit:
+ ret i32 %B
+; CHECK-LABEL: @test3(
+; CHECK: Exit:
+; CHECK-NEXT: ret i32 %A
+}
+
+define i32 @test4(i1 %b) {
+BB0:
+ ; Loop is unreachable
+ ret i32 7
+
+Loop: ; preds = %L2, %Loop
+ ; PHI has same value always.
+ %B = phi i32 [ %B, %L2 ], [ %B, %Loop ]
+ br i1 %b, label %L2, label %Loop
+
+L2: ; preds = %Loop
+ br label %Loop
+; CHECK-LABEL: @test4(
+; CHECK: Loop:
+; CHECK-NEXT: br i1 %b
+}
+
+define i32 @test5(i32 %A, i1 %b) {
+BB0:
+ br label %Loop
+
+Loop: ; preds = %Loop, %BB0
+ ; PHI has same value always.
+ %B = phi i32 [ %A, %BB0 ], [ undef, %Loop ]
+ br i1 %b, label %Loop, label %Exit
+
+Exit: ; preds = %Loop
+ ret i32 %B
+; CHECK-LABEL: @test5(
+; CHECK: Loop:
+; CHECK-NEXT: br i1 %b
+; CHECK: Exit:
+; CHECK-NEXT: ret i32 %A
+}
+
+define i32 @test6(i16 %A, i1 %b) {
+BB0:
+ %X = zext i16 %A to i32
+ br i1 %b, label %BB1, label %BB2
+
+BB1:
+ %Y = zext i16 %A to i32
+ br label %BB2
+
+BB2:
+ ;; Suck casts into phi
+ %B = phi i32 [ %X, %BB0 ], [ %Y, %BB1 ]
+ ret i32 %B
+; CHECK-LABEL: @test6(
+; CHECK: BB2:
+; CHECK: zext i16 %A to i32
+; CHECK-NEXT: ret i32
+}
+
+define i32 @test7(i32 %A, i1 %b) {
+BB0:
+ br label %Loop
+
+Loop: ; preds = %Loop, %BB0
+ ; PHI is dead.
+ %B = phi i32 [ %A, %BB0 ], [ %C, %Loop ]
+ %C = add i32 %B, 123
+ br i1 %b, label %Loop, label %Exit
+
+Exit: ; preds = %Loop
+ ret i32 0
+; CHECK-LABEL: @test7(
+; CHECK: Loop:
+; CHECK-NEXT: br i1 %b
+}
+
+define i32* @test8({ i32, i32 } *%A, i1 %b) {
+BB0:
+ %X = getelementptr inbounds { i32, i32 }, { i32, i32 } *%A, i32 0, i32 1
+ br i1 %b, label %BB1, label %BB2
+
+BB1:
+ %Y = getelementptr { i32, i32 }, { i32, i32 } *%A, i32 0, i32 1
+ br label %BB2
+
+BB2:
+ ;; Suck GEPs into phi
+ %B = phi i32* [ %X, %BB0 ], [ %Y, %BB1 ]
+ ret i32* %B
+; CHECK-LABEL: @test8(
+; CHECK-NOT: phi
+; CHECK: BB2:
+; CHECK-NEXT: %B = getelementptr { i32, i32 }, { i32, i32 }* %A
+; CHECK-NEXT: ret i32* %B
+}
+
+define i32 @test9(i32* %A, i32* %B) {
+entry:
+ %c = icmp eq i32* %A, null
+ br i1 %c, label %bb1, label %bb
+
+bb:
+ %C = load i32, i32* %B, align 1
+ br label %bb2
+
+bb1:
+ %D = load i32, i32* %A, align 1
+ br label %bb2
+
+bb2:
+ %E = phi i32 [ %C, %bb ], [ %D, %bb1 ]
+ ret i32 %E
+; CHECK-LABEL: @test9(
+; CHECK: bb2:
+; CHECK-NEXT: phi i32* [ %B, %bb ], [ %A, %bb1 ]
+; CHECK-NEXT: %E = load i32, i32* %{{[^,]*}}, align 1
+; CHECK-NEXT: ret i32 %E
+
+}
+
+define i32 @test10(i32* %A, i32* %B) {
+entry:
+ %c = icmp eq i32* %A, null
+ br i1 %c, label %bb1, label %bb
+
+bb:
+ %C = load i32, i32* %B, align 16
+ br label %bb2
+
+bb1:
+ %D = load i32, i32* %A, align 32
+ br label %bb2
+
+bb2:
+ %E = phi i32 [ %C, %bb ], [ %D, %bb1 ]
+ ret i32 %E
+; CHECK-LABEL: @test10(
+; CHECK: bb2:
+; CHECK-NEXT: phi i32* [ %B, %bb ], [ %A, %bb1 ]
+; CHECK-NEXT: %E = load i32, i32* %{{[^,]*}}, align 16
+; CHECK-NEXT: ret i32 %E
+}
+
+
+; PR1777
+declare i1 @test11a()
+
+define i1 @test11() {
+entry:
+ %a = alloca i32
+ %i = ptrtoint i32* %a to i64
+ %b = call i1 @test11a()
+ br i1 %b, label %one, label %two
+
+one:
+ %x = phi i64 [%i, %entry], [%y, %two]
+ %c = call i1 @test11a()
+ br i1 %c, label %two, label %end
+
+two:
+ %y = phi i64 [%i, %entry], [%x, %one]
+ %d = call i1 @test11a()
+ br i1 %d, label %one, label %end
+
+end:
+ %f = phi i64 [ %x, %one], [%y, %two]
+ ; Change the %f to %i, and the optimizer suddenly becomes a lot smarter
+ ; even though %f must equal %i at this point
+ %g = inttoptr i64 %f to i32*
+ store i32 10, i32* %g
+ %z = call i1 @test11a()
+ ret i1 %z
+; CHECK-LABEL: @test11(
+; CHECK-NOT: phi i32
+; CHECK: ret i1 %z
+}
+
+
+define i64 @test12(i1 %cond, i8* %Ptr, i64 %Val) {
+entry:
+ %tmp41 = ptrtoint i8* %Ptr to i64
+ %tmp42 = zext i64 %tmp41 to i128
+ br i1 %cond, label %end, label %two
+
+two:
+ %tmp36 = zext i64 %Val to i128 ; <i128> [#uses=1]
+ %tmp37 = shl i128 %tmp36, 64 ; <i128> [#uses=1]
+ %ins39 = or i128 %tmp42, %tmp37 ; <i128> [#uses=1]
+ br label %end
+
+end:
+ %tmp869.0 = phi i128 [ %tmp42, %entry ], [ %ins39, %two ]
+ %tmp32 = trunc i128 %tmp869.0 to i64 ; <i64> [#uses=1]
+ %tmp29 = lshr i128 %tmp869.0, 64 ; <i128> [#uses=1]
+ %tmp30 = trunc i128 %tmp29 to i64 ; <i64> [#uses=1]
+
+ %tmp2 = add i64 %tmp32, %tmp30
+ ret i64 %tmp2
+; CHECK-LABEL: @test12(
+; CHECK-NOT: zext
+; CHECK: end:
+; CHECK-NEXT: phi i64 [ 0, %entry ], [ %Val, %two ]
+; CHECK-NOT: phi
+; CHECK: ret i64
+}
+
+declare void @test13f(double, i32)
+
+define void @test13(i1 %cond, i32 %V1, double %Vald) {
+entry:
+ %tmp42 = zext i32 %V1 to i128
+ br i1 %cond, label %end, label %two
+
+two:
+ %Val = bitcast double %Vald to i64
+ %tmp36 = zext i64 %Val to i128 ; <i128> [#uses=1]
+ %tmp37 = shl i128 %tmp36, 64 ; <i128> [#uses=1]
+ %ins39 = or i128 %tmp42, %tmp37 ; <i128> [#uses=1]
+ br label %end
+
+end:
+ %tmp869.0 = phi i128 [ %tmp42, %entry ], [ %ins39, %two ]
+ %tmp32 = trunc i128 %tmp869.0 to i32
+ %tmp29 = lshr i128 %tmp869.0, 64 ; <i128> [#uses=1]
+ %tmp30 = trunc i128 %tmp29 to i64 ; <i64> [#uses=1]
+ %tmp31 = bitcast i64 %tmp30 to double
+
+ call void @test13f(double %tmp31, i32 %tmp32)
+ ret void
+; CHECK-LABEL: @test13(
+; CHECK-NOT: zext
+; CHECK: end:
+; CHECK-NEXT: phi double [ 0.000000e+00, %entry ], [ %Vald, %two ]
+; CHECK-NEXT: call void @test13f(double {{[^,]*}}, i32 %V1)
+; CHECK: ret void
+}
+
+define i640 @test14a(i320 %A, i320 %B, i1 %b1) {
+BB0:
+ %a = zext i320 %A to i640
+ %b = zext i320 %B to i640
+ br label %Loop
+
+Loop:
+ %C = phi i640 [ %a, %BB0 ], [ %b, %Loop ]
+ br i1 %b1, label %Loop, label %Exit
+
+Exit: ; preds = %Loop
+ ret i640 %C
+; CHECK-LABEL: @test14a(
+; CHECK: Loop:
+; CHECK-NEXT: phi i320
+}
+
+define i160 @test14b(i320 %A, i320 %B, i1 %b1) {
+BB0:
+ %a = trunc i320 %A to i160
+ %b = trunc i320 %B to i160
+ br label %Loop
+
+Loop:
+ %C = phi i160 [ %a, %BB0 ], [ %b, %Loop ]
+ br i1 %b1, label %Loop, label %Exit
+
+Exit: ; preds = %Loop
+ ret i160 %C
+; CHECK-LABEL: @test14b(
+; CHECK: Loop:
+; CHECK-NEXT: phi i160
+}
+
+declare i64 @test15a(i64)
+
+define i64 @test15b(i64 %A, i1 %b) {
+; CHECK-LABEL: @test15b(
+entry:
+ %i0 = zext i64 %A to i128
+ %i1 = shl i128 %i0, 64
+ %i = or i128 %i1, %i0
+ br i1 %b, label %one, label %two
+; CHECK: entry:
+; CHECK-NEXT: br i1 %b
+
+one:
+ %x = phi i128 [%i, %entry], [%y, %two]
+ %x1 = lshr i128 %x, 64
+ %x2 = trunc i128 %x1 to i64
+ %c = call i64 @test15a(i64 %x2)
+ %c1 = zext i64 %c to i128
+ br label %two
+
+; CHECK: one:
+; CHECK-NEXT: phi i64
+; CHECK-NEXT: %c = call i64 @test15a
+
+two:
+ %y = phi i128 [%i, %entry], [%c1, %one]
+ %y1 = lshr i128 %y, 64
+ %y2 = trunc i128 %y1 to i64
+ %d = call i64 @test15a(i64 %y2)
+ %d1 = trunc i64 %d to i1
+ br i1 %d1, label %one, label %end
+
+; CHECK: two:
+; CHECK-NEXT: phi i64
+; CHECK-NEXT: phi i64
+; CHECK-NEXT: %d = call i64 @test15a
+
+end:
+ %g = trunc i128 %y to i64
+ ret i64 %g
+; CHECK: end:
+; CHECK-NEXT: ret i64
+}
+
+; PR6512 - Shouldn't merge loads from different addr spaces.
+define i32 @test16(i32 addrspace(1)* %pointer1, i32 %flag, i32* %pointer2)
+nounwind {
+entry:
+ %retval = alloca i32, align 4 ; <i32*> [#uses=2]
+ %pointer1.addr = alloca i32 addrspace(1)*, align 4 ; <i32 addrspace(1)**>
+ %flag.addr = alloca i32, align 4 ; <i32*> [#uses=2]
+ %pointer2.addr = alloca i32*, align 4 ; <i32**> [#uses=2]
+ %res = alloca i32, align 4 ; <i32*> [#uses=4]
+ store i32 addrspace(1)* %pointer1, i32 addrspace(1)** %pointer1.addr
+ store i32 %flag, i32* %flag.addr
+ store i32* %pointer2, i32** %pointer2.addr
+ store i32 10, i32* %res
+ %tmp = load i32, i32* %flag.addr ; <i32> [#uses=1]
+ %tobool = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %if.then, label %if.else
+
+return: ; preds = %if.end
+ %tmp7 = load i32, i32* %retval ; <i32> [#uses=1]
+ ret i32 %tmp7
+
+if.end: ; preds = %if.else, %if.then
+ %tmp6 = load i32, i32* %res ; <i32> [#uses=1]
+ store i32 %tmp6, i32* %retval
+ br label %return
+
+if.then: ; preds = %entry
+ %tmp1 = load i32 addrspace(1)*, i32 addrspace(1)** %pointer1.addr ; <i32 addrspace(1)*>
+ %arrayidx = getelementptr i32, i32 addrspace(1)* %tmp1, i32 0 ; <i32 addrspace(1)*> [#uses=1]
+ %tmp2 = load i32, i32 addrspace(1)* %arrayidx ; <i32> [#uses=1]
+ store i32 %tmp2, i32* %res
+ br label %if.end
+
+if.else: ; preds = %entry
+ %tmp3 = load i32*, i32** %pointer2.addr ; <i32*> [#uses=1]
+ %arrayidx4 = getelementptr i32, i32* %tmp3, i32 0 ; <i32*> [#uses=1]
+ %tmp5 = load i32, i32* %arrayidx4 ; <i32> [#uses=1]
+ store i32 %tmp5, i32* %res
+ br label %if.end
+}
+
+; PR4413
+declare i32 @ext()
+; CHECK-LABEL: @test17(
+define i32 @test17(i1 %a) {
+entry:
+ br i1 %a, label %bb1, label %bb2
+
+bb1: ; preds = %entry
+ %0 = tail call i32 @ext() ; <i32> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb1, %entry
+ %cond = phi i1 [ true, %bb1 ], [ false, %entry ] ; <i1> [#uses=1]
+; CHECK-NOT: %val = phi i32 [ %0, %bb1 ], [ 0, %entry ]
+ %val = phi i32 [ %0, %bb1 ], [ 0, %entry ] ; <i32> [#uses=1]
+ %res = select i1 %cond, i32 %val, i32 0 ; <i32> [#uses=1]
+; CHECK: ret i32 %cond
+ ret i32 %res
+}
+
+define i1 @test18(i1 %cond) {
+ %zero = alloca i32
+ %one = alloca i32
+ br i1 %cond, label %true, label %false
+true:
+ br label %ret
+false:
+ br label %ret
+ret:
+ %ptr = phi i32* [ %zero, %true ] , [ %one, %false ]
+ %isnull = icmp eq i32* %ptr, null
+ ret i1 %isnull
+; CHECK-LABEL: @test18(
+; CHECK: ret i1 false
+}
+
+define i1 @test19(i1 %cond, double %x) {
+ br i1 %cond, label %true, label %false
+true:
+ br label %ret
+false:
+ br label %ret
+ret:
+ %p = phi double [ %x, %true ], [ 0x7FF0000000000000, %false ]; RHS = +infty
+ %cmp = fcmp ule double %x, %p
+ ret i1 %cmp
+; CHECK-LABEL: @test19(
+; CHECK: ret i1 true
+}
+
+define i1 @test20(i1 %cond) {
+ %a = alloca i32
+ %b = alloca i32
+ %c = alloca i32
+ br i1 %cond, label %true, label %false
+true:
+ br label %ret
+false:
+ br label %ret
+ret:
+ %p = phi i32* [ %a, %true ], [ %b, %false ]
+ %r = icmp eq i32* %p, %c
+ ret i1 %r
+; CHECK-LABEL: @test20(
+; CHECK: ret i1 false
+}
+
+define i1 @test21(i1 %c1, i1 %c2) {
+ %a = alloca i32
+ %b = alloca i32
+ %c = alloca i32
+ br i1 %c1, label %true, label %false
+true:
+ br label %loop
+false:
+ br label %loop
+loop:
+ %p = phi i32* [ %a, %true ], [ %b, %false ], [ %p, %loop ]
+ %r = icmp eq i32* %p, %c
+ br i1 %c2, label %ret, label %loop
+ret:
+ ret i1 %r
+; CHECK-LABEL: @test21(
+; CHECK: ret i1 false
+}
+
+define void @test22() {
+; CHECK-LABEL: @test22(
+entry:
+ br label %loop
+loop:
+ %phi = phi i32 [ 0, %entry ], [ %y, %loop ]
+ %y = add i32 %phi, 1
+ %o = or i32 %y, %phi
+ %e = icmp eq i32 %o, %y
+ br i1 %e, label %loop, label %ret
+; CHECK: br i1 %e
+ret:
+ ret void
+}
+
+define i32 @test23(i32 %A, i1 %b, i32 * %P) {
+BB0:
+ br label %Loop
+
+Loop: ; preds = %Loop, %BB0
+ ; PHI has same value always.
+ %B = phi i32 [ %A, %BB0 ], [ 42, %Loop ]
+ %D = add i32 %B, 19
+ store i32 %D, i32* %P
+ br i1 %b, label %Loop, label %Exit
+
+Exit: ; preds = %Loop
+ %E = add i32 %B, 19
+ ret i32 %E
+; CHECK-LABEL: @test23(
+; CHECK: %phitmp = add i32 %A, 19
+; CHECK: Loop:
+; CHECK-NEXT: %B = phi i32 [ %phitmp, %BB0 ], [ 61, %Loop ]
+; CHECK: Exit:
+; CHECK-NEXT: ret i32 %B
+}
+
+define i32 @test24(i32 %A, i1 %cond) {
+BB0:
+ %X = add nuw nsw i32 %A, 1
+ br i1 %cond, label %BB1, label %BB2
+
+BB1:
+ %Y = add nuw i32 %A, 1
+ br label %BB2
+
+BB2:
+ %C = phi i32 [ %X, %BB0 ], [ %Y, %BB1 ]
+ ret i32 %C
+; CHECK-LABEL: @test24(
+; CHECK-NOT: phi
+; CHECK: BB2:
+; CHECK-NEXT: %C = add nuw i32 %A, 1
+; CHECK-NEXT: ret i32 %C
+}
+
+; Same as test11, but used to be missed due to a bug.
+declare i1 @test25a()
+
+define i1 @test25() {
+entry:
+ %a = alloca i32
+ %i = ptrtoint i32* %a to i64
+ %b = call i1 @test25a()
+ br i1 %b, label %one, label %two
+
+one:
+ %x = phi i64 [%y, %two], [%i, %entry]
+ %c = call i1 @test25a()
+ br i1 %c, label %two, label %end
+
+two:
+ %y = phi i64 [%x, %one], [%i, %entry]
+ %d = call i1 @test25a()
+ br i1 %d, label %one, label %end
+
+end:
+ %f = phi i64 [ %x, %one], [%y, %two]
+ ; Change the %f to %i, and the optimizer suddenly becomes a lot smarter
+ ; even though %f must equal %i at this point
+ %g = inttoptr i64 %f to i32*
+ store i32 10, i32* %g
+ %z = call i1 @test25a()
+ ret i1 %z
+; CHECK-LABEL: @test25(
+; CHECK-NOT: phi i32
+; CHECK: ret i1 %z
+}
+
+declare i1 @test26a()
+
+define i1 @test26(i32 %n) {
+entry:
+ %a = alloca i32
+ %i = ptrtoint i32* %a to i64
+ %b = call i1 @test26a()
+ br label %one
+
+one:
+ %x = phi i64 [%y, %two], [%w, %three], [%i, %entry]
+ %c = call i1 @test26a()
+ switch i32 %n, label %end [
+ i32 2, label %two
+ i32 3, label %three
+ ]
+
+two:
+ %y = phi i64 [%x, %one], [%w, %three]
+ %d = call i1 @test26a()
+ switch i32 %n, label %end [
+ i32 10, label %one
+ i32 30, label %three
+ ]
+
+three:
+ %w = phi i64 [%y, %two], [%x, %one]
+ %e = call i1 @test26a()
+ br i1 %e, label %one, label %two
+
+end:
+ %f = phi i64 [ %x, %one], [%y, %two]
+ ; Change the %f to %i, and the optimizer suddenly becomes a lot smarter
+ ; even though %f must equal %i at this point
+ %g = inttoptr i64 %f to i32*
+ store i32 10, i32* %g
+ %z = call i1 @test26a()
+ ret i1 %z
+; CHECK-LABEL: @test26(
+; CHECK-NOT: phi i32
+; CHECK: ret i1 %z
+}
+
+; CHECK-LABEL: @test27(
+; CHECK: ret i32 undef
+define i32 @test27(i1 %b) {
+entry:
+ br label %done
+done:
+ %y = phi i32 [ undef, %entry ]
+ ret i32 %y
+}
+
+; We should be able to fold the zexts to the other side of the phi
+; even though there's a constant value input to the phi. This is
+; because we can shrink that constant to the smaller phi type.
+
+define i1 @PR24766(i8 %x1, i8 %x2, i8 %condition) {
+entry:
+ %conv = sext i8 %condition to i32
+ switch i32 %conv, label %epilog [
+ i32 0, label %sw1
+ i32 1, label %sw2
+ ]
+
+sw1:
+ %cmp1 = icmp eq i8 %x1, %x2
+ %frombool1 = zext i1 %cmp1 to i8
+ br label %epilog
+
+sw2:
+ %cmp2 = icmp sle i8 %x1, %x2
+ %frombool2 = zext i1 %cmp2 to i8
+ br label %epilog
+
+epilog:
+ %conditionMet = phi i8 [ 0, %entry ], [ %frombool2, %sw2 ], [ %frombool1, %sw1 ]
+ %tobool = icmp ne i8 %conditionMet, 0
+ ret i1 %tobool
+
+; CHECK-LABEL: @PR24766(
+; CHECK: %[[RES:.*]] = phi i1 [ false, %entry ], [ %cmp2, %sw2 ], [ %cmp1, %sw1 ]
+; CHECK-NEXT: ret i1 %[[RES]]
+}
+
+; Same as above (a phi with more than 2 operands), but no constants
+
+define i1 @PR24766_no_constants(i8 %x1, i8 %x2, i8 %condition, i1 %another_condition) {
+entry:
+ %frombool0 = zext i1 %another_condition to i8
+ %conv = sext i8 %condition to i32
+ switch i32 %conv, label %epilog [
+ i32 0, label %sw1
+ i32 1, label %sw2
+ ]
+
+sw1:
+ %cmp1 = icmp eq i8 %x1, %x2
+ %frombool1 = zext i1 %cmp1 to i8
+ br label %epilog
+
+sw2:
+ %cmp2 = icmp sle i8 %x1, %x2
+ %frombool2 = zext i1 %cmp2 to i8
+ br label %epilog
+
+epilog:
+ %conditionMet = phi i8 [ %frombool0, %entry ], [ %frombool2, %sw2 ], [ %frombool1, %sw1 ]
+ %tobool = icmp ne i8 %conditionMet, 0
+ ret i1 %tobool
+
+; CHECK-LABEL: @PR24766_no_constants(
+; CHECK: %[[RES:.*]] = phi i1 [ %another_condition, %entry ], [ %cmp2, %sw2 ], [ %cmp1, %sw1 ]
+; CHECK-NEXT: ret i1 %[[RES]]
+}
+
+; Same as above (a phi with more than 2 operands), but two constants
+
+define i1 @PR24766_two_constants(i8 %x1, i8 %x2, i8 %condition) {
+entry:
+ %conv = sext i8 %condition to i32
+ switch i32 %conv, label %epilog [
+ i32 0, label %sw1
+ i32 1, label %sw2
+ ]
+
+sw1:
+ %cmp1 = icmp eq i8 %x1, %x2
+ %frombool1 = zext i1 %cmp1 to i8
+ br label %epilog
+
+sw2:
+ %cmp2 = icmp sle i8 %x1, %x2
+ %frombool2 = zext i1 %cmp2 to i8
+ br label %epilog
+
+epilog:
+ %conditionMet = phi i8 [ 0, %entry ], [ 1, %sw2 ], [ %frombool1, %sw1 ]
+ %tobool = icmp ne i8 %conditionMet, 0
+ ret i1 %tobool
+
+; CHECK-LABEL: @PR24766_two_constants(
+; CHECK: %[[RES:.*]] = phi i1 [ false, %entry ], [ true, %sw2 ], [ %cmp1, %sw1 ]
+; CHECK-NEXT: ret i1 %[[RES]]
+}
+
+; Same as above (a phi with more than 2 operands), but two constants and two variables
+
+define i1 @PR24766_two_constants_two_var(i8 %x1, i8 %x2, i8 %condition) {
+entry:
+ %conv = sext i8 %condition to i32
+ switch i32 %conv, label %epilog [
+ i32 0, label %sw1
+ i32 1, label %sw2
+ i32 2, label %sw3
+ ]
+
+sw1:
+ %cmp1 = icmp eq i8 %x1, %x2
+ %frombool1 = zext i1 %cmp1 to i8
+ br label %epilog
+
+sw2:
+ %cmp2 = icmp sle i8 %x1, %x2
+ %frombool2 = zext i1 %cmp2 to i8
+ br label %epilog
+
+sw3:
+ %cmp3 = icmp sge i8 %x1, %x2
+ %frombool3 = zext i1 %cmp3 to i8
+ br label %epilog
+
+epilog:
+ %conditionMet = phi i8 [ 0, %entry ], [ %frombool2, %sw2 ], [ %frombool1, %sw1 ], [ 1, %sw3 ]
+ %tobool = icmp ne i8 %conditionMet, 0
+ ret i1 %tobool
+
+; CHECK-LABEL: @PR24766_two_constants_two_var(
+; CHECK: %[[RES:.*]] = phi i1 [ false, %entry ], [ %cmp2, %sw2 ], [ %cmp1, %sw1 ], [ true, %sw3 ]
+; CHECK-NEXT: ret i1 %[[RES]]
+}
+
+; CHECK-LABEL: phi_allnonzeroconstant
+; CHECK-NOT: phi i32
+; CHECK: ret i1 false
+define i1 @phi_allnonzeroconstant(i1 %c, i32 %a, i32 %b) {
+entry:
+ br i1 %c, label %if.then, label %if.else
+
+if.then: ; preds = %entry
+ br label %if.end
+
+if.else: ; preds = %entry
+ call void @dummy()
+
+ br label %if.end
+
+if.end: ; preds = %if.else, %if.then
+ %x.0 = phi i32 [ 1, %if.then ], [ 2, %if.else ]
+ %or = or i32 %x.0, %a
+ %cmp1 = icmp eq i32 %or, 0
+ ret i1 %cmp1
+}
+
+declare void @dummy()
+
+; CHECK-LABEL: @phi_knownnonzero_eq
+; CHECK-LABEL: if.then:
+; CHECK-NOT: select
+; CHECK-LABEL: if.end:
+; CHECK: phi i32 [ 1, %if.then ]
+define i1 @phi_knownnonzero_eq(i32 %n, i32 %s, i32* nocapture readonly %P) {
+entry:
+ %tobool = icmp slt i32 %n, %s
+ br i1 %tobool, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ %0 = load i32, i32* %P
+ %cmp = icmp eq i32 %n, %0
+ %1 = select i1 %cmp, i32 1, i32 2
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+ %a.0 = phi i32 [ %1, %if.then ], [ %n, %entry ]
+ %cmp1 = icmp eq i32 %a.0, 0
+ ret i1 %cmp1
+}
+
+; CHECK-LABEL: @phi_knownnonzero_ne
+; CHECK-LABEL: if.then:
+; CHECK-NOT: select
+; CHECK-LABEL: if.end:
+; CHECK: phi i32 [ 1, %if.then ]
+define i1 @phi_knownnonzero_ne(i32 %n, i32 %s, i32* nocapture readonly %P) {
+entry:
+ %tobool = icmp slt i32 %n, %s
+ br i1 %tobool, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ %0 = load i32, i32* %P
+ %cmp = icmp eq i32 %n, %0
+ %1 = select i1 %cmp, i32 1, i32 2
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+ %a.0 = phi i32 [ %1, %if.then ], [ %n, %entry ]
+ %cmp1 = icmp ne i32 %a.0, 0
+ ret i1 %cmp1
+}
+
+; CHECK-LABEL: @phi_knownnonzero_eq_2
+; CHECK-LABEL: if.then:
+; CHECK-NOT: select
+; CHECK-LABEL: if.end:
+; CHECK: phi i32 [ 2, %if.else ]
+define i1 @phi_knownnonzero_eq_2(i32 %n, i32 %s, i32* nocapture readonly %P) {
+entry:
+ %tobool = icmp slt i32 %n, %s
+ br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+ %tobool2 = icmp slt i32 %n, %s
+ br i1 %tobool2, label %if.else, label %if.end
+
+if.else: ; preds = %entry
+ %0 = load i32, i32* %P
+ %cmp = icmp eq i32 %n, %0
+ %1 = select i1 %cmp, i32 1, i32 2
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+ %a.0 = phi i32 [ %1, %if.else], [ %n, %entry ], [2, %if.then]
+ %cmp1 = icmp eq i32 %a.0, 0
+ ret i1 %cmp1
+}
+
+; CHECK-LABEL: @phi_knownnonzero_ne_2
+; CHECK-LABEL: if.then:
+; CHECK-NOT: select
+; CHECK-LABEL: if.end:
+; CHECK: phi i32 [ 2, %if.else ]
+define i1 @phi_knownnonzero_ne_2(i32 %n, i32 %s, i32* nocapture readonly %P) {
+entry:
+ %tobool = icmp slt i32 %n, %s
+ br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+ %tobool2 = icmp slt i32 %n, %s
+ br i1 %tobool2, label %if.else, label %if.end
+
+if.else: ; preds = %entry
+ %0 = load i32, i32* %P
+ %cmp = icmp eq i32 %n, %0
+ %1 = select i1 %cmp, i32 1, i32 2
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+ %a.0 = phi i32 [ %1, %if.else], [ %n, %entry ], [2, %if.then]
+ %cmp1 = icmp ne i32 %a.0, 0
+ ret i1 %cmp1
+}
Added: llvm/trunk/test/Transforms/InstCombine/pow-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-1.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-1.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-1.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,488 @@
+; Test that the pow library call simplifier works correctly.
+;
+; RUN: opt -instcombine -S < %s | FileCheck %s --check-prefixes=CHECK,ANY
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefixes=CHECK,ANY,CHECK-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios7.0 | FileCheck %s --check-prefixes=CHECK,ANY,CHECK-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.8 | FileCheck %s --check-prefixes=CHECK,ANY,CHECK-NO-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios6.0 | FileCheck %s --check-prefixes=CHECK,ANY,CHECK-NO-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-netbsd | FileCheck %s --check-prefixes=CHECK,ANY,CHECK-NO-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=arm-apple-tvos9.0 | FileCheck %s --check-prefixes=CHECK,ANY,CHECK-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=arm-apple-watchos2.0 | FileCheck %s --check-prefixes=CHECK,ANY,CHECK-EXP10
+; rdar://7251832
+; RUN: opt -instcombine -S < %s -mtriple=i386-pc-windows-msvc18 | FileCheck %s --check-prefixes=CHECK,MSVC,VC32,CHECK-NO-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=i386-pc-windows-msvc | FileCheck %s --check-prefixes=CHECK,MSVC,VC51,VC19,CHECK-NO-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-pc-windows-msvc18 | FileCheck %s --check-prefixes=CHECK,MSVC,VC64,CHECK-NO-EXP10
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s --check-prefixes=CHECK,MSVC,VC83,VC19,CHECK-NO-EXP10
+
+; NOTE: The readonly attribute on the pow call should be preserved
+; in the cases below where pow is transformed into another function call.
+
+declare float @powf(float, float) nounwind readonly
+declare double @pow(double, double) nounwind readonly
+declare double @llvm.pow.f64(double, double)
+declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) nounwind readonly
+declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) nounwind readonly
+
+; Check pow(1.0, x) -> 1.0.
+
+define float @test_simplify1(float %x) {
+; CHECK-LABEL: @test_simplify1(
+; ANY-NEXT: ret float 1.000000e+00
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float 1.000000e+00, float [[X:%.*]])
+; VC32-NEXT: ret float [[POW]]
+; VC64-NEXT: ret float 1.000000e+00
+;
+ %retval = call float @powf(float 1.0, float %x)
+ ret float %retval
+}
+
+define <2 x float> @test_simplify1v(<2 x float> %x) {
+; CHECK-LABEL: @test_simplify1v(
+; ANY-NEXT: ret <2 x float> <float 1.000000e+00, float 1.000000e+00>
+; MSVC-NEXT: [[POW:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> [[X:%.*]])
+; MSVC-NEXT: ret <2 x float> [[POW]]
+;
+ %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 1.0, float 1.0>, <2 x float> %x)
+ ret <2 x float> %retval
+}
+
+define double @test_simplify2(double %x) {
+; CHECK-LABEL: @test_simplify2(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %retval = call double @pow(double 1.0, double %x)
+ ret double %retval
+}
+
+define <2 x double> @test_simplify2v(<2 x double> %x) {
+; CHECK-LABEL: @test_simplify2v(
+; ANY-NEXT: ret <2 x double> <double 1.000000e+00, double 1.000000e+00>
+; MSVC-NEXT: [[POW:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 1.000000e+00, double 1.000000e+00>, <2 x double> [[X:%.*]])
+; MSVC-NEXT: ret <2 x double> [[POW]]
+;
+ %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 1.0, double 1.0>, <2 x double> %x)
+ ret <2 x double> %retval
+}
+
+; Check pow(2.0 ** n, x) -> exp2(n * x).
+
+define float @test_simplify3(float %x) {
+; CHECK-LABEL: @test_simplify3(
+; ANY-NEXT: [[EXP2F:%.*]] = call float @exp2f(float [[X:%.*]])
+; ANY-NEXT: ret float [[EXP2F]]
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float 2.000000e+00, float [[X:%.*]])
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float 2.000000e+00, float [[X:%.*]])
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: [[POW:%.*]] = call float @powf(float 2.000000e+00, float [[X:%.*]])
+; VC64-NEXT: ret float [[POW]]
+; VC83-NEXT: [[EXP2F:%.*]] = call float @exp2f(float [[X:%.*]])
+; VC83-NEXT: ret float [[EXP2F]]
+;
+ %retval = call float @powf(float 2.0, float %x)
+ ret float %retval
+}
+
+define double @test_simplify3n(double %x) {
+; CHECK-LABEL: @test_simplify3n(
+; ANY-NEXT: [[MUL:%.*]] = fmul double [[X:%.*]], -2.000000e+00
+; ANY-NEXT: [[EXP2:%.*]] = call double @exp2(double [[MUL]])
+; ANY-NEXT: ret double [[EXP2]]
+; VC19-NEXT: [[MUL:%.*]] = fmul double [[X:%.*]], -2.000000e+00
+; VC19-NEXT: [[EXP2:%.*]] = call double @exp2(double [[MUL]])
+; VC19-NEXT: ret double [[EXP2]]
+; VC32-NEXT: [[POW:%.*]] = call double @pow(double 2.500000e-01, double [[X:%.*]])
+; VC32-NEXT: ret double [[POW]]
+; VC64-NEXT: [[POW:%.*]] = call double @pow(double 2.500000e-01, double [[X:%.*]])
+; VC64-NEXT: ret double [[POW]]
+;
+ %retval = call double @pow(double 0.25, double %x)
+ ret double %retval
+}
+
+define <2 x float> @test_simplify3v(<2 x float> %x) {
+; CHECK-LABEL: @test_simplify3v(
+; ANY-NEXT: [[EXP2:%.*]] = call <2 x float> @llvm.exp2.v2f32(<2 x float> [[X:%.*]])
+; ANY-NEXT: ret <2 x float> [[EXP2]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 2.000000e+00, float 2.000000e+00>, <2 x float> [[X:%.*]])
+; MSVC-NEXT: ret <2 x float> [[POW]]
+;
+ %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 2.0, float 2.0>, <2 x float> %x)
+ ret <2 x float> %retval
+}
+
+define <2 x double> @test_simplify3vn(<2 x double> %x) {
+; CHECK-LABEL: @test_simplify3vn(
+; ANY-NEXT: [[MUL:%.*]] = fmul <2 x double> [[X:%.*]], <double 2.000000e+00, double 2.000000e+00>
+; ANY-NEXT: [[EXP2:%.*]] = call <2 x double> @llvm.exp2.v2f64(<2 x double> [[MUL]])
+; ANY-NEXT: ret <2 x double> [[EXP2]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 4.000000e+00, double 4.000000e+00>, <2 x double> [[X:%.*]])
+; MSVC-NEXT: ret <2 x double> [[POW]]
+;
+ %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 4.0, double 4.0>, <2 x double> %x)
+ ret <2 x double> %retval
+}
+
+define double @test_simplify4(double %x) {
+; CHECK-LABEL: @test_simplify4(
+; ANY-NEXT: [[EXP2:%.*]] = call double @exp2(double [[X:%.*]])
+; ANY-NEXT: ret double [[EXP2]]
+; VC19-NEXT: [[EXP2:%.*]] = call double @exp2(double [[X:%.*]])
+; VC19-NEXT: ret double [[EXP2]]
+; VC32-NEXT: [[POW:%.*]] = call double @pow(double 2.000000e+00, double [[X:%.*]])
+; VC32-NEXT: ret double [[POW]]
+; VC64-NEXT: [[POW:%.*]] = call double @pow(double 2.000000e+00, double [[X:%.*]])
+; VC64-NEXT: ret double [[POW]]
+;
+ %retval = call double @pow(double 2.0, double %x)
+ ret double %retval
+}
+
+define float @test_simplify4n(float %x) {
+; CHECK-LABEL: @test_simplify4n(
+; ANY-NEXT: [[MUL:%.*]] = fmul float [[X:%.*]], 3.000000e+00
+; ANY-NEXT: [[EXP2F:%.*]] = call float @exp2f(float [[MUL]])
+; ANY-NEXT: ret float [[EXP2F]]
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float 8.000000e+00, float [[X:%.*]])
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float 8.000000e+00, float [[X:%.*]])
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: [[POW:%.*]] = call float @powf(float 8.000000e+00, float [[X:%.*]])
+; VC64-NEXT: ret float [[POW]]
+; VC83-NEXT: [[MUL:%.*]] = fmul float [[X:%.*]], 3.000000e+00
+; VC83-NEXT: [[EXP2F:%.*]] = call float @exp2f(float [[MUL]])
+; VC83-NEXT: ret float [[EXP2F]]
+;
+ %retval = call float @powf(float 8.0, float %x)
+ ret float %retval
+}
+
+define <2 x double> @test_simplify4v(<2 x double> %x) {
+; CHECK-LABEL: @test_simplify4v(
+; ANY-NEXT: [[EXP2:%.*]] = call <2 x double> @llvm.exp2.v2f64(<2 x double> [[X:%.*]])
+; ANY-NEXT: ret <2 x double> [[EXP2]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> [[X:%.*]])
+; MSVC-NEXT: ret <2 x double> [[POW]]
+;
+ %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 2.0, double 2.0>, <2 x double> %x)
+ ret <2 x double> %retval
+}
+
+define <2 x float> @test_simplify4vn(<2 x float> %x) {
+; CHECK-LABEL: @test_simplify4vn(
+; ANY-NEXT: [[MUL:%.*]] = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, [[X:%.*]]
+; ANY-NEXT: [[EXP2:%.*]] = call <2 x float> @llvm.exp2.v2f32(<2 x float> [[MUL]])
+; ANY-NEXT: ret <2 x float> [[EXP2]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 5.000000e-01, float 5.000000e-01>, <2 x float> [[X:%.*]])
+; MSVC-NEXT: ret <2 x float> [[POW]]
+;
+ %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 0.5, float 0.5>, <2 x float> %x)
+ ret <2 x float> %retval
+}
+
+; Check pow(x, 0.0) -> 1.0.
+
+define float @test_simplify5(float %x) {
+; CHECK-LABEL: @test_simplify5(
+; ANY-NEXT: ret float 1.000000e+00
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 0.000000e+00)
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 0.000000e+00)
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: ret float 1.000000e+00
+; VC83-NEXT: ret float 1.000000e+00
+;
+ %retval = call float @powf(float %x, float 0.0)
+ ret float %retval
+}
+
+define <2 x float> @test_simplify5v(<2 x float> %x) {
+; CHECK-LABEL: @test_simplify5v(
+; ANY-NEXT: ret <2 x float> <float 1.000000e+00, float 1.000000e+00>
+; MSVC-NEXT: [[POW:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> [[X:%.*]], <2 x float> zeroinitializer)
+; MSVC-NEXT: ret <2 x float> [[POW]]
+;
+ %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 0.0, float 0.0>)
+ ret <2 x float> %retval
+}
+
+define double @test_simplify6(double %x) {
+; CHECK-LABEL: @test_simplify6(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %retval = call double @pow(double %x, double 0.0)
+ ret double %retval
+}
+
+define <2 x double> @test_simplify6v(<2 x double> %x) {
+; CHECK-LABEL: @test_simplify6v(
+; ANY-NEXT: ret <2 x double> <double 1.000000e+00, double 1.000000e+00>
+; MSVC-NEXT: [[POW:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[X:%.*]], <2 x double> zeroinitializer)
+; MSVC-NEXT: ret <2 x double> [[POW]]
+;
+ %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 0.0, double 0.0>)
+ ret <2 x double> %retval
+}
+
+; Check pow(x, 0.5) -> fabs(sqrt(x)), where x != -infinity.
+
+define float @test_simplify7(float %x) {
+; CHECK-LABEL: @test_simplify7(
+; ANY-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[X:%.*]])
+; ANY-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SQRTF]])
+; ANY-NEXT: [[ISINF:%.*]] = fcmp oeq float [[X]], 0xFFF0000000000000
+; ANY-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], float 0x7FF0000000000000, float [[ABS]]
+; ANY-NEXT: ret float [[TMP1]]
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 5.000000e-01)
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 5.000000e-01)
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[X:%.*]])
+; VC64-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SQRTF]])
+; VC64-NEXT: [[ISINF:%.*]] = fcmp oeq float [[X]], 0xFFF0000000000000
+; VC64-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], float 0x7FF0000000000000, float [[ABS]]
+; VC64-NEXT: ret float [[TMP1]]
+; VC83-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[X:%.*]])
+; VC83-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SQRTF]])
+; VC83-NEXT: [[ISINF:%.*]] = fcmp oeq float [[X]], 0xFFF0000000000000
+; VC83-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], float 0x7FF0000000000000, float [[ABS]]
+; VC83-NEXT: ret float [[TMP1]]
+;
+ %retval = call float @powf(float %x, float 0.5)
+ ret float %retval
+}
+
+define double @test_simplify8(double %x) {
+; CHECK-LABEL: @test_simplify8(
+; CHECK-NEXT: [[SQRT:%.*]] = call double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %retval = call double @pow(double %x, double 0.5)
+ ret double %retval
+}
+
+; Check pow(-infinity, 0.5) -> +infinity.
+
+define float @test_simplify9(float %x) {
+; CHECK-LABEL: @test_simplify9(
+; ANY-NEXT: ret float 0x7FF0000000000000
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float 0xFFF0000000000000, float 5.000000e-01)
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float 0xFFF0000000000000, float 5.000000e-01)
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: ret float 0x7FF0000000000000
+; VC83-NEXT: ret float 0x7FF0000000000000
+;
+ %retval = call float @powf(float 0xFFF0000000000000, float 0.5)
+ ret float %retval
+}
+
+define double @test_simplify10(double %x) {
+; CHECK-LABEL: @test_simplify10(
+; CHECK-NEXT: ret double 0x7FF0000000000000
+;
+ %retval = call double @pow(double 0xFFF0000000000000, double 0.5)
+ ret double %retval
+}
+
+; Check pow(x, 1.0) -> x.
+
+define float @test_simplify11(float %x) {
+; CHECK-LABEL: @test_simplify11(
+; ANY-NEXT: ret float [[X:%.*]]
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 1.000000e+00)
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 1.000000e+00)
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: ret float [[X:%.*]]
+; VC83-NEXT: ret float [[X:%.*]]
+;
+ %retval = call float @powf(float %x, float 1.0)
+ ret float %retval
+}
+
+define <2 x float> @test_simplify11v(<2 x float> %x) {
+; CHECK-LABEL: @test_simplify11v(
+; ANY-NEXT: ret <2 x float> [[X:%.*]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> [[X:%.*]], <2 x float> <float 1.000000e+00, float 1.000000e+00>)
+; MSVC-NEXT: ret <2 x float> [[POW]]
+;
+ %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 1.0, float 1.0>)
+ ret <2 x float> %retval
+}
+
+define double @test_simplify12(double %x) {
+; CHECK-LABEL: @test_simplify12(
+; CHECK-NEXT: ret double [[X:%.*]]
+;
+ %retval = call double @pow(double %x, double 1.0)
+ ret double %retval
+}
+
+define <2 x double> @test_simplify12v(<2 x double> %x) {
+; CHECK-LABEL: @test_simplify12v(
+; ANY-NEXT: ret <2 x double> [[X:%.*]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[X:%.*]], <2 x double> <double 1.000000e+00, double 1.000000e+00>)
+; MSVC-NEXT: ret <2 x double> [[POW]]
+;
+ %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 1.0, double 1.0>)
+ ret <2 x double> %retval
+}
+
+; Check pow(x, 2.0) -> x*x.
+
+define float @pow2_strict(float %x) {
+; CHECK-LABEL: @pow2_strict(
+; ANY-NEXT: [[SQUARE:%.*]] = fmul float [[X:%.*]], [[X]]
+; ANY-NEXT: ret float [[SQUARE]]
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 2.000000e+00)
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float 2.000000e+00)
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: [[SQUARE:%.*]] = fmul float [[X:%.*]], [[X]]
+; VC64-NEXT: ret float [[SQUARE]]
+; VC83-NEXT: [[SQUARE:%.*]] = fmul float [[X:%.*]], [[X]]
+; VC83-NEXT: ret float [[SQUARE]]
+;
+ %r = call float @powf(float %x, float 2.0)
+ ret float %r
+}
+
+define <2 x float> @pow2_strictv(<2 x float> %x) {
+; CHECK-LABEL: @pow2_strictv(
+; ANY-NEXT: [[SQUARE:%.*]] = fmul <2 x float> [[X:%.*]], [[X]]
+; ANY-NEXT: ret <2 x float> [[SQUARE]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> [[X:%.*]], <2 x float> <float 2.000000e+00, float 2.000000e+00>)
+; MSVC-NEXT: ret <2 x float> [[POW]]
+;
+ %r = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 2.0, float 2.0>)
+ ret <2 x float> %r
+}
+
+define double @pow2_double_strict(double %x) {
+; CHECK-LABEL: @pow2_double_strict(
+; CHECK-NEXT: [[SQUARE:%.*]] = fmul double [[X:%.*]], [[X]]
+; CHECK-NEXT: ret double [[SQUARE]]
+;
+ %r = call double @pow(double %x, double 2.0)
+ ret double %r
+}
+
+define <2 x double> @pow2_double_strictv(<2 x double> %x) {
+; CHECK-LABEL: @pow2_double_strictv(
+; ANY-NEXT: [[SQUARE:%.*]] = fmul <2 x double> [[X:%.*]], [[X]]
+; ANY-NEXT: ret <2 x double> [[SQUARE]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[X:%.*]], <2 x double> <double 2.000000e+00, double 2.000000e+00>)
+; MSVC-NEXT: ret <2 x double> [[POW]]
+;
+ %r = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.0, double 2.0>)
+ ret <2 x double> %r
+}
+
+; Don't drop the FMF - PR35601 ( https://bugs.llvm.org/show_bug.cgi?id=35601 )
+
+define float @pow2_fast(float %x) {
+; CHECK-LABEL: @pow2_fast(
+; ANY-NEXT: [[SQUARE:%.*]] = fmul fast float [[X:%.*]], [[X]]
+; ANY-NEXT: ret float [[SQUARE]]
+; VC32-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 2.000000e+00)
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 2.000000e+00)
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: [[SQUARE:%.*]] = fmul fast float [[X:%.*]], [[X]]
+; VC64-NEXT: ret float [[SQUARE]]
+; VC83-NEXT: [[SQUARE:%.*]] = fmul fast float [[X:%.*]], [[X]]
+; VC83-NEXT: ret float [[SQUARE]]
+;
+ %r = call fast float @powf(float %x, float 2.0)
+ ret float %r
+}
+
+; Check pow(x, -1.0) -> 1.0/x.
+
+define float @pow_neg1_strict(float %x) {
+; CHECK-LABEL: @pow_neg1_strict(
+; ANY-NEXT: [[RECIPROCAL:%.*]] = fdiv float 1.000000e+00, [[X:%.*]]
+; ANY-NEXT: ret float [[RECIPROCAL]]
+; VC32-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float -1.000000e+00)
+; VC32-NEXT: ret float [[POW]]
+; VC51-NEXT: [[POW:%.*]] = call float @powf(float [[X:%.*]], float -1.000000e+00)
+; VC51-NEXT: ret float [[POW]]
+; VC64-NEXT: [[RECIPROCAL:%.*]] = fdiv float 1.000000e+00, [[X:%.*]]
+; VC64-NEXT: ret float [[RECIPROCAL]]
+; VC83-NEXT: [[RECIPROCAL:%.*]] = fdiv float 1.000000e+00, [[X:%.*]]
+; VC83-NEXT: ret float [[RECIPROCAL]]
+;
+ %r = call float @powf(float %x, float -1.0)
+ ret float %r
+}
+
+define <2 x float> @pow_neg1_strictv(<2 x float> %x) {
+; CHECK-LABEL: @pow_neg1_strictv(
+; ANY-NEXT: [[RECIPROCAL:%.*]] = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, [[X:%.*]]
+; ANY-NEXT: ret <2 x float> [[RECIPROCAL]]
+; MSVC-NEXT: [[POW:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> [[X:%.*]], <2 x float> <float -1.000000e+00, float -1.000000e+00>)
+; MSVC-NEXT: ret <2 x float> [[POW]]
+;
+ %r = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float -1.0, float -1.0>)
+ ret <2 x float> %r
+}
+
+define double @pow_neg1_double_fast(double %x) {
+; CHECK-LABEL: @pow_neg1_double_fast(
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv fast double 1.000000e+00, [[X:%.*]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %r = call fast double @pow(double %x, double -1.0)
+ ret double %r
+}
+
+define <2 x double> @pow_neg1_double_fastv(<2 x double> %x) {
+; CHECK-LABEL: @pow_neg1_double_fastv(
+; ANY-NEXT: [[RECIPROCAL:%.*]] = fdiv fast <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[X:%.*]]
+; ANY-NEXT: ret <2 x double> [[RECIPROCAL]]
+; MSVC-NEXT: [[POW:%.*]] = call fast <2 x double> @llvm.pow.v2f64(<2 x double> [[X:%.*]], <2 x double> <double -1.000000e+00, double -1.000000e+00>)
+; MSVC-NEXT: ret <2 x double> [[POW]]
+;
+ %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -1.0, double -1.0>)
+ ret <2 x double> %r
+}
+
+define double @test_simplify17(double %x) {
+; CHECK-LABEL: @test_simplify17(
+; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %retval = call double @llvm.pow.f64(double %x, double 0.5)
+ ret double %retval
+}
+
+; Check pow(10.0, x) -> __exp10(x) on OS X 10.9+ and iOS 7.0+.
+
+define float @test_simplify18(float %x) {
+; CHECK-LABEL: @test_simplify18(
+; CHECK-EXP10-NEXT: [[__EXP10F:%.*]] = call float @__exp10f(float [[X:%.*]])
+; CHECK-EXP10-NEXT: ret float [[__EXP10F]]
+; CHECK-NO-EXP10-NEXT: [[RETVAL:%.*]] = call float @powf(float 1.000000e+01, float [[X:%.*]])
+; CHECK-NO-EXP10-NEXT: ret float [[RETVAL]]
+;
+ %retval = call float @powf(float 10.0, float %x)
+ ret float %retval
+}
+
+define double @test_simplify19(double %x) {
+; CHECK-LABEL: @test_simplify19(
+; CHECK-EXP10-NEXT: [[__EXP10:%.*]] = call double @__exp10(double [[X:%.*]])
+; CHECK-EXP10-NEXT: ret double [[__EXP10]]
+; CHECK-NO-EXP10-NEXT: [[RETVAL:%.*]] = call double @pow(double 1.000000e+01, double [[X:%.*]])
+; CHECK-NO-EXP10-NEXT: ret double [[RETVAL]]
+;
+ %retval = call double @pow(double 10.0, double %x)
+ ret double %retval
+}
Added: llvm/trunk/test/Transforms/InstCombine/pow-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-2.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-2.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-2.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; Test that the pow library call simplifier works correctly.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare float @pow(double, double)
+
+; Check that pow functions with the wrong prototype aren't simplified.
+
+define float @test_no_simplify1(double %x) {
+; CHECK-LABEL: @test_no_simplify1(
+; CHECK-NEXT: [[RETVAL:%.*]] = call float @pow(double 1.000000e+00, double [[X:%.*]])
+; CHECK-NEXT: ret float [[RETVAL]]
+;
+ %retval = call float @pow(double 1.0, double %x)
+ ret float %retval
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/pow-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-3.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-3.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-3.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; Test that the pow() won't get simplified to when it's disabled.
+;
+; RUN: opt < %s -disable-simplify-libcalls -instcombine -S | FileCheck %s
+
+declare double @llvm.pow.f64(double, double)
+declare double @pow(double, double)
+
+define double @test_simplify_unavailable1(double %x) {
+; CHECK-LABEL: @test_simplify_unavailable1(
+; CHECK-NEXT: [[RETVAL:%.*]] = call double @llvm.pow.f64(double [[X:%.*]], double 5.000000e-01)
+; CHECK-NEXT: ret double [[RETVAL]]
+;
+ %retval = call double @llvm.pow.f64(double %x, double 0.5)
+ ret double %retval
+}
+
+; Shrinking is disabled too.
+
+define float @test_simplify_unavailable2(float %f, float %g) {
+; CHECK-LABEL: @test_simplify_unavailable2(
+; CHECK-NEXT: [[DF:%.*]] = fpext float [[F:%.*]] to double
+; CHECK-NEXT: [[DG:%.*]] = fpext float [[G:%.*]] to double
+; CHECK-NEXT: [[CALL:%.*]] = call fast double @pow(double [[DF]], double [[DG]])
+; CHECK-NEXT: [[FR:%.*]] = fptrunc double [[CALL]] to float
+; CHECK-NEXT: ret float [[FR]]
+;
+ %df = fpext float %f to double
+ %dg = fpext float %g to double
+ %call = call fast double @pow(double %df, double %dg)
+ %fr = fptrunc double %call to float
+ ret float %fr
+}
+
+; Shrinking is disabled for the intrinsic too.
+
+define float @test_simplify_unavailable3(float %f, float %g) {
+; CHECK-LABEL: @test_simplify_unavailable3(
+; CHECK-NEXT: [[DF:%.*]] = fpext float [[F:%.*]] to double
+; CHECK-NEXT: [[DG:%.*]] = fpext float [[G:%.*]] to double
+; CHECK-NEXT: [[CALL:%.*]] = call fast double @llvm.pow.f64(double [[DF]], double [[DG]])
+; CHECK-NEXT: [[FR:%.*]] = fptrunc double [[CALL]] to float
+; CHECK-NEXT: ret float [[FR]]
+;
+ %df = fpext float %f to double
+ %dg = fpext float %g to double
+ %call = call fast double @llvm.pow.f64(double %df, double %dg)
+ %fr = fptrunc double %call to float
+ ret float %fr
+}
Added: llvm/trunk/test/Transforms/InstCombine/pow-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-4.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-4.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-4.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,225 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+declare double @llvm.pow.f64(double, double)
+declare float @llvm.pow.f32(float, float)
+declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
+declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
+declare double @pow(double, double)
+
+; pow(x, 3.0)
+define double @test_simplify_3(double %x) {
+; CHECK-LABEL: @test_simplify_3(
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[TMP1]], [[X]]
+; CHECK-NEXT: ret double [[TMP2]]
+;
+ %1 = call fast double @llvm.pow.f64(double %x, double 3.000000e+00)
+ ret double %1
+}
+
+; powf(x, 4.0)
+define float @test_simplify_4f(float %x) {
+; CHECK-LABEL: @test_simplify_4f(
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast float [[TMP1]], [[TMP1]]
+; CHECK-NEXT: ret float [[TMP2]]
+;
+ %1 = call fast float @llvm.pow.f32(float %x, float 4.000000e+00)
+ ret float %1
+}
+
+; pow(x, 4.0)
+define double @test_simplify_4(double %x) {
+; CHECK-LABEL: @test_simplify_4(
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[TMP1]], [[TMP1]]
+; CHECK-NEXT: ret double [[TMP2]]
+;
+ %1 = call fast double @llvm.pow.f64(double %x, double 4.000000e+00)
+ ret double %1
+}
+
+; powf(x, <15.0, 15.0>)
+define <2 x float> @test_simplify_15(<2 x float> %x) {
+; CHECK-LABEL: @test_simplify_15(
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast <2 x float> [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <2 x float> [[TMP1]], [[X]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <2 x float> [[TMP3]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret <2 x float> [[TMP5]]
+;
+ %1 = call fast <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 1.500000e+01, float 1.500000e+01>)
+ ret <2 x float> %1
+}
+
+; pow(x, -7.0)
+define <2 x double> @test_simplify_neg_7(<2 x double> %x) {
+; CHECK-LABEL: @test_simplify_neg_7(
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast <2 x double> [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <2 x double> [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x double> [[TMP2]], [[X]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <2 x double> [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[TMP4]]
+; CHECK-NEXT: ret <2 x double> [[TMP5]]
+;
+ %1 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -7.000000e+00, double -7.000000e+00>)
+ ret <2 x double> %1
+}
+
+; powf(x, -19.0)
+define float @test_simplify_neg_19(float %x) {
+; CHECK-LABEL: @test_simplify_neg_19(
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast float [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP3]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP1]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP5]], [[X]]
+; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]]
+; CHECK-NEXT: ret float [[TMP7]]
+;
+ %1 = call fast float @llvm.pow.f32(float %x, float -1.900000e+01)
+ ret float %1
+}
+
+; pow(x, 11.23)
+define double @test_simplify_11_23(double %x) {
+; CHECK-LABEL: @test_simplify_11_23(
+; CHECK-NEXT: [[TMP1:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 1.123000e+01)
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %1 = call fast double @llvm.pow.f64(double %x, double 1.123000e+01)
+ ret double %1
+}
+
+; powf(x, 32.0)
+define float @test_simplify_32(float %x) {
+; CHECK-LABEL: @test_simplify_32(
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast float [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP3]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], [[TMP4]]
+; CHECK-NEXT: ret float [[TMP5]]
+;
+ %1 = call fast float @llvm.pow.f32(float %x, float 3.200000e+01)
+ ret float %1
+}
+
+; pow(x, 33.0)
+define double @test_simplify_33(double %x) {
+; CHECK-LABEL: @test_simplify_33(
+; CHECK-NEXT: [[TMP1:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 3.300000e+01)
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %1 = call fast double @llvm.pow.f64(double %x, double 3.300000e+01)
+ ret double %1
+}
+
+; pow(x, 16.5) with double
+define double @test_simplify_16_5(double %x) {
+; CHECK-LABEL: @test_simplify_16_5(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast double @llvm.sqrt.f64(double [[X]])
+; CHECK-NEXT: [[SQUARE:%.*]] = fmul fast double [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[SQUARE]], [[SQUARE]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast double [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast double [[TMP3]], [[SQRT]]
+; CHECK-NEXT: ret double [[TMP4]]
+;
+ %1 = call fast double @llvm.pow.f64(double %x, double 1.650000e+01)
+ ret double %1
+}
+
+; pow(x, -16.5) with double
+define double @test_simplify_neg_16_5(double %x) {
+; CHECK-LABEL: @test_simplify_neg_16_5(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast double @llvm.sqrt.f64(double [[X]])
+; CHECK-NEXT: [[SQUARE:%.*]] = fmul fast double [[X:%.*]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[SQUARE]], [[SQUARE]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast double [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast double [[TMP3]], [[SQRT]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv fast double 1.000000e+00, [[TMP4]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %1 = call fast double @llvm.pow.f64(double %x, double -1.650000e+01)
+ ret double %1
+}
+
+; pow(x, 16.5) with double
+define double @test_simplify_16_5_libcall(double %x) {
+; CHECK-LABEL: @test_simplify_16_5_libcall(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[SQUARE:%.*]] = fmul fast double [[X]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[SQUARE]], [[SQUARE]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast double [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast double [[TMP3]], [[SQRT]]
+; CHECK-NEXT: ret double [[TMP4]]
+;
+ %1 = call fast double @pow(double %x, double 1.650000e+01)
+ ret double %1
+}
+
+; pow(x, -16.5) with double
+define double @test_simplify_neg_16_5_libcall(double %x) {
+; CHECK-LABEL: @test_simplify_neg_16_5_libcall(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[SQUARE:%.*]] = fmul fast double [[X]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[SQUARE]], [[SQUARE]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast double [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast double [[TMP3]], [[SQRT]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv fast double 1.000000e+00, [[TMP4]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %1 = call fast double @pow(double %x, double -1.650000e+01)
+ ret double %1
+}
+
+; pow(x, -8.5) with float
+define float @test_simplify_neg_8_5(float %x) {
+; CHECK-LABEL: @test_simplify_neg_8_5(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast float @llvm.sqrt.f32(float [[X:%.*]])
+; CHECK-NEXT: [[SQUARE:%.*]] = fmul fast float [[X]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[SQUARE]], [[SQUARE]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast float [[TMP1]], [[SQRT]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv fast float 1.000000e+00, [[TMP2]]
+; CHECK-NEXT: ret float [[RECIPROCAL]]
+;
+ %1 = call fast float @llvm.pow.f32(float %x, float -0.450000e+01)
+ ret float %1
+}
+
+; pow(x, 7.5) with <2 x double>
+define <2 x double> @test_simplify_7_5(<2 x double> %x) {
+; CHECK-LABEL: @test_simplify_7_5(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
+; CHECK-NEXT: [[SQUARE:%.*]] = fmul fast <2 x double> [[X]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast <2 x double> [[SQUARE]], [[SQUARE]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <2 x double> [[TMP1]], [[X]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x double> [[SQUARE]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <2 x double> [[TMP3]], [[SQRT]]
+; CHECK-NEXT: ret <2 x double> [[TMP4]]
+;
+ %1 = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 7.500000e+00, double 7.500000e+00>)
+ ret <2 x double> %1
+}
+
+; pow(x, 3.5) with <4 x float>
+define <4 x float> @test_simplify_3_5(<4 x float> %x) {
+; CHECK-LABEL: @test_simplify_3_5(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = fmul fast <4 x float> [[X]], [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <4 x float> [[TMP1]], [[X]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <4 x float> [[TMP2]], [[SQRT]]
+; CHECK-NEXT: ret <4 x float> [[TMP3]]
+;
+ %1 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 3.500000e+00, float 3.500000e+00, float 3.500000e+00, float 3.500000e+00>)
+ ret <4 x float> %1
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/pow-cbrt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-cbrt.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-cbrt.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-cbrt.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,117 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define double @pow_intrinsic_third_fast(double %x) {
+; CHECK-LABEL: @pow_intrinsic_third_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 0x3FD5555555555555)
+; CHECK-NEXT: ret double [[POW]]
+;
+ %pow = call fast double @llvm.pow.f64(double %x, double 0x3fd5555555555555)
+ ret double %pow
+}
+
+define float @powf_intrinsic_third_fast(float %x) {
+; CHECK-LABEL: @powf_intrinsic_third_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float 0x3FD5555560000000)
+; CHECK-NEXT: ret float [[POW]]
+;
+ %pow = call fast float @llvm.pow.f32(float %x, float 0x3fd5555560000000)
+ ret float %pow
+}
+
+define double @pow_intrinsic_third_approx(double %x) {
+; CHECK-LABEL: @pow_intrinsic_third_approx(
+; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double 0x3FD5555555555555)
+; CHECK-NEXT: ret double [[POW]]
+;
+ %pow = call afn double @llvm.pow.f64(double %x, double 0x3fd5555555555555)
+ ret double %pow
+}
+
+define float @powf_intrinsic_third_approx(float %x) {
+; CHECK-LABEL: @powf_intrinsic_third_approx(
+; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float 0x3FD5555560000000)
+; CHECK-NEXT: ret float [[POW]]
+;
+ %pow = call afn float @llvm.pow.f32(float %x, float 0x3fd5555560000000)
+ ret float %pow
+}
+
+define double @pow_libcall_third_fast(double %x) {
+; CHECK-LABEL: @pow_libcall_third_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double 0x3FD5555555555555)
+; CHECK-NEXT: ret double [[POW]]
+;
+ %pow = call fast double @pow(double %x, double 0x3fd5555555555555)
+ ret double %pow
+}
+
+define float @powf_libcall_third_fast(float %x) {
+; CHECK-LABEL: @powf_libcall_third_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 0x3FD5555560000000)
+; CHECK-NEXT: ret float [[POW]]
+;
+ %pow = call fast float @powf(float %x, float 0x3fd5555560000000)
+ ret float %pow
+}
+
+define double @pow_intrinsic_negthird_fast(double %x) {
+; CHECK-LABEL: @pow_intrinsic_negthird_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 0xBFD5555555555555)
+; CHECK-NEXT: ret double [[POW]]
+;
+ %pow = call fast double @llvm.pow.f64(double %x, double 0xbfd5555555555555)
+ ret double %pow
+}
+
+define float @powf_intrinsic_negthird_fast(float %x) {
+; CHECK-LABEL: @powf_intrinsic_negthird_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float 0xBFD5555560000000)
+; CHECK-NEXT: ret float [[POW]]
+;
+ %pow = call fast float @llvm.pow.f32(float %x, float 0xbfd5555560000000)
+ ret float %pow
+}
+
+define double @pow_intrinsic_negthird_approx(double %x) {
+; CHECK-LABEL: @pow_intrinsic_negthird_approx(
+; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double 0xBFD5555555555555)
+; CHECK-NEXT: ret double [[POW]]
+;
+ %pow = call afn double @llvm.pow.f64(double %x, double 0xbfd5555555555555)
+ ret double %pow
+}
+
+define float @powf_intrinsic_negthird_approx(float %x) {
+; CHECK-LABEL: @powf_intrinsic_negthird_approx(
+; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float 0xBFD5555560000000)
+; CHECK-NEXT: ret float [[POW]]
+;
+ %pow = call afn float @llvm.pow.f32(float %x, float 0xbfd5555560000000)
+ ret float %pow
+}
+
+define double @pow_libcall_negthird_fast(double %x) {
+; CHECK-LABEL: @pow_libcall_negthird_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double 0xBFD5555555555555)
+; CHECK-NEXT: ret double [[POW]]
+;
+ %pow = call fast double @pow(double %x, double 0xbfd5555555555555)
+ ret double %pow
+}
+
+define float @powf_libcall_negthird_fast(float %x) {
+; CHECK-LABEL: @powf_libcall_negthird_fast(
+; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 0xBFD5555560000000)
+; CHECK-NEXT: ret float [[POW]]
+;
+ %pow = call fast float @powf(float %x, float 0xbfd5555560000000)
+ ret float %pow
+}
+
+declare double @llvm.pow.f64(double, double) #0
+declare float @llvm.pow.f32(float, float) #0
+declare double @pow(double, double)
+declare float @powf(float, float)
+
+attributes #0 = { nounwind readnone speculatable }
Added: llvm/trunk/test/Transforms/InstCombine/pow-exp-nofastmath.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-exp-nofastmath.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-exp-nofastmath.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-exp-nofastmath.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define double @mypow(double %x, double %y) {
+; CHECK-LABEL: @mypow(
+; CHECK-NEXT: [[CALL:%.*]] = call double @exp(double [[X:%.*]])
+; CHECK-NEXT: [[POW:%.*]] = call double @llvm.pow.f64(double [[CALL]], double [[Y:%.*]])
+; CHECK-NEXT: ret double [[POW]]
+;
+ %call = call double @exp(double %x)
+ %pow = call double @llvm.pow.f64(double %call, double %y)
+ ret double %pow
+}
+
+declare double @exp(double) #1
+declare double @llvm.pow.f64(double, double)
Added: llvm/trunk/test/Transforms/InstCombine/pow-exp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-exp.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-exp.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-exp.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,222 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define float @powf_expf(float %x, float %y) {
+; CHECK-LABEL: @powf_expf(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP:%.*]] = call fast float @llvm.exp.f32(float [[MUL]])
+; CHECK-NEXT: ret float [[EXP]]
+;
+ %call = call fast float @expf(float %x) nounwind readnone
+ %pow = call fast float @llvm.pow.f32(float %call, float %y)
+ ret float %pow
+}
+
+define float @powf_expf_libcall(float %x, float %y) {
+; CHECK-LABEL: @powf_expf_libcall(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXPF:%.*]] = call fast float @expf(float [[MUL]])
+; CHECK-NEXT: ret float [[EXPF]]
+;
+ %call = call fast float @expf(float %x)
+ %pow = call fast float @powf(float %call, float %y)
+ ret float %pow
+}
+
+define double @pow_exp(double %x, double %y) {
+; CHECK-LABEL: @pow_exp(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP:%.*]] = call fast double @llvm.exp.f64(double [[MUL]])
+; CHECK-NEXT: ret double [[EXP]]
+;
+ %call = call fast double @exp(double %x) nounwind readnone
+ %pow = call fast double @llvm.pow.f64(double %call, double %y)
+ ret double %pow
+}
+
+define double @pow_exp_not_intrinsic(double %x, double %y) {
+; CHECK-LABEL: @pow_exp_not_intrinsic(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP:%.*]] = call fast double @llvm.exp.f64(double [[MUL]])
+; CHECK-NEXT: ret double [[EXP]]
+;
+ %call = call fast double @exp(double %x) nounwind readnone
+ %pow = call fast double @pow(double %call, double %y) nounwind readnone
+ ret double %pow
+}
+
+define fp128 @powl_expl(fp128 %x, fp128 %y) {
+; CHECK-LABEL: @powl_expl(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast fp128 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP:%.*]] = call fast fp128 @llvm.exp.f128(fp128 [[MUL]])
+; CHECK-NEXT: ret fp128 [[EXP]]
+;
+ %call = call fast fp128 @expl(fp128 %x) nounwind readnone
+ %pow = call fast fp128 @llvm.pow.f128(fp128 %call, fp128 %y)
+ ret fp128 %pow
+}
+
+define fp128 @powl_expl_not_fast(fp128 %x, fp128 %y) {
+; CHECK-LABEL: @powl_expl_not_fast(
+; CHECK-NEXT: [[CALL:%.*]] = call fp128 @expl(fp128 [[X:%.*]])
+; CHECK-NEXT: [[POW:%.*]] = call fast fp128 @llvm.pow.f128(fp128 [[CALL]], fp128 [[Y:%.*]])
+; CHECK-NEXT: ret fp128 [[POW]]
+;
+ %call = call fp128 @expl(fp128 %x)
+ %pow = call fast fp128 @llvm.pow.f128(fp128 %call, fp128 %y)
+ ret fp128 %pow
+}
+
+define float @powf_exp2f(float %x, float %y) {
+; CHECK-LABEL: @powf_exp2f(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[MUL]])
+; CHECK-NEXT: ret float [[EXP2]]
+;
+ %call = call fast float @exp2f(float %x) nounwind readnone
+ %pow = call fast float @llvm.pow.f32(float %call, float %y)
+ ret float %pow
+}
+
+define float @powf_exp2f_not_intrinsic(float %x, float %y) {
+; CHECK-LABEL: @powf_exp2f_not_intrinsic(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[MUL]])
+; CHECK-NEXT: ret float [[EXP2]]
+;
+ %call = call fast float @exp2f(float %x) nounwind readnone
+ %pow = call fast float @powf(float %call, float %y) nounwind readnone
+ ret float %pow
+}
+
+define double @pow_exp2(double %x, double %y) {
+; CHECK-LABEL: @pow_exp2(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP2:%.*]] = call fast double @llvm.exp2.f64(double [[MUL]])
+; CHECK-NEXT: ret double [[EXP2]]
+;
+ %call = call fast double @exp2(double %x) nounwind readnone
+ %pow = call fast double @llvm.pow.f64(double %call, double %y)
+ ret double %pow
+}
+
+define double @pow_exp2_libcall(double %x, double %y) {
+; CHECK-LABEL: @pow_exp2_libcall(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP2:%.*]] = call fast double @exp2(double [[MUL]])
+; CHECK-NEXT: ret double [[EXP2]]
+;
+ %call = call fast double @exp2(double %x)
+ %pow = call fast double @pow(double %call, double %y)
+ ret double %pow
+}
+
+define fp128 @powl_exp2l(fp128 %x, fp128 %y) {
+; CHECK-LABEL: @powl_exp2l(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast fp128 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP2:%.*]] = call fast fp128 @llvm.exp2.f128(fp128 [[MUL]])
+; CHECK-NEXT: ret fp128 [[EXP2]]
+;
+ %call = call fast fp128 @exp2l(fp128 %x) nounwind readnone
+ %pow = call fast fp128 @llvm.pow.f128(fp128 %call, fp128 %y)
+ ret fp128 %pow
+}
+
+define fp128 @powl_exp2l_not_fast(fp128 %x, fp128 %y) {
+; CHECK-LABEL: @powl_exp2l_not_fast(
+; CHECK-NEXT: [[CALL:%.*]] = call fp128 @exp2l(fp128 [[X:%.*]])
+; CHECK-NEXT: [[POW:%.*]] = call fast fp128 @llvm.pow.f128(fp128 [[CALL]], fp128 [[Y:%.*]])
+; CHECK-NEXT: ret fp128 [[POW]]
+;
+ %call = call fp128 @exp2l(fp128 %x)
+ %pow = call fast fp128 @llvm.pow.f128(fp128 %call, fp128 %y)
+ ret fp128 %pow
+}
+
+; TODO: exp10() is not widely enabled by many targets yet.
+
+define float @powf_exp10f(float %x, float %y) {
+; CHECK-LABEL: @powf_exp10f(
+; CHECK-NEXT: [[CALL:%.*]] = call fast float @exp10f(float [[X:%.*]]) #1
+; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[CALL]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[POW]]
+;
+ %call = call fast float @exp10f(float %x) nounwind readnone
+ %pow = call fast float @llvm.pow.f32(float %call, float %y)
+ ret float %pow
+}
+
+define double @pow_exp10(double %x, double %y) {
+; CHECK-LABEL: @pow_exp10(
+; CHECK-NEXT: [[CALL:%.*]] = call fast double @exp10(double [[X:%.*]]) #1
+; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[CALL]], double [[Y:%.*]])
+; CHECK-NEXT: ret double [[POW]]
+;
+ %call = call fast double @exp10(double %x) nounwind readnone
+ %pow = call fast double @llvm.pow.f64(double %call, double %y)
+ ret double %pow
+}
+
+define fp128 @pow_exp10l(fp128 %x, fp128 %y) {
+; CHECK-LABEL: @pow_exp10l(
+; CHECK-NEXT: [[CALL:%.*]] = call fast fp128 @exp10l(fp128 [[X:%.*]]) #1
+; CHECK-NEXT: [[POW:%.*]] = call fast fp128 @llvm.pow.f128(fp128 [[CALL]], fp128 [[Y:%.*]])
+; CHECK-NEXT: ret fp128 [[POW]]
+;
+ %call = call fast fp128 @exp10l(fp128 %x) nounwind readnone
+ %pow = call fast fp128 @llvm.pow.f128(fp128 %call, fp128 %y)
+ ret fp128 %pow
+}
+
+define float @reuse_fast(float %x, float %y, float * %p) {
+; CHECK-LABEL: @reuse_fast(
+; CHECK-NEXT: [[EXP:%.*]] = call fast float @expf(float [[X:%.*]])
+; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[EXP]], float [[Y:%.*]])
+; CHECK-NEXT: store float [[EXP]], float* [[P:%.*]], align 4
+; CHECK-NEXT: ret float [[POW]]
+;
+ %exp = call fast float @expf(float %x)
+ %pow = call fast float @powf(float %exp, float %y)
+ store float %exp, float *%p, align 4
+ ret float %pow
+}
+
+define fp128 @reuse_libcall(fp128 %x, fp128 %y, fp128 * %p) {
+; CHECK-LABEL: @reuse_libcall(
+; CHECK-NEXT: [[EXP:%.*]] = call fp128 @expl(fp128 [[X:%.*]])
+; CHECK-NEXT: [[POW:%.*]] = call fp128 @powl(fp128 [[EXP]], fp128 [[Y:%.*]])
+; CHECK-NEXT: store fp128 [[EXP]], fp128* [[P:%.*]], align 16
+; CHECK-NEXT: ret fp128 [[POW]]
+;
+ %exp = call fp128 @expl(fp128 %x)
+ %pow = call fp128 @powl(fp128 %exp, fp128 %y)
+ store fp128 %exp, fp128 *%p, align 16
+ ret fp128 %pow
+}
+
+define double @function_pointer(double ()* %fptr, double %p1) {
+; CHECK-LABEL: @function_pointer(
+; CHECK-NEXT: [[CALL1:%.*]] = call fast double [[FPTR:%.*]]()
+; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[CALL1]], double [[P1:%.*]])
+; CHECK-NEXT: ret double [[POW]]
+;
+ %call1 = call fast double %fptr()
+ %pow = call fast double @llvm.pow.f64(double %call1, double %p1)
+ ret double %pow
+}
+
+declare float @expf(float)
+declare double @exp(double)
+declare fp128 @expl(fp128)
+declare float @exp2f(float)
+declare double @exp2(double)
+declare fp128 @exp2l(fp128)
+declare float @exp10f(float)
+declare double @exp10(double)
+declare fp128 @exp10l(fp128)
+declare float @powf(float, float)
+declare double @pow(double, double)
+declare fp128 @powl(fp128, fp128)
+declare float @llvm.pow.f32(float, float)
+declare double @llvm.pow.f64(double, double)
+declare fp128 @llvm.pow.f128(fp128, fp128)
Added: llvm/trunk/test/Transforms/InstCombine/pow-sqrt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pow-sqrt.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pow-sqrt.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pow-sqrt.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,297 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Check the libcall and the intrinsic for each case with differing FMF.
+
+; The transform to sqrt is allowed as long as we deal with -0.0 and -INF.
+
+define double @pow_libcall_half_no_FMF(double %x) {
+; CHECK-LABEL: @pow_libcall_half_no_FMF(
+; CHECK-NEXT: [[SQRT:%.*]] = call double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %pow = call double @pow(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+define double @pow_intrinsic_half_no_FMF(double %x) {
+; CHECK-LABEL: @pow_intrinsic_half_no_FMF(
+; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %pow = call double @llvm.pow.f64(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+; This makes no difference, but FMF are propagated.
+
+define double @pow_libcall_half_approx(double %x) {
+; CHECK-LABEL: @pow_libcall_half_approx(
+; CHECK-NEXT: [[SQRT:%.*]] = call afn double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call afn double @llvm.fabs.f64(double [[SQRT]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %pow = call afn double @pow(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+define <2 x double> @pow_intrinsic_half_approx(<2 x double> %x) {
+; CHECK-LABEL: @pow_intrinsic_half_approx(
+; CHECK-NEXT: [[SQRT:%.*]] = call afn <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq <2 x double> [[X]], <double 0xFFF0000000000000, double 0xFFF0000000000000>
+; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> [[ISINF]], <2 x double> <double 0x7FF0000000000000, double 0x7FF0000000000000>, <2 x double> [[ABS]]
+; CHECK-NEXT: ret <2 x double> [[TMP1]]
+;
+ %pow = call afn <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 5.0e-01, double 5.0e-01>)
+ ret <2 x double> %pow
+}
+
+define float @powf_intrinsic_half_fast(float %x) {
+; CHECK-LABEL: @powf_intrinsic_half_fast(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast float @llvm.sqrt.f32(float [[X:%.*]])
+; CHECK-NEXT: ret float [[SQRT]]
+;
+ %pow = call fast float @llvm.pow.f32(float %x, float 5.0e-01)
+ ret float %pow
+}
+
+; If we can disregard INFs, no need for a select.
+
+define double @pow_libcall_half_ninf(double %x) {
+; CHECK-LABEL: @pow_libcall_half_ninf(
+; CHECK-NEXT: [[SQRT:%.*]] = call ninf double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call ninf double @llvm.fabs.f64(double [[SQRT]])
+; CHECK-NEXT: ret double [[ABS]]
+;
+ %pow = call ninf double @pow(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+define <2 x double> @pow_intrinsic_half_ninf(<2 x double> %x) {
+; CHECK-LABEL: @pow_intrinsic_half_ninf(
+; CHECK-NEXT: [[SQRT:%.*]] = call ninf <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call ninf <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
+; CHECK-NEXT: ret <2 x double> [[ABS]]
+;
+ %pow = call ninf <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 5.0e-01, double 5.0e-01>)
+ ret <2 x double> %pow
+}
+
+; If we can disregard -0.0, no need for fabs.
+
+define double @pow_libcall_half_nsz(double %x) {
+; CHECK-LABEL: @pow_libcall_half_nsz(
+; CHECK-NEXT: [[SQRT:%.*]] = call nsz double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[SQRT]]
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %pow = call nsz double @pow(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+define double @pow_intrinsic_half_nsz(double %x) {
+; CHECK-LABEL: @pow_intrinsic_half_nsz(
+; CHECK-NEXT: [[SQRT:%.*]] = call nsz double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[SQRT]]
+; CHECK-NEXT: ret double [[TMP1]]
+;
+ %pow = call nsz double @llvm.pow.f64(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+; This is just sqrt.
+
+define float @pow_libcall_half_ninf_nsz(float %x) {
+; CHECK-LABEL: @pow_libcall_half_ninf_nsz(
+; CHECK-NEXT: [[SQRTF:%.*]] = call ninf nsz float @sqrtf(float [[X:%.*]])
+; CHECK-NEXT: ret float [[SQRTF]]
+;
+ %pow = call ninf nsz float @powf(float %x, float 5.0e-01)
+ ret float %pow
+}
+
+define double @pow_intrinsic_half_ninf_nsz(double %x) {
+; CHECK-LABEL: @pow_intrinsic_half_ninf_nsz(
+; CHECK-NEXT: [[SQRT:%.*]] = call ninf nsz double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: ret double [[SQRT]]
+;
+ %pow = call ninf nsz double @llvm.pow.f64(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+; Overspecified FMF to test propagation to the new op(s).
+
+define float @pow_libcall_half_fast(float %x) {
+; CHECK-LABEL: @pow_libcall_half_fast(
+; CHECK-NEXT: [[SQRTF:%.*]] = call fast float @sqrtf(float [[X:%.*]])
+; CHECK-NEXT: ret float [[SQRTF]]
+;
+ %pow = call fast float @powf(float %x, float 5.0e-01)
+ ret float %pow
+}
+
+define double @pow_intrinsic_half_fast(double %x) {
+; CHECK-LABEL: @pow_intrinsic_half_fast(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: ret double [[SQRT]]
+;
+ %pow = call fast double @llvm.pow.f64(double %x, double 5.0e-01)
+ ret double %pow
+}
+
+; -0.5 means take the reciprocal.
+
+define float @pow_libcall_neghalf_no_FMF(float %x) {
+; CHECK-LABEL: @pow_libcall_neghalf_no_FMF(
+; CHECK-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SQRTF]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq float [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[ABS_OP:%.*]] = fdiv float 1.000000e+00, [[ABS]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select i1 [[ISINF]], float 0.000000e+00, float [[ABS_OP]]
+; CHECK-NEXT: ret float [[RECIPROCAL]]
+;
+ %pow = call float @powf(float %x, float -5.0e-01)
+ ret float %pow
+}
+
+define <2 x double> @pow_intrinsic_neghalf_no_FMF(<2 x double> %x) {
+; CHECK-LABEL: @pow_intrinsic_neghalf_no_FMF(
+; CHECK-NEXT: [[SQRT:%.*]] = call <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq <2 x double> [[X]], <double 0xFFF0000000000000, double 0xFFF0000000000000>
+; CHECK-NEXT: [[ABS_OP:%.*]] = fdiv <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[ABS]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select <2 x i1> [[ISINF]], <2 x double> zeroinitializer, <2 x double> [[ABS_OP]]
+; CHECK-NEXT: ret <2 x double> [[RECIPROCAL]]
+;
+ %pow = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -5.0e-01, double -5.0e-01>)
+ ret <2 x double> %pow
+}
+
+; If we can disregard INFs, no need for a select.
+
+define double @pow_libcall_neghalf_ninf(double %x) {
+; CHECK-LABEL: @pow_libcall_neghalf_ninf(
+; CHECK-NEXT: [[SQRT:%.*]] = call ninf double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call ninf double @llvm.fabs.f64(double [[SQRT]])
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv ninf double 1.000000e+00, [[ABS]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %pow = call ninf double @pow(double %x, double -5.0e-01)
+ ret double %pow
+}
+
+define <2 x double> @pow_intrinsic_neghalf_ninf(<2 x double> %x) {
+; CHECK-LABEL: @pow_intrinsic_neghalf_ninf(
+; CHECK-NEXT: [[SQRT:%.*]] = call ninf <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call ninf <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv ninf <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[ABS]]
+; CHECK-NEXT: ret <2 x double> [[RECIPROCAL]]
+;
+ %pow = call ninf <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -5.0e-01, double -5.0e-01>)
+ ret <2 x double> %pow
+}
+
+; If we can disregard -0.0, no need for fabs.
+
+define double @pow_libcall_neghalf_nsz(double %x) {
+; CHECK-LABEL: @pow_libcall_neghalf_nsz(
+; CHECK-NEXT: [[SQRT:%.*]] = call nsz double @sqrt(double [[X:%.*]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[SQRT_OP:%.*]] = fdiv nsz double 1.000000e+00, [[SQRT]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select i1 [[ISINF]], double 0.000000e+00, double [[SQRT_OP]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %pow = call nsz double @pow(double %x, double -5.0e-01)
+ ret double %pow
+}
+
+define double @pow_intrinsic_neghalf_nsz(double %x) {
+; CHECK-LABEL: @pow_intrinsic_neghalf_nsz(
+; CHECK-NEXT: [[SQRT:%.*]] = call nsz double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz oeq double [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[SQRT_OP:%.*]] = fdiv nsz double 1.000000e+00, [[SQRT]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select i1 [[ISINF]], double 0.000000e+00, double [[SQRT_OP]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %pow = call nsz double @llvm.pow.f64(double %x, double -5.0e-01)
+ ret double %pow
+}
+
+; This is just recip-sqrt.
+
+define double @pow_intrinsic_neghalf_ninf_nsz(double %x) {
+; CHECK-LABEL: @pow_intrinsic_neghalf_ninf_nsz(
+; CHECK-NEXT: [[SQRT:%.*]] = call ninf nsz double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv ninf nsz double 1.000000e+00, [[SQRT]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %pow = call ninf nsz double @llvm.pow.f64(double %x, double -5.0e-01)
+ ret double %pow
+}
+
+define float @pow_libcall_neghalf_ninf_nsz(float %x) {
+; CHECK-LABEL: @pow_libcall_neghalf_ninf_nsz(
+; CHECK-NEXT: [[SQRTF:%.*]] = call ninf nsz float @sqrtf(float [[X:%.*]])
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv ninf nsz float 1.000000e+00, [[SQRTF]]
+; CHECK-NEXT: ret float [[RECIPROCAL]]
+;
+ %pow = call ninf nsz float @powf(float %x, float -5.0e-01)
+ ret float %pow
+}
+
+; Overspecified FMF to test propagation to the new op(s).
+
+define float @pow_libcall_neghalf_fast(float %x) {
+; CHECK-LABEL: @pow_libcall_neghalf_fast(
+; CHECK-NEXT: [[SQRTF:%.*]] = call fast float @sqrtf(float [[X:%.*]])
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv fast float 1.000000e+00, [[SQRTF]]
+; CHECK-NEXT: ret float [[RECIPROCAL]]
+;
+ %pow = call fast float @powf(float %x, float -5.0e-01)
+ ret float %pow
+}
+
+define float @powf_libcall_neghalf_approx(float %x) {
+; CHECK-LABEL: @powf_libcall_neghalf_approx(
+; CHECK-NEXT: [[SQRTF:%.*]] = call afn float @sqrtf(float [[X:%.*]])
+; CHECK-NEXT: [[ABS:%.*]] = call afn float @llvm.fabs.f32(float [[SQRTF]])
+; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq float [[X]], 0xFFF0000000000000
+; CHECK-NEXT: [[ABS_OP:%.*]] = fdiv afn float 1.000000e+00, [[ABS]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select i1 [[ISINF]], float 0.000000e+00, float [[ABS_OP]]
+; CHECK-NEXT: ret float [[RECIPROCAL]]
+;
+ %pow = call afn float @powf(float %x, float -5.0e-01)
+ ret float %pow
+}
+
+define double @pow_intrinsic_neghalf_fast(double %x) {
+; CHECK-LABEL: @pow_intrinsic_neghalf_fast(
+; CHECK-NEXT: [[SQRT:%.*]] = call fast double @llvm.sqrt.f64(double [[X:%.*]])
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = fdiv fast double 1.000000e+00, [[SQRT]]
+; CHECK-NEXT: ret double [[RECIPROCAL]]
+;
+ %pow = call fast double @llvm.pow.f64(double %x, double -5.0e-01)
+ ret double %pow
+}
+
+declare double @llvm.pow.f64(double, double) #0
+declare float @llvm.pow.f32(float, float) #0
+declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) #0
+declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) #0
+declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) #0
+declare double @pow(double, double)
+declare float @powf(float, float)
+
+attributes #0 = { nounwind readnone speculatable }
+attributes #1 = { nounwind readnone }
Added: llvm/trunk/test/Transforms/InstCombine/pr12251.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr12251.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr12251.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr12251.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,15 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define zeroext i1 @_Z3fooPb(i8* nocapture %x) {
+entry:
+ %a = load i8, i8* %x, align 1, !range !0
+ %b = and i8 %a, 1
+ %tobool = icmp ne i8 %b, 0
+ ret i1 %tobool
+}
+
+; CHECK: %a = load i8, i8* %x, align 1, !range !0
+; CHECK-NEXT: %tobool = icmp ne i8 %a, 0
+; CHECK-NEXT: ret i1 %tobool
+
+!0 = !{i8 0, i8 2}
Added: llvm/trunk/test/Transforms/InstCombine/pr12338.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr12338.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr12338.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr12338.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,24 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define void @entry() nounwind {
+entry:
+ br label %for.cond
+
+; CHECK: br label %for.cond
+for.cond:
+ %local = phi <1 x i32> [ <i32 0>, %entry ], [ %phi2, %cond.end47 ]
+ %phi3 = sub <1 x i32> zeroinitializer, %local
+ br label %cond.end
+
+cond.false:
+ br label %cond.end
+
+cond.end:
+ %cond = phi <1 x i32> [ %phi3, %for.cond ], [ undef, %cond.false ]
+ br label %cond.end47
+
+cond.end47:
+ %sum = add <1 x i32> %cond, <i32 92>
+ %phi2 = sub <1 x i32> zeroinitializer, %sum
+ br label %for.cond
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr17827.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr17827.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr17827.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr17827.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; With left shift, the comparison should not be modified.
+define i1 @test_shift_and_cmp_not_changed1(i8 %p) {
+; CHECK-LABEL: @test_shift_and_cmp_not_changed1(
+; CHECK-NEXT: [[SHLP:%.*]] = shl i8 %p, 5
+; CHECK-NEXT: [[ANDP:%.*]] = and i8 [[SHLP]], -64
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shlp = shl i8 %p, 5
+ %andp = and i8 %shlp, -64
+ %cmp = icmp slt i8 %andp, 32
+ ret i1 %cmp
+}
+
+; With arithmetic right shift, the comparison should not be modified.
+define i1 @test_shift_and_cmp_not_changed2(i8 %p) {
+; CHECK-LABEL: @test_shift_and_cmp_not_changed2(
+; CHECK-NEXT: [[SHLP:%.*]] = ashr i8 %p, 5
+; CHECK-NEXT: [[ANDP:%.*]] = and i8 [[SHLP]], -64
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shlp = ashr i8 %p, 5
+ %andp = and i8 %shlp, -64
+ %cmp = icmp slt i8 %andp, 32
+ ret i1 %cmp
+}
+
+; This should simplify functionally to the left shift case.
+; The extra input parameter should be optimized away.
+define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) {
+; CHECK-LABEL: @test_shift_and_cmp_changed1(
+; CHECK-NEXT: [[ANDP:%.*]] = shl i8 %p, 5
+; CHECK-NEXT: [[SHL:%.*]] = and i8 [[ANDP]], -64
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[SHL]], 32
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %andp = and i8 %p, 6
+ %andq = and i8 %q, 8
+ %or = or i8 %andq, %andp
+ %shl = shl i8 %or, 5
+ %ashr = ashr i8 %shl, 5
+ %cmp = icmp slt i8 %ashr, 1
+ ret i1 %cmp
+}
+
+define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) {
+; CHECK-LABEL: @test_shift_and_cmp_changed1_vec(
+; CHECK-NEXT: [[ANDP:%.*]] = shl <2 x i8> [[P:%.*]], <i8 5, i8 5>
+; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[ANDP]], <i8 -64, i8 -64>
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[SHL]], <i8 32, i8 32>
+; CHECK-NEXT: ret <2 x i1> [[CMP]]
+;
+ %andp = and <2 x i8> %p, <i8 6, i8 6>
+ %andq = and <2 x i8> %q, <i8 8, i8 8>
+ %or = or <2 x i8> %andq, %andp
+ %shl = shl <2 x i8> %or, <i8 5, i8 5>
+ %ashr = ashr <2 x i8> %shl, <i8 5, i8 5>
+ %cmp = icmp slt <2 x i8> %ashr, <i8 1, i8 1>
+ ret <2 x i1> %cmp
+}
+
+; Unsigned compare allows a transformation to compare against 0.
+define i1 @test_shift_and_cmp_changed2(i8 %p) {
+; CHECK-LABEL: @test_shift_and_cmp_changed2(
+; CHECK-NEXT: [[ANDP:%.*]] = and i8 %p, 6
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[ANDP]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shlp = shl i8 %p, 5
+ %andp = and i8 %shlp, -64
+ %cmp = icmp ult i8 %andp, 32
+ ret i1 %cmp
+}
+
+define <2 x i1> @test_shift_and_cmp_changed2_vec(<2 x i8> %p) {
+; CHECK-LABEL: @test_shift_and_cmp_changed2_vec(
+; CHECK-NEXT: [[ANDP:%.*]] = and <2 x i8> %p, <i8 6, i8 6>
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[ANDP]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[CMP]]
+;
+ %shlp = shl <2 x i8> %p, <i8 5, i8 5>
+ %andp = and <2 x i8> %shlp, <i8 -64, i8 -64>
+ %cmp = icmp ult <2 x i8> %andp, <i8 32, i8 32>
+ ret <2 x i1> %cmp
+}
+
+; nsw on the shift should not affect the comparison.
+define i1 @test_shift_and_cmp_changed3(i8 %p) {
+; CHECK-LABEL: @test_shift_and_cmp_changed3(
+; CHECK-NEXT: [[SHLP:%.*]] = shl nsw i8 %p, 5
+; CHECK-NEXT: [[ANDP:%.*]] = and i8 [[SHLP]], -64
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ANDP]], 32
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shlp = shl nsw i8 %p, 5
+ %andp = and i8 %shlp, -64
+ %cmp = icmp slt i8 %andp, 32
+ ret i1 %cmp
+}
+
+; Logical shift right allows a return true because the 'and' guarantees no bits are set.
+define i1 @test_shift_and_cmp_changed4(i8 %p) {
+; CHECK-LABEL: @test_shift_and_cmp_changed4(
+; CHECK-NEXT: ret i1 true
+;
+ %shlp = lshr i8 %p, 5
+ %andp = and i8 %shlp, -64
+ %cmp = icmp slt i8 %andp, 32
+ ret i1 %cmp
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/pr19420.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr19420.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr19420.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr19420.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,89 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define <4 x i32> @test_FoldShiftByConstant_CreateSHL(<4 x i32> %in) {
+; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL(
+; CHECK-NEXT: [[VSHL_N:%.*]] = mul <4 x i32> %in, <i32 0, i32 -32, i32 0, i32 -32>
+; CHECK-NEXT: ret <4 x i32> [[VSHL_N]]
+;
+ %mul.i = mul <4 x i32> %in, <i32 0, i32 -1, i32 0, i32 -1>
+ %vshl_n = shl <4 x i32> %mul.i, <i32 5, i32 5, i32 5, i32 5>
+ ret <4 x i32> %vshl_n
+}
+
+define <8 x i16> @test_FoldShiftByConstant_CreateSHL2(<8 x i16> %in) {
+; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL2(
+; CHECK-NEXT: [[VSHL_N:%.*]] = mul <8 x i16> %in, <i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32>
+; CHECK-NEXT: ret <8 x i16> [[VSHL_N]]
+;
+ %mul.i = mul <8 x i16> %in, <i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1>
+ %vshl_n = shl <8 x i16> %mul.i, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+ ret <8 x i16> %vshl_n
+}
+
+define <16 x i8> @test_FoldShiftByConstant_CreateAnd(<16 x i8> %in0) {
+; CHECK-LABEL: @test_FoldShiftByConstant_CreateAnd(
+; CHECK-NEXT: [[VSRA_N2:%.*]] = mul <16 x i8> %in0, <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33>
+; CHECK-NEXT: [[VSHL_N:%.*]] = and <16 x i8> [[VSRA_N2]], <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32>
+; CHECK-NEXT: ret <16 x i8> [[VSHL_N]]
+;
+ %vsra_n = ashr <16 x i8> %in0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+ %tmp = add <16 x i8> %in0, %vsra_n
+ %vshl_n = shl <16 x i8> %tmp, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+ ret <16 x i8> %vshl_n
+}
+
+define i32 @bar(i32 %x, i32 %y) {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT: [[B1:%.*]] = shl i32 %y, 4
+; CHECK-NEXT: [[A2:%.*]] = add i32 [[B1]], %x
+; CHECK-NEXT: [[C:%.*]] = and i32 [[A2]], -16
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %a = lshr i32 %x, 4
+ %b = add i32 %a, %y
+ %c = shl i32 %b, 4
+ ret i32 %c
+}
+
+define <2 x i32> @bar_v2i32(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @bar_v2i32(
+; CHECK-NEXT: [[B1:%.*]] = shl <2 x i32> %y, <i32 5, i32 5>
+; CHECK-NEXT: [[A2:%.*]] = add <2 x i32> [[B1]], %x
+; CHECK-NEXT: [[C:%.*]] = and <2 x i32> [[A2]], <i32 -32, i32 -32>
+; CHECK-NEXT: ret <2 x i32> [[C]]
+;
+ %a = lshr <2 x i32> %x, <i32 5, i32 5>
+ %b = add <2 x i32> %a, %y
+ %c = shl <2 x i32> %b, <i32 5, i32 5>
+ ret <2 x i32> %c
+}
+
+define i32 @foo(i32 %x, i32 %y) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: [[C1:%.*]] = shl i32 %y, 4
+; CHECK-NEXT: [[X_MASK:%.*]] = and i32 %x, 128
+; CHECK-NEXT: [[D:%.*]] = add i32 [[X_MASK]], [[C1]]
+; CHECK-NEXT: ret i32 [[D]]
+;
+ %a = lshr i32 %x, 4
+ %b = and i32 %a, 8
+ %c = add i32 %b, %y
+ %d = shl i32 %c, 4
+ ret i32 %d
+}
+
+define <2 x i32> @foo_v2i32(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @foo_v2i32(
+; CHECK-NEXT: [[A:%.*]] = lshr <2 x i32> %x, <i32 4, i32 4>
+; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[A]], <i32 8, i32 8>
+; CHECK-NEXT: [[C:%.*]] = add <2 x i32> [[B]], %y
+; CHECK-NEXT: [[D:%.*]] = shl <2 x i32> [[C]], <i32 4, i32 4>
+; CHECK-NEXT: ret <2 x i32> [[D]]
+;
+ %a = lshr <2 x i32> %x, <i32 4, i32 4>
+ %b = and <2 x i32> %a, <i32 8, i32 8>
+ %c = add <2 x i32> %b, %y
+ %d = shl <2 x i32> %c, <i32 4, i32 4>
+ ret <2 x i32> %d
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/pr20079.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr20079.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr20079.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr20079.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,9 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+ at b = internal global [1 x i32] zeroinitializer, align 4
+ at c = internal global i32 0, align 4
+
+; CHECK-LABEL: @fn1
+; CHECK-NEXT: ret i32 0
+define i32 @fn1(i32 %a) {
+ ret i32 0
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr20678.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr20678.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr20678.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr20678.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,8 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define i1 @test1() {
+entry:
+ ret i1 icmp ne (i16 bitcast (<16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false> to i16), i16 0)
+}
+; CHECK-LABEL: define i1 @test1(
+; CHECK: ret i1 true
Added: llvm/trunk/test/Transforms/InstCombine/pr21199.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr21199.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr21199.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr21199.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,25 @@
+; do not replace a 'select' with 'or' in 'select - cmp - br' sequence
+; RUN: opt -instcombine -S < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare void @f(i32)
+
+define void @test(i32 %len) {
+entry:
+ %cmp = icmp ult i32 %len, 8
+ %cond = select i1 %cmp, i32 %len, i32 8
+ %cmp11 = icmp ult i32 0, %cond
+ br i1 %cmp11, label %for.body, label %for.end
+
+for.body: ; preds = %entry, %for.body
+ %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+ tail call void @f(i32 %cond)
+ %inc = add i32 %i.02, 1
+ %cmp1 = icmp ult i32 %inc, %cond
+ br i1 %cmp1, label %for.body, label %for.end
+
+for.end: ; preds = %for.body, %entry
+ ret void
+; CHECK: select
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr21210.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr21210.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr21210.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr21210.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,51 @@
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -instcombine -S | FileCheck %s
+; Checks that the select-icmp optimization is safe in two cases
+declare void @foo(i32)
+declare i32 @bar(i32)
+
+; don't replace 'cond' by 'len' in the home block ('bb') that
+; contains the select
+define void @test1(i32 %len) {
+entry:
+ br label %bb
+
+bb:
+ %cmp = icmp ult i32 %len, 8
+ %cond = select i1 %cmp, i32 %len, i32 8
+ call void @foo(i32 %cond)
+ %cmp11 = icmp eq i32 %cond, 8
+ br i1 %cmp11, label %for.end, label %bb
+
+for.end:
+ ret void
+; CHECK: select
+; CHECK: icmp eq i32 %cond, 8
+}
+
+; don't replace 'cond' by 'len' in a block ('b1') that dominates all uses
+; of the select outside the home block ('bb'), but can be reached from the home
+; block on another path ('bb -> b0 -> b1')
+define void @test2(i32 %len) {
+entry:
+ %0 = call i32 @bar(i32 %len);
+ %cmp = icmp ult i32 %len, 4
+ br i1 %cmp, label %bb, label %b1
+bb:
+ %cmp2 = icmp ult i32 %0, 2
+ %cond = select i1 %cmp2, i32 %len, i32 8
+ %cmp3 = icmp eq i32 %cond, 8
+ br i1 %cmp3, label %b0, label %b1
+
+b0:
+ call void @foo(i32 %len)
+ br label %b1
+
+b1:
+; CHECK: phi i32 [ %cond, %bb ], [ undef, %b0 ], [ %0, %entry ]
+ %1 = phi i32 [ %cond, %bb ], [ undef, %b0 ], [ %0, %entry ]
+ br label %ret
+
+ret:
+ call void @foo(i32 %1)
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr21651.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr21651.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr21651.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr21651.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Provide legal integer types.
+target datalayout = "n8:16:32:64"
+
+define void @PR21651() {
+; CHECK-LABEL: @PR21651(
+; CHECK-NEXT: switch i1 false, label %out [
+; CHECK-NEXT: i1 false, label %out
+; CHECK-NEXT: i1 true, label %out
+; CHECK-NEXT: ]
+; CHECK: out:
+; CHECK-NEXT: ret void
+;
+ switch i2 0, label %out [
+ i2 0, label %out
+ i2 1, label %out
+ ]
+
+out:
+ ret void
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/pr21891.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr21891.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr21891.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr21891.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,18 @@
+; RUN: opt %s -instcombine
+
+define i32 @f(i32 %theNumber) {
+entry:
+ %cmp = icmp sgt i32 %theNumber, -1
+ call void @llvm.assume(i1 %cmp)
+ br i1 true, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ %shl = shl nuw i32 %theNumber, 1
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ %phi = phi i32 [ %shl, %if.then ], [ undef, %entry ]
+ ret i32 %phi
+}
+
+declare void @llvm.assume(i1)
Added: llvm/trunk/test/Transforms/InstCombine/pr23751.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr23751.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr23751.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr23751.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,13 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+ at d = common global i32 0, align 4
+
+define i1 @f(i8 zeroext %p) #1 {
+; CHECK-NOT: ret i1 false
+ %1 = zext i8 %p to i32
+ %2 = load i32, i32* @d, align 4
+ %3 = or i32 %2, -2
+ %4 = add nsw i32 %3, %1
+ %5 = icmp ugt i32 %1, %4
+ ret i1 %5
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr23809.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr23809.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr23809.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr23809.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,22 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; InstCombine should preserve the call to @llvm.assume.
+define i32 @icmp(i32 %a, i32 %b) {
+; CHECK-LABEL: @icmp(
+ %sum = add i32 %a, %b
+ %1 = icmp sge i32 %sum, 0
+ call void @llvm.assume(i1 %1)
+; CHECK: call void @llvm.assume
+ ret i32 %sum
+}
+
+define float @fcmp(float %a, float %b) {
+; CHECK-LABEL: @fcmp(
+ %sum = fadd float %a, %b
+ %1 = fcmp oge float %sum, 0.0
+ call void @llvm.assume(i1 %1)
+; CHECK: call void @llvm.assume
+ ret float %sum
+}
+
+declare void @llvm.assume(i1)
Added: llvm/trunk/test/Transforms/InstCombine/pr24354.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr24354.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr24354.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr24354.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,33 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+; This used to crash opt
+
+ at c = common global i32 0, align 4
+ at b = common global i32 0, align 4
+ at a = common global i16 0, align 2
+ at d = common global i32 0, align 4
+
+define void @fn3() {
+; CHECK: @fn3
+bb:
+ %tmp = load i32, i32* @c, align 4
+ %tmp1 = icmp eq i32 %tmp, 0
+ br i1 %tmp1, label %bb2, label %bb6
+
+bb2: ; preds = %bb
+ %tmp3 = load i32, i32* @b, align 4
+ %tmp.i = add nsw i32 255, %tmp3
+ %tmp5 = icmp ugt i32 %tmp.i, 254
+ br label %bb6
+
+bb6: ; preds = %bb, %bb2
+ %tmp7 = phi i1 [ true, %bb ], [ %tmp5, %bb2 ]
+ %tmp8 = zext i1 %tmp7 to i32
+ %tmp10 = icmp eq i32 %tmp8, 0
+ %tmp12 = load i16, i16* @a, align 2
+ %tmp14 = icmp ne i16 %tmp12, 0
+ %tmp16 = select i1 %tmp10, i1 false, i1 %tmp14
+ %tmp17 = zext i1 %tmp16 to i32
+ store i32 %tmp17, i32* @d, align 4
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr24605.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr24605.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr24605.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr24605.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,15 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i1 @f(i8* %a, i8 %b) {
+; CHECK-LABEL: @f(
+entry:
+ %or = or i8 %b, -117
+ %sub = add i8 %or, -1
+ store i8 %sub, i8* %a, align 1
+ %cmp = icmp ugt i8 %or, %sub
+ ret i1 %cmp
+; CHECK: ret i1 true
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr25342.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr25342.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr25342.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr25342.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,93 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+%"struct.std::complex" = type { { float, float } }
+ at dd = external global %"struct.std::complex", align 4
+ at dd2 = external global %"struct.std::complex", align 4
+
+define void @_Z3fooi(i32 signext %n) {
+entry:
+ br label %for.cond
+
+for.cond:
+ %ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %5, %for.body ]
+ %ldd.sroa.6.0 = phi i32 [ 0, %entry ], [ %7, %for.body ]
+ %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+ %cmp = icmp slt i32 %i.0, %n
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body:
+ %0 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd, i64 0, i32 0, i32 0), align 4
+ %1 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd, i64 0, i32 0, i32 1), align 4
+ %2 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd2, i64 0, i32 0, i32 0), align 4
+ %3 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd2, i64 0, i32 0, i32 1), align 4
+ %mul.i = fmul float %0, %2
+ %mul4.i = fmul float %1, %3
+ %sub.i = fsub float %mul.i, %mul4.i
+ %mul5.i = fmul float %1, %2
+ %mul6.i = fmul float %0, %3
+ %add.i4 = fadd float %mul5.i, %mul6.i
+ %4 = bitcast i32 %ldd.sroa.0.0 to float
+ %add.i = fadd float %sub.i, %4
+ %5 = bitcast float %add.i to i32
+ %6 = bitcast i32 %ldd.sroa.6.0 to float
+ %add4.i = fadd float %add.i4, %6
+ %7 = bitcast float %add4.i to i32
+ %inc = add nsw i32 %i.0, 1
+ br label %for.cond
+
+for.end:
+ store i32 %ldd.sroa.0.0, i32* bitcast (%"struct.std::complex"* @dd to i32*), align 4
+ store i32 %ldd.sroa.6.0, i32* bitcast (float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd, i64 0, i32 0, i32 1) to i32*), align 4
+ ret void
+
+; CHECK: phi float
+; CHECK: store float
+; CHECK-NOT: bitcast
+}
+
+
+define void @multi_phi(i32 signext %n) {
+entry:
+ br label %for.cond
+
+for.cond:
+ %ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %9, %odd.bb ]
+ %i.0 = phi i32 [ 0, %entry ], [ %inc, %odd.bb ]
+ %cmp = icmp slt i32 %i.0, %n
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body:
+ %0 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd, i64 0, i32 0, i32 0), align 4
+ %1 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd, i64 0, i32 0, i32 1), align 4
+ %2 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd2, i64 0, i32 0, i32 0), align 4
+ %3 = load float, float* getelementptr inbounds (%"struct.std::complex", %"struct.std::complex"* @dd2, i64 0, i32 0, i32 1), align 4
+ %mul.i = fmul float %0, %2
+ %mul4.i = fmul float %1, %3
+ %sub.i = fsub float %mul.i, %mul4.i
+ %4 = bitcast i32 %ldd.sroa.0.0 to float
+ %add.i = fadd float %sub.i, %4
+ %5 = bitcast float %add.i to i32
+ %inc = add nsw i32 %i.0, 1
+ %bit0 = and i32 %inc, 1
+ %even = icmp slt i32 %bit0, 1
+ br i1 %even, label %even.bb, label %odd.bb
+
+even.bb:
+ %6 = bitcast i32 %5 to float
+ %7 = fadd float %sub.i, %6
+ %8 = bitcast float %7 to i32
+ br label %odd.bb
+
+odd.bb:
+ %9 = phi i32 [ %5, %for.body ], [ %8, %even.bb ]
+ br label %for.cond
+
+for.end:
+ store i32 %ldd.sroa.0.0, i32* bitcast (%"struct.std::complex"* @dd to i32*), align 4
+ ret void
+
+; CHECK-LABEL: @multi_phi(
+; CHECK: phi float
+; CHECK: store float
+; CHECK-NOT: bitcast
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr25745.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr25745.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr25745.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr25745.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,20 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+; Checking for a crash
+
+declare void @use.i1(i1 %val)
+declare void @use.i64(i64 %val)
+
+define i64 @f(i32 %x) {
+; CHECK-LABEL: @f(
+ entry:
+ %x.wide = sext i32 %x to i64
+ %minus.x = sub i32 0, %x
+ %minus.x.wide = sext i32 %minus.x to i64
+ %c = icmp slt i32 %x, 0
+ %val = select i1 %c, i64 %x.wide, i64 %minus.x.wide
+ call void @use.i1(i1 %c)
+ call void @use.i64(i64 %x.wide)
+ ret i64 %val
+; CHECK: ret i64 %val
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr2645-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr2645-0.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr2645-0.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr2645-0.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,33 @@
+; RUN: opt < %s -instcombine -S | grep "insertelement <4 x float> undef"
+
+; Instcombine should be able to prove that none of the
+; insertelement's first operand's elements are needed.
+
+define internal void @""(i8*) {
+; <label>:1
+ bitcast i8* %0 to i32* ; <i32*>:2 [#uses=1]
+ load i32, i32* %2, align 1 ; <i32>:3 [#uses=1]
+ getelementptr i8, i8* %0, i32 4 ; <i8*>:4 [#uses=1]
+ bitcast i8* %4 to i32* ; <i32*>:5 [#uses=1]
+ load i32, i32* %5, align 1 ; <i32>:6 [#uses=1]
+ br label %7
+
+; <label>:7 ; preds = %9, %1
+ %.01 = phi <4 x float> [ undef, %1 ], [ %12, %9 ] ; <<4 x float>> [#uses=1]
+ %.0 = phi i32 [ %3, %1 ], [ %15, %9 ] ; <i32> [#uses=3]
+ icmp slt i32 %.0, %6 ; <i1>:8 [#uses=1]
+ br i1 %8, label %9, label %16
+
+; <label>:9 ; preds = %7
+ sitofp i32 %.0 to float ; <float>:10 [#uses=1]
+ insertelement <4 x float> %.01, float %10, i32 0 ; <<4 x float>>:11 [#uses=1]
+ shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:12 [#uses=2]
+ getelementptr i8, i8* %0, i32 48 ; <i8*>:13 [#uses=1]
+ bitcast i8* %13 to <4 x float>* ; <<4 x float>*>:14 [#uses=1]
+ store <4 x float> %12, <4 x float>* %14, align 16
+ add i32 %.0, 2 ; <i32>:15 [#uses=1]
+ br label %7
+
+; <label>:16 ; preds = %7
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr26992.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr26992.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr26992.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr26992.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,37 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+target triple = "x86_64-pc-windows-msvc"
+
+define i1 @test1(i8* %p) personality i32 (...)* @__CxxFrameHandler3 {
+entry:
+ %a = getelementptr i8, i8* %p, i64 1
+ invoke void @may_throw()
+ to label %invoke.cont unwind label %catch.dispatch
+
+invoke.cont:
+ %b = getelementptr inbounds i8, i8* %a, i64 1
+ invoke void @may_throw()
+ to label %exit unwind label %catch.dispatch
+
+catch.dispatch:
+ %c = phi i8* [ %b, %invoke.cont ], [ %a, %entry ]
+ %tmp1 = catchswitch within none [label %catch] unwind to caller
+
+catch:
+ %tmp2 = catchpad within %tmp1 [i8* null, i32 64, i8* null]
+ catchret from %tmp2 to label %exit
+
+exit:
+ %d = phi i8* [ %a, %invoke.cont ], [ %c, %catch ]
+ %cmp = icmp eq i8* %d, %a
+ ret i1 %cmp
+}
+
+; CHECK-LABEL: define i1 @test1(
+; CHECK: %[[gep_a:.*]] = getelementptr i8, i8* %p, i64 1
+; CHECK: %[[gep_b:.*]] = getelementptr inbounds i8, i8* %p, i64 2
+; CHECK: phi i8* [ %[[gep_b]], {{.*}} ], [ %[[gep_a]], {{.*}} ]
+; CHECK: %tmp1 = catchswitch within none [label %catch] unwind to caller
+
+declare void @may_throw()
+
+declare i32 @__CxxFrameHandler3(...)
Added: llvm/trunk/test/Transforms/InstCombine/pr26993.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr26993.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr26993.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr26993.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,24 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+define double @test1() {
+ %sin = call double @__sinpi(double 1.0)
+ ret double %sin
+}
+
+; CHECK-LABEL: define double @test1(
+; CHECK: %[[sin:.*]] = call double @__sinpi(double 1.000000e+00)
+; CHECK-NEXT: ret double %[[sin]]
+
+define double @test2() {
+ %cos = call double @__cospi(double 1.0)
+ ret double %cos
+}
+
+; CHECK-LABEL: define double @test2(
+; CHECK: %[[cos:.*]] = call double @__cospi(double 1.000000e+00)
+; CHECK-NEXT: ret double %[[cos]]
+
+declare double @__sinpi(double %x) #0
+declare double @__cospi(double %x) #0
+
+attributes #0 = { readnone nounwind }
Added: llvm/trunk/test/Transforms/InstCombine/pr27236.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr27236.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr27236.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr27236.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define float @test1(i32 %scale) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[SCALE:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[SCALE]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
+; CHECK-NEXT: ret float [[TMP3]]
+;
+ %1 = icmp sgt i32 1, %scale
+ %2 = select i1 %1, i32 1, i32 %scale
+ %3 = sitofp i32 %2 to float
+ %4 = icmp sgt i32 %2, 0
+ %sel = select i1 %4, float %3, float 0.000000e+00
+ ret float %sel
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr27332.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr27332.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr27332.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr27332.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,23 @@
+; RUN: opt -instcombine -S -o - < %s | FileCheck %s
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
+
+define <4 x i1> @test1(<4 x float> %V) {
+entry:
+ %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %V)
+ %cmp = fcmp olt <4 x float> %abs, zeroinitializer
+ ret <4 x i1> %cmp
+}
+; CHECK-LABEL: define <4 x i1> @test1(
+; CHECK: ret <4 x i1> zeroinitializer
+
+declare float @fabsf()
+
+define i1 @test2() {
+ %call = call float @fabsf()
+ %cmp = fcmp olt float %call, 0.000000e+00
+ ret i1 %cmp
+}
+; CHECK-LABEL: define i1 @test2(
+; CHECK: %[[call:.*]] = call float @fabsf()
+; CHECK: %[[cmp:.*]] = fcmp olt float %[[call]], 0.000000e+00
+; CHECK: ret i1 %[[cmp]]
Added: llvm/trunk/test/Transforms/InstCombine/pr27343.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr27343.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr27343.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr27343.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -S -instcombine | FileCheck %s
+
+define i32 @__isnan(float %x) alwaysinline nounwind optsize {
+; CHECK-LABEL: @__isnan(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[DOTCAST:%.*]] = bitcast float [[X:%.*]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[DOTCAST]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SHL]], -16777216
+; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT: ret i32 [[CONV]]
+;
+entry:
+ %x.addr = alloca float, align 4
+ store float %x, float* %x.addr, align 4
+ %0 = load float, float* %x.addr, align 4
+ %1 = bitcast float %0 to i32
+ %shl = shl i32 %1, 1
+ %cmp = icmp ugt i32 %shl, -16777216
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+define i1 @icmp_shl7(i32 %x) {
+; CHECK-LABEL: @icmp_shl7(
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 7
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 4608
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shl = shl i32 %x, 7
+ %cmp = icmp slt i32 %shl, 4608
+ ret i1 %cmp
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr27703.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr27703.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr27703.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr27703.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,20 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define void @mem() {
+bb:
+ br label %bb6
+
+bb6:
+ %.0 = phi i8** [ undef, %bb ], [ %t2, %bb6 ]
+ %tmp = load i8*, i8** %.0, align 8
+ %bc = bitcast i8* %tmp to i8**
+ %t1 = load i8*, i8** %bc, align 8
+ %t2 = bitcast i8* %t1 to i8**
+ br label %bb6
+
+bb206:
+ ret void
+; CHECK: phi
+; CHECK: bitcast
+; CHECK: load
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr27996.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr27996.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr27996.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr27996.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,41 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+
+ at i = constant i32 1, align 4
+ at f = constant float 0x3FF19999A0000000, align 4
+ at cmp = common global i32 0, align 4
+ at resf = common global float* null, align 8
+ at resi = common global i32* null, align 8
+
+define i32 @foo() {
+entry:
+ br label %while.cond
+
+while.cond:
+ %res.0 = phi i32* [ null, %entry ], [ @i, %if.then ], [ bitcast (float* @f to i32*), %if.else ]
+ %0 = load i32, i32* @cmp, align 4
+ %shr = ashr i32 %0, 1
+ store i32 %shr, i32* @cmp, align 4
+ %tobool = icmp ne i32 %shr, 0
+ br i1 %tobool, label %while.body, label %while.end
+
+while.body:
+ %and = and i32 %shr, 1
+ %tobool1 = icmp ne i32 %and, 0
+ br i1 %tobool1, label %if.then, label %if.else
+
+if.then:
+ br label %while.cond
+
+if.else:
+ br label %while.cond
+
+while.end:
+ %1 = bitcast i32* %res.0 to float*
+ store float* %1, float** @resf, align 8
+ store i32* %res.0, i32** @resi, align 8
+ ret i32 0
+
+; CHECK-NOT: bitcast i32
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/pr28143.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr28143.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr28143.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr28143.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,12 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define void @test1() {
+entry:
+ call void @tan()
+ ret void
+}
+; CHECK-LABEL: define void @test1(
+; CHECK: call void @tan()
+; CHECK-NEXT: ret void
+
+declare void @tan()
Added: llvm/trunk/test/Transforms/InstCombine/pr28725.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr28725.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr28725.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr28725.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,11 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+%S = type { i16, i32 }
+
+define <2 x i16> @test1() {
+entry:
+ %b = insertelement <2 x i16> <i16 undef, i16 0>, i16 extractvalue (%S select (i1 icmp eq (i16 extractelement (<2 x i16> bitcast (<1 x i32> <i32 1> to <2 x i16>), i32 0), i16 0), %S zeroinitializer, %S { i16 0, i32 1 }), 0), i32 0
+ ret <2 x i16> %b
+}
+
+; CHECK-LABEL: @test1(
+; CHECK: ret <2 x i16> zeroinitializer
Added: llvm/trunk/test/Transforms/InstCombine/pr2996.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr2996.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr2996.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr2996.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,12 @@
+; RUN: opt < %s -instcombine
+; PR2996
+
+define void @func_53(i16 signext %p_56) nounwind {
+entry:
+ %0 = icmp sgt i16 %p_56, -1 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %0, i32 -1, i32 0 ; <i32> [#uses=1]
+ %1 = call i32 (...) @func_4(i32 %iftmp.0.0) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @func_4(...)
Added: llvm/trunk/test/Transforms/InstCombine/pr30929.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr30929.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr30929.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr30929.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,11 @@
+; We need this pipeline because to trigger dominator info verification
+; we have to compute the dominator before libcalls-shrinkwrap and
+; have a pass which requires the dominator tree after.
+; RUN: opt -domtree -libcalls-shrinkwrap -instcombine -verify-dom-info %s
+
+define void @main() {
+ %_tmp31 = call float @acosf(float 2.000000e+00)
+ ret void
+}
+
+declare float @acosf(float)
Added: llvm/trunk/test/Transforms/InstCombine/pr31990_wrong_memcpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr31990_wrong_memcpy.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr31990_wrong_memcpy.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr31990_wrong_memcpy.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,25 @@
+; RUN: opt -S -instcombine %s -o - | FileCheck %s
+
+; Regression test of PR31990. A memcpy of one byte, copying 0xff, was
+; replaced with a single store of an i4 0xf.
+
+ at g = constant i8 -1
+
+define void @foo() {
+entry:
+ %0 = alloca i8
+ %1 = bitcast i8* %0 to i4*
+ call void @bar(i4* %1)
+ %2 = bitcast i4* %1 to i8*
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %2, i8* @g, i32 1, i1 false)
+ call void @gaz(i8* %2)
+ ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
+declare void @bar(i4*)
+declare void @gaz(i8*)
+
+; The mempcy should be simplified to a single store of an i8, not i4
+; CHECK: store i8 -1
+; CHECK-NOT: store i4 -1
Added: llvm/trunk/test/Transforms/InstCombine/pr32686.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr32686.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr32686.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr32686.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine %s | FileCheck %s
+
+ at a = external global i8
+ at b = external global i32
+
+define void @tinkywinky() {
+; CHECK-LABEL: @tinkywinky(
+; CHECK-NEXT: [[PATATINO:%.*]] = load i8, i8* @a, align 1
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i8 [[PATATINO]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[TOBOOL]] to i32
+; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], or (i32 zext (i1 icmp ne (i32* bitcast (i8* @a to i32*), i32* @b) to i32), i32 2)
+; CHECK-NEXT: store i32 [[OR1]], i32* @b, align 4
+; CHECK-NEXT: ret void
+;
+ %patatino = load i8, i8* @a
+ %tobool = icmp ne i8 %patatino, 0
+ %lnot = xor i1 %tobool, true
+ %lnot.ext = zext i1 %lnot to i32
+ %or = or i32 xor (i32 zext (i1 icmp ne (i32* bitcast (i8* @a to i32*), i32* @b) to i32), i32 2), %lnot.ext
+ store i32 %or, i32* @b, align 4
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr33453.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr33453.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr33453.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr33453.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S %s | FileCheck %s
+
+ at g1 = external global i16
+ at g2 = external global i16
+
+define float @patatino() {
+; CHECK-LABEL: @patatino(
+; CHECK-NEXT: ret float fmul (float uitofp (i1 icmp eq (i16* getelementptr inbounds (i16, i16* @g2, i64 1), i16* @g1) to float), float uitofp (i1 icmp eq (i16* getelementptr inbounds (i16, i16* @g2, i64 1), i16* @g1) to float))
+;
+ %call = call float @fabsf(float fmul (float uitofp (i1 icmp eq (i16* getelementptr inbounds (i16, i16* @g2, i64 1), i16* @g1) to float), float uitofp (i1 icmp eq (i16* getelementptr inbounds (i16, i16* @g2, i64 1), i16* @g1) to float)))
+ ret float %call
+}
+
+declare float @fabsf(float)
Added: llvm/trunk/test/Transforms/InstCombine/pr33689_same_bitwidth.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr33689_same_bitwidth.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr33689_same_bitwidth.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr33689_same_bitwidth.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine %s -o - | FileCheck %s
+
+; All the "useless" instructions should be removed and we shouldn't crash.
+
+target datalayout = "p:16:16"
+
+%i64_t = type i64
+
+ at a = external global i16
+ at b = external global i16*
+
+define void @f() {
+; CHECK-LABEL: @f(
+; CHECK-NEXT: bb0:
+; CHECK-NEXT: [[TMP12:%.*]] = alloca [2 x i32], align 8
+; CHECK-NEXT: [[TMP12_SUB:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP12]], i16 0, i16 0
+; CHECK-NEXT: br i1 undef, label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint [2 x i32]* [[TMP12]] to i16
+; CHECK-NEXT: store i16 [[TMP8]], i16* @a, align 2
+; CHECK-NEXT: unreachable
+; CHECK: bb2:
+; CHECK-NEXT: [[TMP9:%.*]] = load i16*, i16** @b, align 2
+; CHECK-NEXT: store i16 0, i16* [[TMP9]], align 2
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP12_SUB]], align 8
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], -1
+; CHECK-NEXT: store i32 [[TMP11]], i32* [[TMP12_SUB]], align 8
+; CHECK-NEXT: ret void
+;
+bb0:
+ %tmp1 = alloca %i64_t
+ %tmp2 = bitcast %i64_t* %tmp1 to i32*
+ %useless3 = bitcast %i64_t* %tmp1 to i16*
+ %useless4 = getelementptr inbounds i16, i16* %useless3, i16 undef
+ %useless5 = bitcast i16* %useless4 to i32*
+ br i1 undef, label %bb1, label %bb2
+
+bb1: ; preds = %bb0
+ %useless6 = insertvalue [1 x i32*] undef, i32* %tmp2, 0
+ %useless7 = insertvalue [1 x i32*] %useless6, i32* null, 0
+ %tmp8 = ptrtoint i32* %tmp2 to i16
+ store i16 %tmp8, i16* @a
+ unreachable
+
+bb2: ; preds = %bb0
+ %tmp9 = load i16*, i16** @b
+ store i16 0, i16* %tmp9
+ %tmp10 = load i32, i32* %tmp2
+ %tmp11 = sub i32 %tmp10, 1
+ store i32 %tmp11, i32* %tmp2
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr34349.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr34349.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr34349.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr34349.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+;RUN: opt -instcombine -S %s | FileCheck %s
+
+define i8 @fast_div_201(i8 %p) {
+; CHECK-LABEL: @fast_div_201(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[V3:%.*]] = zext i8 [[P:%.*]] to i16
+; CHECK-NEXT: [[V4:%.*]] = mul nuw nsw i16 [[V3]], 71
+; CHECK-NEXT: [[V5:%.*]] = lshr i16 [[V4]], 8
+; CHECK-NEXT: [[V6:%.*]] = trunc i16 [[V5]] to i8
+; CHECK-NEXT: [[V7:%.*]] = sub i8 [[P]], [[V6]]
+; CHECK-NEXT: [[V8:%.*]] = lshr i8 [[V7]], 1
+; CHECK-NEXT: [[V13:%.*]] = add nuw i8 [[V8]], [[V6]]
+; CHECK-NEXT: [[V14:%.*]] = lshr i8 [[V13]], 7
+; CHECK-NEXT: ret i8 [[V14]]
+;
+entry:
+ %v3 = zext i8 %p to i16
+ %v4 = mul i16 %v3, 71
+ %v5 = lshr i16 %v4, 8
+ %v6 = trunc i16 %v5 to i8
+ %v7 = sub i8 %p, %v6
+ %v8 = lshr i8 %v7, 1
+ %v13 = add i8 %v6, %v8
+ %v14 = lshr i8 %v13, 7
+ ret i8 %v14
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr34627.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr34627.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr34627.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr34627.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine %s |FileCheck %s
+
+define <2 x i16> @patatino() {
+; CHECK-LABEL: @patatino(
+; CHECK-NEXT: ret <2 x i16> zeroinitializer
+;
+ %tmp2 = getelementptr inbounds [1 x i16], [1 x i16]* null, i16 0, <2 x i16> undef
+ %tmp3 = ptrtoint <2 x i16*> %tmp2 to <2 x i16>
+ ret <2 x i16> %tmp3
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr35515.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr35515.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr35515.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr35515.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,20 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+ at g_40 = external global i8, align 2
+ at g_461 = external global [6 x i8], align 2
+ at g_49 = external local_unnamed_addr global { i8, i8, i8, i8, i8 }, align 2
+
+; CHECK-LABEL: @func_24(
+define fastcc void @func_24() {
+entry:
+ %bf.load81 = load i40, i40* bitcast ({ i8, i8, i8, i8, i8 }* @g_49 to i40*), align 2
+ %bf.clear = and i40 %bf.load81, -274869518337
+ %bf.set = or i40 %bf.clear, shl (i40 zext (i1 icmp sgt (i32 zext (i1 icmp eq (i8* getelementptr inbounds ([6 x i8], [6 x i8]* @g_461, i64 0, i64 2), i8* @g_40) to i32), i32 0) to i40), i40 23)
+ %tmp = lshr i40 %bf.set, 23
+ %tmp1 = trunc i40 %tmp to i32
+ %tmp2 = and i32 1, %tmp1
+ %tmp3 = shl nuw nsw i32 %tmp2, 23
+ %bf.shl154 = zext i32 %tmp3 to i40
+ %bf.set156 = or i40 %bf.clear, %bf.shl154
+ unreachable
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr36362.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr36362.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr36362.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr36362.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+;RUN: opt -instcombine -S %s | FileCheck %s
+
+; We shouldn't remove the select before the srem
+define i32 @foo(i1 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[A:%.*]], i32 [[B:%.*]], i32 -1
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[C:%.*]], [[SEL1]]
+; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[A]], i32 [[REM]], i32 0
+; CHECK-NEXT: ret i32 [[SEL2]]
+;
+ %sel1 = select i1 %a, i32 %b, i32 -1
+ %rem = srem i32 %c, %sel1
+ %sel2 = select i1 %a, i32 %rem, i32 0
+ ret i32 %sel2
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/pr38677.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr38677.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr38677.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr38677.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+;RUN: opt -instcombine -S %s | FileCheck %s
+
+ at A = extern_weak global i32, align 4
+ at B = extern_weak global i32, align 4
+
+define i32 @foo(i1 %which) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 true, label [[FINAL:%.*]], label [[DELAY:%.*]]
+; CHECK: delay:
+; CHECK-NEXT: br label [[FINAL]]
+; CHECK: final:
+; CHECK-NEXT: [[USE2:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ select (i1 icmp eq (i32* @A, i32* @B), i32 2, i32 1), [[DELAY]] ]
+; CHECK-NEXT: [[B7:%.*]] = mul i32 [[USE2]], 2147483647
+; CHECK-NEXT: [[C3:%.*]] = icmp eq i32 [[B7]], 0
+; CHECK-NEXT: store i1 [[C3]], i1* undef, align 1
+; CHECK-NEXT: ret i32 [[USE2]]
+;
+entry:
+ br i1 true, label %final, label %delay
+
+delay: ; preds = %entry
+ br label %final
+
+final: ; preds = %delay, %entry
+ %use2 = phi i1 [ false, %entry ], [ icmp eq (i32* @A, i32* @B), %delay ]
+ %value = select i1 %use2, i32 2, i32 1
+ %B7 = mul i32 %value, 2147483647
+ %C3 = icmp ule i32 %B7, 0
+ store i1 %C3, i1* undef
+ ret i32 %value
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr38897.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr38897.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr38897.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr38897.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+define i32 @sharpening(i32 %b340, i1 %c, i1 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
+; CHECK-LABEL: @sharpening(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SMAX58:%.*]] = select i1 [[C:%.*]], i32 [[E:%.*]], i32 [[F:%.*]]
+; CHECK-NEXT: [[SMAX59:%.*]] = select i1 [[D:%.*]], i32 [[G:%.*]], i32 [[H:%.*]]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[SMAX59]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], -1
+; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 -1
+; CHECK-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[SMAX58]], [[TMP12]]
+; CHECK-NEXT: [[SMAX61:%.*]] = select i1 [[TMP13]], i32 [[SMAX58]], i32 [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = xor i32 [[SMAX61]], -1
+; CHECK-NEXT: ret i32 [[TMP14]]
+;
+entry:
+ %smax58 = select i1 %c, i32 %e, i32 %f
+ %smax59 = select i1 %d, i32 %g, i32 %h
+ %tmp10 = sub i32 -2, %smax59
+ %tmp11 = icmp sgt i32 %tmp10, 0
+ %smax60 = select i1 %tmp11, i32 %tmp10, i32 0
+ %tmp12 = xor i32 %smax60, -1
+ %tmp13 = icmp sgt i32 %smax58, %tmp12
+ %smax61 = select i1 %tmp13, i32 %smax58, i32 %tmp12
+ %tmp14 = xor i32 %smax61, -1
+ ret i32 %tmp14
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr38915.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr38915.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr38915.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr38915.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+define i32 @PR38915(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @PR38915(
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[Y:%.*]], -1
+; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: [[M1N:%.*]] = select i1 [[TMP3]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[M1N]], [[Z:%.*]]
+; CHECK-NEXT: [[M2:%.*]] = select i1 [[C2]], i32 [[M1N]], i32 [[Z]]
+; CHECK-NEXT: [[M2N:%.*]] = xor i32 [[M2]], -1
+; CHECK-NEXT: ret i32 [[M2N]]
+;
+ %xn = sub i32 0, %x
+ %yn = sub i32 0, %y
+ %c1 = icmp sgt i32 %xn, %yn
+ %m1 = select i1 %c1, i32 %xn, i32 %yn
+ %m1n = xor i32 %m1, -1
+ %c2 = icmp sgt i32 %m1n, %z
+ %m2 = select i1 %c2, i32 %m1n, i32 %z
+ %m2n = xor i32 %m2, -1
+ ret i32 %m2n
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr38984.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr38984.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr38984.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr38984.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "p:16:16"
+
+ at a = external global [21 x i16], align 1
+ at offsets = external global [4 x i16], align 1
+
+; The "same gep" optimization should work with vector icmp.
+define <4 x i1> @PR38984_1() {
+; CHECK-LABEL: @PR38984_1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+ %0 = load i16, i16* getelementptr ([4 x i16], [4 x i16]* @offsets, i16 0, i16 undef), align 1
+ %1 = insertelement <4 x i16> undef, i16 %0, i32 3
+ %2 = getelementptr i32, i32* null, <4 x i16> %1
+ %3 = getelementptr i32, i32* null, <4 x i16> %1
+ %4 = icmp eq <4 x i32*> %2, %3
+ ret <4 x i1> %4
+}
+
+; The "compare base pointers" optimization should not kick in for vector icmp.
+define <4 x i1> @PR38984_2() {
+; CHECK-LABEL: @PR38984_2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* getelementptr ([4 x i16], [4 x i16]* @offsets, i16 0, i16 undef), align 2
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> undef, i16 [[TMP0]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, i16* getelementptr inbounds ([21 x i16], [21 x i16]* @a, i16 1, i16 0), <4 x i16> [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, i16* null, <4 x i16> [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i16*> [[TMP2]], [[TMP3]]
+; CHECK-NEXT: ret <4 x i1> [[TMP4]]
+;
+entry:
+ %0 = load i16, i16* getelementptr ([4 x i16], [4 x i16]* @offsets, i16 0, i16 undef)
+ %1 = insertelement <4 x i16> undef, i16 %0, i32 3
+ %2 = getelementptr i16, i16* getelementptr ([21 x i16], [21 x i16]* @a, i64 1, i32 0), <4 x i16> %1
+ %3 = getelementptr i16, i16* null, <4 x i16> %1
+ %4 = icmp eq <4 x i16*> %2, %3
+ ret <4 x i1> %4
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr39177.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr39177.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr39177.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr39177.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+%struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
+%struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 }
+
+ at stderr = external global %struct._IO_FILE*, align 8
+ at .str = private constant [8 x i8] c"crash!\0A\00", align 1
+
+ at fwrite = alias i64 (i8*, i64, i64, %struct._IO_FILE*), i64 (i8*, i64, i64, %struct._IO_FILE*)* @__fwrite_alias
+
+define i64 @__fwrite_alias(i8* %ptr, i64 %size, i64 %n, %struct._IO_FILE* %s) {
+; CHECK-LABEL: @__fwrite_alias(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret i64 0
+;
+entry:
+ %ptr.addr = alloca i8*, align 8
+ %size.addr = alloca i64, align 8
+ %n.addr = alloca i64, align 8
+ %s.addr = alloca %struct._IO_FILE*, align 8
+ store i8* %ptr, i8** %ptr.addr, align 8
+ store i64 %size, i64* %size.addr, align 8
+ store i64 %n, i64* %n.addr, align 8
+ store %struct._IO_FILE* %s, %struct._IO_FILE** %s.addr, align 8
+ ret i64 0
+}
+
+define void @foo() {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load %struct._IO_FILE*, %struct._IO_FILE** @stderr, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @__fwrite_alias(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i64 7, i64 1, %struct._IO_FILE* [[TMP0]])
+; CHECK-NEXT: ret void
+;
+entry:
+ %retval = alloca i32, align 4
+ store i32 0, i32* %retval, align 4
+ %0 = load %struct._IO_FILE*, %struct._IO_FILE** @stderr, align 8
+ %call = call i32 (%struct._IO_FILE*, i8*, ...) @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0))
+ ret void
+}
+
+declare i32 @fprintf(%struct._IO_FILE*, i8*, ...)
Added: llvm/trunk/test/Transforms/InstCombine/pr39908.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr39908.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr39908.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr39908.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "p:32:32"
+
+%S = type { [2 x i32] }
+
+define i1 @test([0 x %S]* %p, i32 %n) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[N:%.*]], 1
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %start.cast = bitcast [0 x %S]* %p to %S*
+ %end = getelementptr inbounds [0 x %S], [0 x %S]* %p, i32 0, i32 %n, i32 0, i32 0
+ %end.cast = bitcast i32* %end to %S*
+ %last = getelementptr inbounds %S, %S* %end.cast, i32 -1
+ %cmp = icmp eq %S* %last, %start.cast
+ ret i1 %cmp
+}
+
+; Same test using 64-bit indices.
+define i1 @test64([0 x %S]* %p, i64 %n) {
+; CHECK-LABEL: @test64(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[N:%.*]] to i32
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 1
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %start.cast = bitcast [0 x %S]* %p to %S*
+ %end = getelementptr inbounds [0 x %S], [0 x %S]* %p, i64 0, i64 %n, i32 0, i64 0
+ %end.cast = bitcast i32* %end to %S*
+ %last = getelementptr inbounds %S, %S* %end.cast, i64 -1
+ %cmp = icmp eq %S* %last, %start.cast
+ ret i1 %cmp
+}
+
+; Here the offset overflows and is treated modulo 2^32. This is UB.
+define i1 @test64_overflow([0 x %S]* %p, i64 %n) {
+; CHECK-LABEL: @test64_overflow(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[N:%.*]] to i32
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 1
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %start.cast = bitcast [0 x %S]* %p to %S*
+ %end = getelementptr inbounds [0 x %S], [0 x %S]* %p, i64 0, i64 %n, i32 0, i64 8589934592
+ %end.cast = bitcast i32* %end to %S*
+ %last = getelementptr inbounds %S, %S* %end.cast, i64 -1
+ %cmp = icmp eq %S* %last, %start.cast
+ ret i1 %cmp
+}
Added: llvm/trunk/test/Transforms/InstCombine/pr41164.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr41164.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/pr41164.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/pr41164.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+ at wyhash64_x = global i64 0, align 8
+
+define i64 @_Z8wyhash64v() {
+; CHECK-LABEL: @_Z8wyhash64v(
+; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* @wyhash64_x, align 8
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 6971258582664805397
+; CHECK-NEXT: store i64 [[TMP2]], i64* @wyhash64_x, align 8
+; CHECK-NEXT: [[TMP3:%.*]] = zext i64 [[TMP2]] to i128
+; CHECK-NEXT: [[TMP4:%.*]] = mul nuw i128 [[TMP3]], 11795372955171141389
+; CHECK-NEXT: [[TMP5:%.*]] = lshr i128 [[TMP4]], 64
+; CHECK-NEXT: [[DOTMASKED:%.*]] = and i128 [[TMP4]], 18446744073709551615
+; CHECK-NEXT: [[TMP6:%.*]] = xor i128 [[TMP5]], [[DOTMASKED]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul nuw nsw i128 [[TMP6]], 1946526487930394057
+; CHECK-NEXT: [[TMP8:%.*]] = lshr i128 [[TMP7]], 64
+; CHECK-NEXT: [[TMP9:%.*]] = xor i128 [[TMP8]], [[TMP7]]
+; CHECK-NEXT: [[TMP10:%.*]] = trunc i128 [[TMP9]] to i64
+; CHECK-NEXT: ret i64 [[TMP10]]
+;
+ %1 = load i64, i64* @wyhash64_x, align 8
+ %2 = add i64 %1, 6971258582664805397
+ store i64 %2, i64* @wyhash64_x, align 8
+ %3 = zext i64 %2 to i128
+ %4 = mul i128 %3, 11795372955171141389
+ %5 = lshr i128 %4, 64
+ %6 = xor i128 %5, %4
+ %7 = trunc i128 %6 to i64
+ %8 = zext i64 %7 to i128
+ %9 = mul i128 %8, 1946526487930394057
+ %10 = lshr i128 %9, 64
+ %11 = xor i128 %10, %9
+ %12 = trunc i128 %11 to i64
+ ret i64 %12
+}
Added: llvm/trunk/test/Transforms/InstCombine/prefetch-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/prefetch-load.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/prefetch-load.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/prefetch-load.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,34 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+%struct.C = type { %struct.C*, i32 }
+
+; Check that we instcombine the load across the prefetch.
+
+; CHECK-LABEL: define signext i32 @foo
+define signext i32 @foo(%struct.C* %c) local_unnamed_addr #0 {
+; CHECK: store i32 %dec, i32* %length_
+; CHECK-NOT: load
+; CHECK: llvm.prefetch
+; CHECK-NEXT: ret
+entry:
+ %next_ = getelementptr inbounds %struct.C, %struct.C* %c, i32 0, i32 0
+ %0 = load %struct.C*, %struct.C** %next_, align 8
+ %next_1 = getelementptr inbounds %struct.C, %struct.C* %0, i32 0, i32 0
+ %1 = load %struct.C*, %struct.C** %next_1, align 8
+ store %struct.C* %1, %struct.C** %next_, align 8
+ %length_ = getelementptr inbounds %struct.C, %struct.C* %c, i32 0, i32 1
+ %2 = load i32, i32* %length_, align 8
+ %dec = add nsw i32 %2, -1
+ store i32 %dec, i32* %length_, align 8
+ %3 = bitcast %struct.C* %1 to i8*
+ call void @llvm.prefetch(i8* %3, i32 0, i32 0, i32 1)
+ %4 = load i32, i32* %length_, align 8
+ ret i32 %4
+}
+
+; Function Attrs: inaccessiblemem_or_argmemonly nounwind
+declare void @llvm.prefetch(i8* nocapture readonly, i32, i32, i32)
+
+attributes #0 = { noinline nounwind }
+; We've explicitly removed the function attrs from llvm.prefetch so we get the defaults.
+; attributes #1 = { inaccessiblemem_or_argmemonly nounwind }
Added: llvm/trunk/test/Transforms/InstCombine/preserve-sminmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/preserve-sminmax.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/preserve-sminmax.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/preserve-sminmax.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,32 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Instcombine normally would fold the sdiv into the comparison,
+; making "icmp slt i32 %h, 2", but in this case the sdiv has
+; another use, so it wouldn't a big win, and it would also
+; obfuscate an otherise obvious smax pattern to the point where
+; other analyses wouldn't recognize it.
+
+define i32 @foo(i32 %h) {
+ %sd = sdiv i32 %h, 2
+ %t = icmp slt i32 %sd, 1
+ %r = select i1 %t, i32 %sd, i32 1
+ ret i32 %r
+}
+
+; CHECK: %sd = sdiv i32 %h, 2
+; CHECK: %t = icmp slt i32 %sd, 1
+; CHECK: %r = select i1 %t, i32 %sd, i32 1
+; CHECK: ret i32 %r
+
+define i32 @bar(i32 %h) {
+ %sd = sdiv i32 %h, 2
+ %t = icmp sgt i32 %sd, 1
+ %r = select i1 %t, i32 %sd, i32 1
+ ret i32 %r
+}
+
+; CHECK: %sd = sdiv i32 %h, 2
+; CHECK: %t = icmp sgt i32 %sd, 1
+; CHECK: %r = select i1 %t, i32 %sd, i32 1
+; CHECK: ret i32 %r
+
Added: llvm/trunk/test/Transforms/InstCombine/preserved-analyses.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/preserved-analyses.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/preserved-analyses.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/preserved-analyses.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,33 @@
+; This is really testing that instcombine preserves analyses correctly, so we
+; don't care much about the code other than it is something instcombine can
+; transform.
+;
+; RUN: opt < %s -disable-output -debug-pass-manager 2>&1 -aa-pipeline=basic-aa,globals-aa \
+; RUN: -passes='require<globals-aa>,function(require<aa>,instcombine),function(require<aa>)' \
+; RUN: | FileCheck %s --check-prefix=AA
+; AA: Running analysis: GlobalsAA
+; AA: Running analysis: AAManager
+; AA: Running analysis: BasicAA
+; AA: Running pass: InstCombinePass on test
+; AA-NOT: Invalidating analysis: GlobalsAA
+; AA-NOT: Invalidating analysis: AAmanager
+; AA-NOT: Invalidating analysis: BasicAA
+; AA: Running pass: RequireAnalysisPass<{{.*}}AAManager
+; AA-NOT: Running analysis: GlobalsAA
+; AA-NOT: Running analysis: AAmanager
+; AA-NOT: Running analysis: BasicAA
+;
+; RUN: opt < %s -disable-output -debug-pass-manager 2>&1 \
+; RUN: -passes='require<domtree>,instcombine,require<domtree>' \
+; RUN: | FileCheck %s --check-prefix=DT
+; DT: Running analysis: DominatorTreeAnalysis
+; DT: Running pass: InstCombinePass on test
+; DT-NOT: Invalidating analysis: DominatorTreeAnalysis
+; DT: Running pass: RequireAnalysisPass<{{.*}}DominatorTreeAnalysis
+; DT-NOT: Running analysis: DominatorTreeAnalysis
+
+define i32 @test(i32 %A) {
+ %B = add i32 %A, 5
+ %C = add i32 %B, -5
+ ret i32 %C
+}
Added: llvm/trunk/test/Transforms/InstCombine/prevent-cmp-merge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/prevent-cmp-merge.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/prevent-cmp-merge.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/prevent-cmp-merge.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,41 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+;
+; This test makes sure that InstCombine does not replace the sequence of
+; xor/sub instruction followed by cmp instruction into a single cmp instruction
+; if there is more than one use of xor/sub.
+
+define zeroext i1 @test1(i32 %lhs, i32 %rhs) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: %xor = xor i32 %lhs, 5
+; CHECK-NEXT: %cmp1 = icmp eq i32 %xor, 10
+
+ %xor = xor i32 %lhs, 5
+ %cmp1 = icmp eq i32 %xor, 10
+ %cmp2 = icmp eq i32 %xor, %rhs
+ %sel = or i1 %cmp1, %cmp2
+ ret i1 %sel
+}
+
+define zeroext i1 @test2(i32 %lhs, i32 %rhs) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: %xor = xor i32 %lhs, %rhs
+; CHECK-NEXT: %cmp1 = icmp eq i32 %xor, 0
+
+ %xor = xor i32 %lhs, %rhs
+ %cmp1 = icmp eq i32 %xor, 0
+ %cmp2 = icmp eq i32 %xor, 32
+ %sel = xor i1 %cmp1, %cmp2
+ ret i1 %sel
+}
+
+define zeroext i1 @test3(i32 %lhs, i32 %rhs) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: %sub = sub nsw i32 %lhs, %rhs
+; CHECK-NEXT: %cmp1 = icmp eq i32 %sub, 0
+
+ %sub = sub nsw i32 %lhs, %rhs
+ %cmp1 = icmp eq i32 %sub, 0
+ %cmp2 = icmp eq i32 %sub, 31
+ %sel = or i1 %cmp1, %cmp2
+ ret i1 %sel
+}
Added: llvm/trunk/test/Transforms/InstCombine/printf-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/printf-1.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/printf-1.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/printf-1.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,131 @@
+; Test that the printf library call simplifier works correctly.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+; RUN: opt < %s -mtriple xcore-xmos-elf -instcombine -S | FileCheck %s -check-prefix=CHECK-IPRINTF
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+ at hello_world = constant [13 x i8] c"hello world\0A\00"
+ at h = constant [2 x i8] c"h\00"
+ at h2 = constant [3 x i8] c"%%\00"
+ at percent = constant [2 x i8] c"%\00"
+ at percent_c = constant [3 x i8] c"%c\00"
+ at percent_d = constant [3 x i8] c"%d\00"
+ at percent_f = constant [3 x i8] c"%f\00"
+ at percent_s = constant [4 x i8] c"%s\0A\00"
+ at empty = constant [1 x i8] c"\00"
+; CHECK: [[$STR:@[a-z0-9]+]] = private unnamed_addr constant [12 x i8] c"hello world\00", align 1
+
+declare i32 @printf(i8*, ...)
+
+; Check printf("") -> noop.
+
+define void @test_simplify1() {
+; CHECK-LABEL: @test_simplify1(
+ %fmt = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+; Check printf("x") -> putchar('x'), even for '%'.
+
+define void @test_simplify2() {
+; CHECK-LABEL: @test_simplify2(
+ %fmt = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @putchar(i32 104)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+; Special case: printf("%%") -> putchar('%').
+
+define void @test_simplify2b() {
+; CHECK-LABEL: @test_simplify2b(
+ %fmt = getelementptr [3 x i8], [3 x i8]* @h2, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @putchar(i32 37)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+define void @test_simplify3() {
+; CHECK-LABEL: @test_simplify3(
+ %fmt = getelementptr [2 x i8], [2 x i8]* @percent, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @putchar(i32 37)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+; Check printf("foo\n") -> puts("foo").
+
+define void @test_simplify4() {
+; CHECK-LABEL: @test_simplify4(
+ %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* [[$STR]], i32 0, i32 0))
+ ret void
+; CHECK-NEXT: ret void
+}
+
+; Check printf("%c", chr) -> putchar(chr).
+
+define void @test_simplify5() {
+; CHECK-LABEL: @test_simplify5(
+ %fmt = getelementptr [3 x i8], [3 x i8]* @percent_c, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt, i8 104)
+; CHECK-NEXT: call i32 @putchar(i32 104)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+; Check printf("%s\n", str) -> puts(str).
+
+define void @test_simplify6() {
+; CHECK-LABEL: @test_simplify6(
+ %fmt = getelementptr [4 x i8], [4 x i8]* @percent_s, i32 0, i32 0
+ %str = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt, i8* %str)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0))
+ ret void
+; CHECK-NEXT: ret void
+}
+
+; Check printf(format, ...) -> iprintf(format, ...) if no floating point.
+
+define void @test_simplify7() {
+; CHECK-IPRINTF-LABEL: @test_simplify7(
+ %fmt = getelementptr [3 x i8], [3 x i8]* @percent_d, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt, i32 187)
+; CHECK-IPRINTF-NEXT: call i32 (i8*, ...) @iprintf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_d, i32 0, i32 0), i32 187)
+ ret void
+; CHECK-IPRINTF-NEXT: ret void
+}
+
+define void @test_no_simplify1() {
+; CHECK-IPRINTF-LABEL: @test_no_simplify1(
+ %fmt = getelementptr [3 x i8], [3 x i8]* @percent_f, i32 0, i32 0
+ call i32 (i8*, ...) @printf(i8* %fmt, double 1.87)
+; CHECK-IPRINTF-NEXT: call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
+ ret void
+; CHECK-IPRINTF-NEXT: ret void
+}
+
+define void @test_no_simplify2(i8* %fmt, double %d) {
+; CHECK-LABEL: @test_no_simplify2(
+ call i32 (i8*, ...) @printf(i8* %fmt, double %d)
+; CHECK-NEXT: call i32 (i8*, ...) @printf(i8* %fmt, double %d)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+define i32 @test_no_simplify3() {
+; CHECK-LABEL: @test_no_simplify3(
+ %fmt = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+ %ret = call i32 (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @h, i32 0, i32 0))
+ ret i32 %ret
+; CHECK-NEXT: ret i32 %ret
+}
Added: llvm/trunk/test/Transforms/InstCombine/printf-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/printf-2.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/printf-2.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/printf-2.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,53 @@
+; Test that the printf library call simplifier works correctly.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+ at hello_world = constant [13 x i8] c"hello world\0A\00"
+ at h = constant [2 x i8] c"h\00"
+ at percent_s = constant [4 x i8] c"%s\0A\00"
+ at format_str = constant [3 x i8] c"%s\00"
+ at charstr = constant [2 x i8] c"a\00"
+
+declare void @printf(i8*, ...)
+
+; Check simplification of printf with void return type.
+
+define void @test_simplify1() {
+; CHECK-LABEL: @test_simplify1(
+ %fmt = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+ call void (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @putchar(i32 104)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+define void @test_simplify2() {
+; CHECK-LABEL: @test_simplify2(
+ %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+ call void (i8*, ...) @printf(i8* %fmt)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0))
+ ret void
+; CHECK-NEXT: ret void
+}
+
+define void @test_simplify6() {
+; CHECK-LABEL: @test_simplify6(
+ %fmt = getelementptr [4 x i8], [4 x i8]* @percent_s, i32 0, i32 0
+ %str = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
+ call void (i8*, ...) @printf(i8* %fmt, i8* %str)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @hello_world, i32 0, i32 0))
+ ret void
+; CHECK-NEXT: ret void
+}
+
+define void @test_simplify7() {
+; CHECK-LABEL: @test_simplify7(
+ %fmt = getelementptr [3 x i8], [3 x i8]* @format_str, i32 0, i32 0
+ %str = getelementptr [2 x i8], [2 x i8]* @charstr, i32 0, i32 0
+ call void (i8*, ...) @printf(i8* %fmt, i8* %str)
+; CHECK-NEXT: call i32 @putchar(i32 97)
+ ret void
+; CHECK-NEXT: ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/printf-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/printf-3.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/printf-3.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/printf-3.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,39 @@
+; Test that the printf library call simplifier works correctly.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc18.0.0"
+
+ at .str = private unnamed_addr constant [2 x i8] c"\0A\00", align 1
+
+define void @test1() personality i32 (...)* @__CxxFrameHandler3 {
+entry:
+ invoke void @_CxxThrowException(i8* null, i8* null)
+ to label %unreachable unwind label %catch.dispatch
+
+catch.dispatch:
+ %cs = catchswitch within none [label %catch] unwind to caller
+
+catch:
+ %cp = catchpad within %cs [i8* null, i32 64, i8* null]
+ %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0)) [ "funclet"(token %cp) ]
+ catchret from %cp to label %try.cont
+
+try.cont:
+ ret void
+
+unreachable:
+ unreachable
+}
+
+; CHECK-DAG: define void @test1(
+; CHECK: %[[CS:.*]] = catchswitch within none
+; CHECK: %[[CP:.*]] = catchpad within %[[CS]] [i8* null, i32 64, i8* null]
+; CHECK: call i32 @putchar(i32 10) [ "funclet"(token %[[CP]]) ]
+
+declare void @_CxxThrowException(i8*, i8*)
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare i32 @printf(i8*, ...)
Added: llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,60 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
+
+define i1 @test1(i32 *%x) nounwind {
+entry:
+; CHECK: test1
+; CHECK: ptrtoint i32* %x to i64
+ %0 = ptrtoint i32* %x to i1
+ ret i1 %0
+}
+
+define i32* @test2(i128 %x) nounwind {
+entry:
+; CHECK: test2
+; CHECK: inttoptr i64 %0 to i32*
+ %0 = inttoptr i128 %x to i32*
+ ret i32* %0
+}
+
+; PR3574
+; CHECK: f0
+; CHECK: %1 = zext i32 %a0 to i64
+; CHECK: ret i64 %1
+define i64 @f0(i32 %a0) nounwind {
+ %t0 = inttoptr i32 %a0 to i8*
+ %t1 = ptrtoint i8* %t0 to i64
+ ret i64 %t1
+}
+
+define <4 x i32> @test4(<4 x i8*> %arg) nounwind {
+; CHECK-LABEL: @test4(
+; CHECK: ptrtoint <4 x i8*> %arg to <4 x i64>
+; CHECK: trunc <4 x i64> %1 to <4 x i32>
+ %p1 = ptrtoint <4 x i8*> %arg to <4 x i32>
+ ret <4 x i32> %p1
+}
+
+define <4 x i128> @test5(<4 x i8*> %arg) nounwind {
+; CHECK-LABEL: @test5(
+; CHECK: ptrtoint <4 x i8*> %arg to <4 x i64>
+; CHECK: zext <4 x i64> %1 to <4 x i128>
+ %p1 = ptrtoint <4 x i8*> %arg to <4 x i128>
+ ret <4 x i128> %p1
+}
+
+define <4 x i8*> @test6(<4 x i32> %arg) nounwind {
+; CHECK-LABEL: @test6(
+; CHECK: zext <4 x i32> %arg to <4 x i64>
+; CHECK: inttoptr <4 x i64> %1 to <4 x i8*>
+ %p1 = inttoptr <4 x i32> %arg to <4 x i8*>
+ ret <4 x i8*> %p1
+}
+
+define <4 x i8*> @test7(<4 x i128> %arg) nounwind {
+; CHECK-LABEL: @test7(
+; CHECK: trunc <4 x i128> %arg to <4 x i64>
+; CHECK: inttoptr <4 x i64> %1 to <4 x i8*>
+ %p1 = inttoptr <4 x i128> %arg to <4 x i8*>
+ ret <4 x i8*> %p1
+}
Added: llvm/trunk/test/Transforms/InstCombine/puts-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/puts-1.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/puts-1.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/puts-1.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,31 @@
+; Test that the puts library call simplifier works correctly.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+ at empty = constant [1 x i8] zeroinitializer
+
+declare i32 @puts(i8*)
+
+; Check puts("") -> putchar('\n').
+
+define void @test_simplify1() {
+; CHECK-LABEL: @test_simplify1(
+ %str = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
+ call i32 @puts(i8* %str)
+; CHECK-NEXT: call i32 @putchar(i32 10)
+ ret void
+; CHECK-NEXT: ret void
+}
+
+; Don't simplify if the return value is used.
+
+define i32 @test_no_simplify1() {
+; CHECK-LABEL: @test_no_simplify1(
+ %str = getelementptr [1 x i8], [1 x i8]* @empty, i32 0, i32 0
+ %ret = call i32 @puts(i8* %str)
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @empty, i32 0, i32 0))
+ ret i32 %ret
+; CHECK-NEXT: ret i32 %ret
+}
Added: llvm/trunk/test/Transforms/InstCombine/range-check.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/range-check.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/range-check.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/range-check.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,159 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Check simplification of
+; (icmp sgt x, -1) & (icmp sgt/sge n, x) --> icmp ugt/uge n, x
+
+; CHECK-LABEL: define i1 @test_and1
+; CHECK: [[R:%[0-9]+]] = icmp ugt i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_and1(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp sge i32 %x, 0
+ %b = icmp slt i32 %x, %nn
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @test_and2
+; CHECK: [[R:%[0-9]+]] = icmp uge i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_and2(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp sgt i32 %x, -1
+ %b = icmp sle i32 %x, %nn
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @test_and3
+; CHECK: [[R:%[0-9]+]] = icmp ugt i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_and3(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp sgt i32 %nn, %x
+ %b = icmp sge i32 %x, 0
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @test_and4
+; CHECK: [[R:%[0-9]+]] = icmp uge i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_and4(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp sge i32 %nn, %x
+ %b = icmp sge i32 %x, 0
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @test_or1
+; CHECK: [[R:%[0-9]+]] = icmp ule i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_or1(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp slt i32 %x, 0
+ %b = icmp sge i32 %x, %nn
+ %c = or i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @test_or2
+; CHECK: [[R:%[0-9]+]] = icmp ult i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_or2(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp sle i32 %x, -1
+ %b = icmp sgt i32 %x, %nn
+ %c = or i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @test_or3
+; CHECK: [[R:%[0-9]+]] = icmp ule i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_or3(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp sle i32 %nn, %x
+ %b = icmp slt i32 %x, 0
+ %c = or i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @test_or4
+; CHECK: [[R:%[0-9]+]] = icmp ult i32 %nn, %x
+; CHECK: ret i1 [[R]]
+define i1 @test_or4(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp slt i32 %nn, %x
+ %b = icmp slt i32 %x, 0
+ %c = or i1 %a, %b
+ ret i1 %c
+}
+
+; Negative tests
+
+; CHECK-LABEL: define i1 @negative1
+; CHECK: %a = icmp
+; CHECK: %b = icmp
+; CHECK: %c = and i1 %a, %b
+; CHECK: ret i1 %c
+define i1 @negative1(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp slt i32 %x, %nn
+ %b = icmp sgt i32 %x, 0 ; should be: icmp sge
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @negative2
+; CHECK: %a = icmp
+; CHECK: %b = icmp
+; CHECK: %c = and i1 %a, %b
+; CHECK: ret i1 %c
+define i1 @negative2(i32 %x, i32 %n) {
+ %a = icmp slt i32 %x, %n ; n can be negative
+ %b = icmp sge i32 %x, 0
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @negative3
+; CHECK: %a = icmp
+; CHECK: %b = icmp
+; CHECK: %c = and i1 %a, %b
+; CHECK: ret i1 %c
+define i1 @negative3(i32 %x, i32 %y, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp slt i32 %x, %nn
+ %b = icmp sge i32 %y, 0 ; should compare %x and not %y
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @negative4
+; CHECK: %a = icmp
+; CHECK: %b = icmp
+; CHECK: %c = and i1 %a, %b
+; CHECK: ret i1 %c
+define i1 @negative4(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp ne i32 %x, %nn ; should be: icmp slt/sle
+ %b = icmp sge i32 %x, 0
+ %c = and i1 %a, %b
+ ret i1 %c
+}
+
+; CHECK-LABEL: define i1 @negative5
+; CHECK: %a = icmp
+; CHECK: %b = icmp
+; CHECK: %c = or i1 %a, %b
+; CHECK: ret i1 %c
+define i1 @negative5(i32 %x, i32 %n) {
+ %nn = and i32 %n, 2147483647
+ %a = icmp slt i32 %x, %nn
+ %b = icmp sge i32 %x, 0
+ %c = or i1 %a, %b ; should be: and
+ ret i1 %c
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/readnone-maythrow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/readnone-maythrow.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/readnone-maythrow.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/readnone-maythrow.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,34 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+declare void @readnone_but_may_throw() readnone
+
+define void @f_0(i32* %ptr) {
+; CHECK-LABEL: @f_0(
+entry:
+; CHECK: store i32 10, i32* %ptr
+; CHECK-NEXT: call void @readnone_but_may_throw()
+; CHECK-NEXT: store i32 20, i32* %ptr, align 4
+; CHECK: ret void
+
+ store i32 10, i32* %ptr
+ call void @readnone_but_may_throw()
+ store i32 20, i32* %ptr
+ ret void
+}
+
+define void @f_1(i1 %cond, i32* %ptr) {
+; CHECK-LABEL: @f_1(
+; CHECK: store i32 10, i32* %ptr
+; CHECK-NEXT: call void @readnone_but_may_throw()
+
+ store i32 10, i32* %ptr
+ call void @readnone_but_may_throw()
+ br i1 %cond, label %left, label %merge
+
+left:
+ store i32 20, i32* %ptr
+ br label %merge
+
+merge:
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/realloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/realloc.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/realloc.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/realloc.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare i8* @realloc(i8*, i64) #1
+declare noalias i8* @malloc(i64) #1
+
+
+define i8* @realloc_null_ptr() #0 {
+; CHECK-LABEL: @realloc_null_ptr(
+; CHECK-NEXT: [[MALLOC:%.*]] = call i8* @malloc(i64 100)
+; CHECK-NEXT: ret i8* [[MALLOC]]
+;
+ %call = call i8* @realloc(i8* null, i64 100) #2
+ ret i8* %call
+}
+
+define i8* @realloc_unknown_ptr(i8* %ptr) #0 {
+; CHECK-LABEL: @realloc_unknown_ptr(
+; CHECK-NEXT: [[CALL:%.*]] = call i8* @realloc(i8* [[PTR:%.*]], i64 100)
+; CHECK-NEXT: ret i8* [[CALL]]
+;
+ %call = call i8* @realloc(i8* %ptr, i64 100) #2
+ ret i8* %call
+}
Added: llvm/trunk/test/Transforms/InstCombine/rem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/rem.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/rem.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/rem.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,672 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i64 @rem_signed(i64 %x1, i64 %y2) {
+; CHECK-LABEL: @rem_signed(
+; CHECK-NEXT: [[TMP1:%.*]] = srem i64 [[X1:%.*]], [[Y2:%.*]]
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %r = sdiv i64 %x1, %y2
+ %r7 = mul i64 %r, %y2
+ %r8 = sub i64 %x1, %r7
+ ret i64 %r8
+}
+
+define <4 x i32> @rem_signed_vec(<4 x i32> %t, <4 x i32> %u) {
+; CHECK-LABEL: @rem_signed_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = srem <4 x i32> [[T:%.*]], [[U:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+;
+ %k = sdiv <4 x i32> %t, %u
+ %l = mul <4 x i32> %k, %u
+ %m = sub <4 x i32> %t, %l
+ ret <4 x i32> %m
+}
+
+define i64 @rem_unsigned(i64 %x1, i64 %y2) {
+; CHECK-LABEL: @rem_unsigned(
+; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[X1:%.*]], [[Y2:%.*]]
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %r = udiv i64 %x1, %y2
+ %r7 = mul i64 %r, %y2
+ %r8 = sub i64 %x1, %r7
+ ret i64 %r8
+}
+
+; PR28672 - https://llvm.org/bugs/show_bug.cgi?id=28672
+
+define i8 @big_divisor(i8 %x) {
+; CHECK-LABEL: @big_divisor(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], -127
+; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[X]], 127
+; CHECK-NEXT: [[REM:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 [[TMP2]]
+; CHECK-NEXT: ret i8 [[REM]]
+;
+ %rem = urem i8 %x, 129
+ ret i8 %rem
+}
+
+define i5 @biggest_divisor(i5 %x) {
+; CHECK-LABEL: @biggest_divisor(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i5 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i5
+; CHECK-NEXT: [[REM:%.*]] = add i5 [[TMP2]], [[X]]
+; CHECK-NEXT: ret i5 [[REM]]
+;
+ %rem = urem i5 %x, -1
+ ret i5 %rem
+}
+
+define i8 @urem_with_sext_bool_divisor(i1 %x, i8 %y) {
+; CHECK-LABEL: @urem_with_sext_bool_divisor(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[REM:%.*]] = select i1 [[TMP1]], i8 0, i8 [[Y]]
+; CHECK-NEXT: ret i8 [[REM]]
+;
+ %s = sext i1 %x to i8
+ %rem = urem i8 %y, %s
+ ret i8 %rem
+}
+
+define <2 x i8> @urem_with_sext_bool_divisor_vec(<2 x i1> %x, <2 x i8> %y) {
+; CHECK-LABEL: @urem_with_sext_bool_divisor_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[Y:%.*]], <i8 -1, i8 -1>
+; CHECK-NEXT: [[REM:%.*]] = select <2 x i1> [[TMP1]], <2 x i8> zeroinitializer, <2 x i8> [[Y]]
+; CHECK-NEXT: ret <2 x i8> [[REM]]
+;
+ %s = sext <2 x i1> %x to <2 x i8>
+ %rem = urem <2 x i8> %y, %s
+ ret <2 x i8> %rem
+}
+
+define <2 x i4> @big_divisor_vec(<2 x i4> %x) {
+; CHECK-LABEL: @big_divisor_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i4> [[X:%.*]], <i4 -3, i4 -3>
+; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i4> [[X]], <i4 3, i4 3>
+; CHECK-NEXT: [[REM:%.*]] = select <2 x i1> [[TMP1]], <2 x i4> [[X]], <2 x i4> [[TMP2]]
+; CHECK-NEXT: ret <2 x i4> [[REM]]
+;
+ %rem = urem <2 x i4> %x, <i4 13, i4 13>
+ ret <2 x i4> %rem
+}
+
+define i8 @urem1(i8 %x, i8 %y) {
+; CHECK-LABEL: @urem1(
+; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %A = udiv i8 %x, %y
+ %B = mul i8 %A, %y
+ %C = sub i8 %x, %B
+ ret i8 %C
+}
+
+define i8 @srem1(i8 %x, i8 %y) {
+; CHECK-LABEL: @srem1(
+; CHECK-NEXT: [[TMP1:%.*]] = srem i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %A = sdiv i8 %x, %y
+ %B = mul i8 %A, %y
+ %C = sub i8 %x, %B
+ ret i8 %C
+}
+
+define i8 @urem2(i8 %x, i8 %y) {
+; CHECK-LABEL: @urem2(
+; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[C:%.*]] = sub i8 0, [[TMP1]]
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %A = udiv i8 %x, %y
+ %B = mul i8 %A, %y
+ %C = sub i8 %B, %x
+ ret i8 %C
+}
+
+define i8 @urem3(i8 %x) {
+; CHECK-LABEL: @urem3(
+; CHECK-NEXT: [[TMP1:%.*]] = urem i8 [[X:%.*]], 3
+; CHECK-NEXT: [[B1:%.*]] = sub i8 [[X]], [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = add i8 [[B1]], [[X]]
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %A = udiv i8 %x, 3
+ %B = mul i8 %A, -3
+ %C = sub i8 %x, %B
+ ret i8 %C
+}
+
+; (((X / Y) * Y) / Y) -> X / Y
+
+define i32 @sdiv_mul_sdiv(i32 %x, i32 %y) {
+; CHECK-LABEL: @sdiv_mul_sdiv(
+; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %div = sdiv i32 %x, %y
+ %mul = mul i32 %div, %y
+ %r = sdiv i32 %mul, %y
+ ret i32 %r
+}
+
+; (((X / Y) * Y) / Y) -> X / Y
+
+define i32 @udiv_mul_udiv(i32 %x, i32 %y) {
+; CHECK-LABEL: @udiv_mul_udiv(
+; CHECK-NEXT: [[R:%.*]] = udiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %div = udiv i32 %x, %y
+ %mul = mul i32 %div, %y
+ %r = udiv i32 %mul, %y
+ ret i32 %r
+}
+
+define i32 @test1(i32 %A) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: ret i32 0
+;
+ %B = srem i32 %A, 1 ; ISA constant 0
+ ret i32 %B
+}
+
+define i32 @test3(i32 %A) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], 7
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %B = urem i32 %A, 8
+ ret i32 %B
+}
+
+define <2 x i32> @vec_power_of_2_constant_splat_divisor(<2 x i32> %A) {
+; CHECK-LABEL: @vec_power_of_2_constant_splat_divisor(
+; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[A:%.*]], <i32 7, i32 7>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %B = urem <2 x i32> %A, <i32 8, i32 8>
+ ret <2 x i32> %B
+}
+
+define <2 x i19> @weird_vec_power_of_2_constant_splat_divisor(<2 x i19> %A) {
+; CHECK-LABEL: @weird_vec_power_of_2_constant_splat_divisor(
+; CHECK-NEXT: [[B:%.*]] = and <2 x i19> [[A:%.*]], <i19 7, i19 7>
+; CHECK-NEXT: ret <2 x i19> [[B]]
+;
+ %B = urem <2 x i19> %A, <i19 8, i19 8>
+ ret <2 x i19> %B
+}
+
+define i1 @test3a(i32 %A) {
+; CHECK-LABEL: @test3a(
+; CHECK-NEXT: [[B1:%.*]] = and i32 [[A:%.*]], 7
+; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[B1]], 0
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %B = srem i32 %A, -8
+ %C = icmp ne i32 %B, 0
+ ret i1 %C
+}
+
+define <2 x i1> @test3a_vec(<2 x i32> %A) {
+; CHECK-LABEL: @test3a_vec(
+; CHECK-NEXT: [[B1:%.*]] = and <2 x i32> [[A:%.*]], <i32 7, i32 7>
+; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i32> [[B1]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %B = srem <2 x i32> %A, <i32 -8, i32 -8>
+ %C = icmp ne <2 x i32> %B, zeroinitializer
+ ret <2 x i1> %C
+}
+
+define i32 @test4(i32 %X, i1 %C) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C:%.*]], i32 0, i32 7
+; CHECK-NEXT: [[R:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %V = select i1 %C, i32 1, i32 8
+ %R = urem i32 %X, %V
+ ret i32 %R
+}
+
+define i32 @test5(i32 %X, i8 %B) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 [[B:%.*]] to i32
+; CHECK-NEXT: [[AMT:%.*]] = shl nuw i32 32, [[SHIFT_UPGRD_1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[AMT]], -1
+; CHECK-NEXT: [[V:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %shift.upgrd.1 = zext i8 %B to i32
+ %Amt = shl i32 32, %shift.upgrd.1
+ %V = urem i32 %X, %Amt
+ ret i32 %V
+}
+
+define i32 @test6(i32 %A) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: ret i32 undef
+;
+ %B = srem i32 %A, 0 ;; undef
+ ret i32 %B
+}
+
+define i32 @test7(i32 %A) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: ret i32 0
+;
+ %B = mul i32 %A, 8
+ %C = srem i32 %B, 4
+ ret i32 %C
+}
+
+define i32 @test8(i32 %A) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: ret i32 0
+;
+ %B = shl i32 %A, 4
+ %C = srem i32 %B, 8
+ ret i32 %C
+}
+
+define i32 @test9(i32 %A) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: ret i32 0
+;
+ %B = mul i32 %A, 64
+ %C = urem i32 %B, 32
+ ret i32 %C
+}
+
+define i32 @test10(i8 %c) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: ret i32 0
+;
+ %tmp.1 = zext i8 %c to i32
+ %tmp.2 = mul i32 %tmp.1, 4
+ %tmp.3 = sext i32 %tmp.2 to i64
+ %tmp.5 = urem i64 %tmp.3, 4
+ %tmp.6 = trunc i64 %tmp.5 to i32
+ ret i32 %tmp.6
+}
+
+define i32 @test11(i32 %i) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: ret i32 0
+;
+ %tmp.1 = and i32 %i, -2
+ %tmp.3 = mul i32 %tmp.1, 2
+ %tmp.5 = urem i32 %tmp.3, 4
+ ret i32 %tmp.5
+}
+
+define i32 @test12(i32 %i) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: ret i32 0
+;
+ %tmp.1 = and i32 %i, -4
+ %tmp.5 = srem i32 %tmp.1, 2
+ ret i32 %tmp.5
+}
+
+define i32 @test13(i32 %i) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: ret i32 0
+;
+ %x = srem i32 %i, %i
+ ret i32 %x
+}
+
+define i64 @test14(i64 %x, i32 %y) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[Y:%.*]]
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[ZEXT]], -1
+; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i64 [[UREM]]
+;
+ %shl = shl i32 1, %y
+ %zext = zext i32 %shl to i64
+ %urem = urem i64 %x, %zext
+ ret i64 %urem
+}
+
+define i64 @test15(i32 %x, i32 %y) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[Y:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: [[UREM:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[UREM]]
+;
+ %shl = shl i32 1, %y
+ %zext0 = zext i32 %shl to i64
+ %zext1 = zext i32 %x to i64
+ %urem = urem i64 %zext1, %zext0
+ ret i64 %urem
+}
+
+define i32 @test16(i32 %x, i32 %y) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[Y:%.*]], 11
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], 3
+; CHECK-NEXT: [[REM:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[REM]]
+;
+ %shr = lshr i32 %y, 11
+ %and = and i32 %shr, 4
+ %add = add i32 %and, 4
+ %rem = urem i32 %x, %add
+ ret i32 %rem
+}
+
+define i32 @test17(i32 %X) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %A = urem i32 1, %X
+ ret i32 %A
+}
+
+define i32 @test18(i16 %x, i32 %y) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[X:%.*]], 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 63, i32 31
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %1 = and i16 %x, 4
+ %2 = icmp ne i16 %1, 0
+ %3 = select i1 %2, i32 32, i32 64
+ %4 = urem i32 %y, %3
+ ret i32 %4
+}
+
+define i32 @test19(i32 %x, i32 %y) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]]
+; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]]
+; CHECK-NEXT: [[C:%.*]] = and i32 [[A]], [[B]]
+; CHECK-NEXT: [[D:%.*]] = add i32 [[C]], [[A]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1
+; CHECK-NEXT: [[E:%.*]] = and i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: ret i32 [[E]]
+;
+ %A = shl i32 1, %x
+ %B = shl i32 1, %y
+ %C = and i32 %A, %B
+ %D = add i32 %C, %A
+ %E = urem i32 %y, %D
+ ret i32 %E
+}
+
+define i32 @test19_commutative0(i32 %x, i32 %y) {
+; CHECK-LABEL: @test19_commutative0(
+; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]]
+; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]]
+; CHECK-NEXT: [[C:%.*]] = and i32 [[B]], [[A]]
+; CHECK-NEXT: [[D:%.*]] = add i32 [[C]], [[A]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1
+; CHECK-NEXT: [[E:%.*]] = and i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: ret i32 [[E]]
+;
+ %A = shl i32 1, %x
+ %B = shl i32 1, %y
+ %C = and i32 %B, %A ; swapped
+ %D = add i32 %C, %A
+ %E = urem i32 %y, %D
+ ret i32 %E
+}
+
+define i32 @test19_commutative1(i32 %x, i32 %y) {
+; CHECK-LABEL: @test19_commutative1(
+; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]]
+; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]]
+; CHECK-NEXT: [[C:%.*]] = and i32 [[A]], [[B]]
+; CHECK-NEXT: [[D:%.*]] = add i32 [[A]], [[C]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1
+; CHECK-NEXT: [[E:%.*]] = and i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: ret i32 [[E]]
+;
+ %A = shl i32 1, %x
+ %B = shl i32 1, %y
+ %C = and i32 %A, %B
+ %D = add i32 %A, %C ; swapped
+ %E = urem i32 %y, %D
+ ret i32 %E
+}
+
+define i32 @test19_commutative2(i32 %x, i32 %y) {
+; CHECK-LABEL: @test19_commutative2(
+; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]]
+; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]]
+; CHECK-NEXT: [[C:%.*]] = and i32 [[B]], [[A]]
+; CHECK-NEXT: [[D:%.*]] = add i32 [[A]], [[C]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1
+; CHECK-NEXT: [[E:%.*]] = and i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: ret i32 [[E]]
+;
+ %A = shl i32 1, %x
+ %B = shl i32 1, %y
+ %C = and i32 %B, %A ; swapped
+ %D = add i32 %A, %C ; swapped
+ %E = urem i32 %y, %D
+ ret i32 %E
+}
+
+define <2 x i64> @test20(<2 x i64> %X, <2 x i1> %C) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i64> <i64 1, i64 2>, <2 x i64> zeroinitializer
+; CHECK-NEXT: ret <2 x i64> [[R]]
+;
+ %V = select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> <i64 8, i64 9>
+ %R = urem <2 x i64> %V, <i64 2, i64 3>
+ ret <2 x i64> %R
+}
+
+define i32 @test21(i1 %c0, i32* %p) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C0:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT: [[PHITMP:%.*]] = srem i32 [[V]], 5
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[PHITMP]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[LHS]]
+;
+entry:
+ br i1 %c0, label %if.then, label %if.end
+
+if.then:
+ %v = load volatile i32, i32* %p
+ br label %if.end
+
+if.end:
+ %lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
+ %rem = srem i32 %lhs, 5
+ ret i32 %rem
+}
+
+ at a = common global [5 x i16] zeroinitializer, align 2
+ at b = common global i16 0, align 2
+
+define i32 @pr27968_0(i1 %c0, i32* %p) {
+; CHECK-LABEL: @pr27968_0(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C0:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label [[REM_IS_SAFE:%.*]], label [[REM_IS_UNSAFE:%.*]]
+; CHECK: rem.is.safe:
+; CHECK-NEXT: ret i32 0
+; CHECK: rem.is.unsafe:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ br i1 %c0, label %if.then, label %if.end
+
+if.then:
+ %v = load volatile i32, i32* %p
+ br label %if.end
+
+if.end:
+ %lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
+ br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label %rem.is.safe, label %rem.is.unsafe
+
+rem.is.safe:
+ %rem = srem i32 %lhs, zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
+ ret i32 %rem
+
+rem.is.unsafe:
+ ret i32 0
+}
+
+define i32 @pr27968_1(i1 %c0, i1 %always_false, i32* %p) {
+; CHECK-LABEL: @pr27968_1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C0:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[V]], [[IF_THEN]] ], [ 5, [[ENTRY:%.*]] ]
+; CHECK-NEXT: br i1 [[ALWAYS_FALSE:%.*]], label [[REM_IS_SAFE:%.*]], label [[REM_IS_UNSAFE:%.*]]
+; CHECK: rem.is.safe:
+; CHECK-NEXT: [[REM:%.*]] = srem i32 [[LHS]], -2147483648
+; CHECK-NEXT: ret i32 [[REM]]
+; CHECK: rem.is.unsafe:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ br i1 %c0, label %if.then, label %if.end
+
+if.then:
+ %v = load volatile i32, i32* %p
+ br label %if.end
+
+if.end:
+ %lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
+ br i1 %always_false, label %rem.is.safe, label %rem.is.unsafe
+
+rem.is.safe:
+ %rem = srem i32 %lhs, -2147483648
+ ret i32 %rem
+
+rem.is.unsafe:
+ ret i32 0
+}
+
+define i32 @pr27968_2(i1 %c0, i32* %p) {
+; CHECK-LABEL: @pr27968_2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C0:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label [[REM_IS_SAFE:%.*]], label [[REM_IS_UNSAFE:%.*]]
+; CHECK: rem.is.safe:
+; CHECK-NEXT: ret i32 0
+; CHECK: rem.is.unsafe:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ br i1 %c0, label %if.then, label %if.end
+
+if.then:
+ %v = load volatile i32, i32* %p
+ br label %if.end
+
+if.end:
+ %lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
+ br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label %rem.is.safe, label %rem.is.unsafe
+
+rem.is.safe:
+ %rem = urem i32 %lhs, zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
+ ret i32 %rem
+
+rem.is.unsafe:
+ ret i32 0
+}
+
+define i32 @pr27968_3(i1 %c0, i1 %always_false, i32* %p) {
+; CHECK-LABEL: @pr27968_3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C0:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT: [[PHITMP:%.*]] = and i32 [[V]], 2147483647
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[PHITMP]], [[IF_THEN]] ], [ 5, [[ENTRY:%.*]] ]
+; CHECK-NEXT: br i1 [[ALWAYS_FALSE:%.*]], label [[REM_IS_SAFE:%.*]], label [[REM_IS_UNSAFE:%.*]]
+; CHECK: rem.is.safe:
+; CHECK-NEXT: ret i32 [[LHS]]
+; CHECK: rem.is.unsafe:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ br i1 %c0, label %if.then, label %if.end
+
+if.then:
+ %v = load volatile i32, i32* %p
+ br label %if.end
+
+if.end:
+ %lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
+ br i1 %always_false, label %rem.is.safe, label %rem.is.unsafe
+
+rem.is.safe:
+ %rem = urem i32 %lhs, -2147483648
+ ret i32 %rem
+
+rem.is.unsafe:
+ ret i32 0
+}
+
+define i32 @test22(i32 %A) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 2147483647
+; CHECK-NEXT: [[MUL:%.*]] = urem i32 [[AND]], 2147483647
+; CHECK-NEXT: ret i32 [[MUL]]
+;
+ %and = and i32 %A, 2147483647
+ %mul = srem i32 %and, 2147483647
+ ret i32 %mul
+}
+
+define <2 x i32> @test23(<2 x i32> %A) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT: [[MUL:%.*]] = urem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT: ret <2 x i32> [[MUL]]
+;
+ %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+ %mul = srem <2 x i32> %and, <i32 2147483647, i32 2147483647>
+ ret <2 x i32> %mul
+}
+
+; FP division-by-zero is not UB.
+
+define double @PR34870(i1 %cond, double %x, double %y) {
+; CHECK-LABEL: @PR34870(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], double [[Y:%.*]], double 0.000000e+00
+; CHECK-NEXT: [[FMOD:%.*]] = frem double [[X:%.*]], [[SEL]]
+; CHECK-NEXT: ret double [[FMOD]]
+;
+ %sel = select i1 %cond, double %y, double 0.0
+ %fmod = frem double %x, %sel
+ ret double %fmod
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/rotate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/rotate.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/rotate.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/rotate.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,705 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+; TODO: Canonicalize rotate by constant to funnel shift intrinsics.
+; This should help cost modeling for vectorization, inlining, etc.
+; If a target does not have a rotate instruction, the expansion will
+; be exactly these same 3 basic ops (shl/lshr/or).
+
+define i32 @rotl_i32_constant(i32 %x) {
+; CHECK-LABEL: @rotl_i32_constant(
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 11
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[X]], 21
+; CHECK-NEXT: [[R:%.*]] = or i32 [[SHR]], [[SHL]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %shl = shl i32 %x, 11
+ %shr = lshr i32 %x, 21
+ %r = or i32 %shr, %shl
+ ret i32 %r
+}
+
+define i42 @rotr_i42_constant(i42 %x) {
+; CHECK-LABEL: @rotr_i42_constant(
+; CHECK-NEXT: [[SHL:%.*]] = shl i42 [[X:%.*]], 31
+; CHECK-NEXT: [[SHR:%.*]] = lshr i42 [[X]], 11
+; CHECK-NEXT: [[R:%.*]] = or i42 [[SHR]], [[SHL]]
+; CHECK-NEXT: ret i42 [[R]]
+;
+ %shl = shl i42 %x, 31
+ %shr = lshr i42 %x, 11
+ %r = or i42 %shr, %shl
+ ret i42 %r
+}
+
+define i8 @rotr_i8_constant_commute(i8 %x) {
+; CHECK-LABEL: @rotr_i8_constant_commute(
+; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], 5
+; CHECK-NEXT: [[SHR:%.*]] = lshr i8 [[X]], 3
+; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], [[SHR]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %shl = shl i8 %x, 5
+ %shr = lshr i8 %x, 3
+ %r = or i8 %shl, %shr
+ ret i8 %r
+}
+
+define i88 @rotl_i88_constant_commute(i88 %x) {
+; CHECK-LABEL: @rotl_i88_constant_commute(
+; CHECK-NEXT: [[SHL:%.*]] = shl i88 [[X:%.*]], 44
+; CHECK-NEXT: [[SHR:%.*]] = lshr i88 [[X]], 44
+; CHECK-NEXT: [[R:%.*]] = or i88 [[SHL]], [[SHR]]
+; CHECK-NEXT: ret i88 [[R]]
+;
+ %shl = shl i88 %x, 44
+ %shr = lshr i88 %x, 44
+ %r = or i88 %shl, %shr
+ ret i88 %r
+}
+
+; Vector types are allowed.
+
+define <2 x i16> @rotl_v2i16_constant_splat(<2 x i16> %x) {
+; CHECK-LABEL: @rotl_v2i16_constant_splat(
+; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i16> [[X:%.*]], <i16 1, i16 1>
+; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i16> [[X]], <i16 15, i16 15>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i16> [[SHL]], [[SHR]]
+; CHECK-NEXT: ret <2 x i16> [[R]]
+;
+ %shl = shl <2 x i16> %x, <i16 1, i16 1>
+ %shr = lshr <2 x i16> %x, <i16 15, i16 15>
+ %r = or <2 x i16> %shl, %shr
+ ret <2 x i16> %r
+}
+
+; Non-power-of-2 vector types are allowed.
+
+define <2 x i17> @rotr_v2i17_constant_splat(<2 x i17> %x) {
+; CHECK-LABEL: @rotr_v2i17_constant_splat(
+; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i17> [[X:%.*]], <i17 12, i17 12>
+; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i17> [[X]], <i17 5, i17 5>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i17> [[SHR]], [[SHL]]
+; CHECK-NEXT: ret <2 x i17> [[R]]
+;
+ %shl = shl <2 x i17> %x, <i17 12, i17 12>
+ %shr = lshr <2 x i17> %x, <i17 5, i17 5>
+ %r = or <2 x i17> %shr, %shl
+ ret <2 x i17> %r
+}
+
+; Allow arbitrary shift constants.
+
+define <2 x i32> @rotr_v2i32_constant_nonsplat(<2 x i32> %x) {
+; CHECK-LABEL: @rotr_v2i32_constant_nonsplat(
+; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> [[X:%.*]], <i32 17, i32 19>
+; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i32> [[X]], <i32 15, i32 13>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i32> [[SHL]], [[SHR]]
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %shl = shl <2 x i32> %x, <i32 17, i32 19>
+ %shr = lshr <2 x i32> %x, <i32 15, i32 13>
+ %r = or <2 x i32> %shl, %shr
+ ret <2 x i32> %r
+}
+
+define <2 x i36> @rotl_v2i16_constant_nonsplat(<2 x i36> %x) {
+; CHECK-LABEL: @rotl_v2i16_constant_nonsplat(
+; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i36> [[X:%.*]], <i36 21, i36 11>
+; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i36> [[X]], <i36 15, i36 25>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i36> [[SHL]], [[SHR]]
+; CHECK-NEXT: ret <2 x i36> [[R]]
+;
+ %shl = shl <2 x i36> %x, <i36 21, i36 11>
+ %shr = lshr <2 x i36> %x, <i36 15, i36 25>
+ %r = or <2 x i36> %shl, %shr
+ ret <2 x i36> %r
+}
+
+; The most basic rotate by variable - no guards for UB due to oversized shifts.
+; This cannot be canonicalized to funnel shift target-independently. The safe
+; expansion includes masking for the shift amount that is not included here,
+; so it could be more expensive.
+
+define i32 @rotl_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: @rotl_i32(
+; CHECK-NEXT: [[SUB:%.*]] = sub i32 32, [[Y:%.*]]
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[X]], [[SUB]]
+; CHECK-NEXT: [[R:%.*]] = or i32 [[SHR]], [[SHL]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %sub = sub i32 32, %y
+ %shl = shl i32 %x, %y
+ %shr = lshr i32 %x, %sub
+ %r = or i32 %shr, %shl
+ ret i32 %r
+}
+
+; Non-power-of-2 types should follow the same reasoning. Left/right is determined by subtract.
+
+define i37 @rotr_i37(i37 %x, i37 %y) {
+; CHECK-LABEL: @rotr_i37(
+; CHECK-NEXT: [[SUB:%.*]] = sub i37 37, [[Y:%.*]]
+; CHECK-NEXT: [[SHL:%.*]] = shl i37 [[X:%.*]], [[SUB]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr i37 [[X]], [[Y]]
+; CHECK-NEXT: [[R:%.*]] = or i37 [[SHR]], [[SHL]]
+; CHECK-NEXT: ret i37 [[R]]
+;
+ %sub = sub i37 37, %y
+ %shl = shl i37 %x, %sub
+ %shr = lshr i37 %x, %y
+ %r = or i37 %shr, %shl
+ ret i37 %r
+}
+
+; Commute 'or' operands.
+
+define i8 @rotr_i8_commute(i8 %x, i8 %y) {
+; CHECK-LABEL: @rotr_i8_commute(
+; CHECK-NEXT: [[SUB:%.*]] = sub i8 8, [[Y:%.*]]
+; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], [[SUB]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr i8 [[X]], [[Y]]
+; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], [[SHR]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %sub = sub i8 8, %y
+ %shl = shl i8 %x, %sub
+ %shr = lshr i8 %x, %y
+ %r = or i8 %shl, %shr
+ ret i8 %r
+}
+
+; Vector types should follow the same rules.
+
+define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @rotl_v4i32(
+; CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, [[Y:%.*]]
+; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr <4 x i32> [[X]], [[SUB]]
+; CHECK-NEXT: [[R:%.*]] = or <4 x i32> [[SHL]], [[SHR]]
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %sub = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
+ %shl = shl <4 x i32> %x, %y
+ %shr = lshr <4 x i32> %x, %sub
+ %r = or <4 x i32> %shl, %shr
+ ret <4 x i32> %r
+}
+
+; Non-power-of-2 vector types should follow the same rules.
+
+define <3 x i42> @rotr_v3i42(<3 x i42> %x, <3 x i42> %y) {
+; CHECK-LABEL: @rotr_v3i42(
+; CHECK-NEXT: [[SUB:%.*]] = sub <3 x i42> <i42 42, i42 42, i42 42>, [[Y:%.*]]
+; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i42> [[X:%.*]], [[SUB]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr <3 x i42> [[X]], [[Y]]
+; CHECK-NEXT: [[R:%.*]] = or <3 x i42> [[SHR]], [[SHL]]
+; CHECK-NEXT: ret <3 x i42> [[R]]
+;
+ %sub = sub <3 x i42> <i42 42, i42 42, i42 42>, %y
+ %shl = shl <3 x i42> %x, %sub
+ %shr = lshr <3 x i42> %x, %y
+ %r = or <3 x i42> %shr, %shl
+ ret <3 x i42> %r
+}
+
+; This is the canonical pattern for a UB-safe rotate-by-variable with power-of-2-size scalar type.
+; The backend expansion of funnel shift for targets that don't have a rotate instruction should
+; match the original IR, so it is always good to canonicalize to the intrinsics for this pattern.
+
+define i32 @rotl_safe_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: @rotl_safe_i32(
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[X]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %negy = sub i32 0, %y
+ %ymask = and i32 %y, 31
+ %negymask = and i32 %negy, 31
+ %shl = shl i32 %x, %ymask
+ %shr = lshr i32 %x, %negymask
+ %r = or i32 %shr, %shl
+ ret i32 %r
+}
+
+; Extra uses don't change anything.
+
+define i16 @rotl_safe_i16_commute_extra_use(i16 %x, i16 %y, i16* %p) {
+; CHECK-LABEL: @rotl_safe_i16_commute_extra_use(
+; CHECK-NEXT: [[NEGY:%.*]] = sub i16 0, [[Y:%.*]]
+; CHECK-NEXT: [[NEGYMASK:%.*]] = and i16 [[NEGY]], 15
+; CHECK-NEXT: store i16 [[NEGYMASK]], i16* [[P:%.*]], align 2
+; CHECK-NEXT: [[R:%.*]] = call i16 @llvm.fshl.i16(i16 [[X:%.*]], i16 [[X]], i16 [[Y]])
+; CHECK-NEXT: ret i16 [[R]]
+;
+ %negy = sub i16 0, %y
+ %ymask = and i16 %y, 15
+ %negymask = and i16 %negy, 15
+ store i16 %negymask, i16* %p
+ %shl = shl i16 %x, %ymask
+ %shr = lshr i16 %x, %negymask
+ %r = or i16 %shl, %shr
+ ret i16 %r
+}
+
+; Left/right is determined by the negation.
+
+define i64 @rotr_safe_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: @rotr_safe_i64(
+; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.fshr.i64(i64 [[X:%.*]], i64 [[X]], i64 [[Y:%.*]])
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %negy = sub i64 0, %y
+ %ymask = and i64 %y, 63
+ %negymask = and i64 %negy, 63
+ %shl = shl i64 %x, %negymask
+ %shr = lshr i64 %x, %ymask
+ %r = or i64 %shr, %shl
+ ret i64 %r
+}
+
+; Extra uses don't change anything.
+
+define i8 @rotr_safe_i8_commute_extra_use(i8 %x, i8 %y, i8* %p) {
+; CHECK-LABEL: @rotr_safe_i8_commute_extra_use(
+; CHECK-NEXT: [[NEGY:%.*]] = sub i8 0, [[Y:%.*]]
+; CHECK-NEXT: [[YMASK:%.*]] = and i8 [[Y]], 7
+; CHECK-NEXT: [[NEGYMASK:%.*]] = and i8 [[NEGY]], 7
+; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], [[NEGYMASK]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr i8 [[X]], [[YMASK]]
+; CHECK-NEXT: store i8 [[SHR]], i8* [[P:%.*]], align 1
+; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], [[SHR]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %negy = sub i8 0, %y
+ %ymask = and i8 %y, 7
+ %negymask = and i8 %negy, 7
+ %shl = shl i8 %x, %negymask
+ %shr = lshr i8 %x, %ymask
+ store i8 %shr, i8* %p
+ %r = or i8 %shl, %shr
+ ret i8 %r
+}
+
+; Vectors follow the same rules.
+
+define <2 x i32> @rotl_safe_v2i32(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @rotl_safe_v2i32(
+; CHECK-NEXT: [[R:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[X]], <2 x i32> [[Y:%.*]])
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %negy = sub <2 x i32> zeroinitializer, %y
+ %ymask = and <2 x i32> %y, <i32 31, i32 31>
+ %negymask = and <2 x i32> %negy, <i32 31, i32 31>
+ %shl = shl <2 x i32> %x, %ymask
+ %shr = lshr <2 x i32> %x, %negymask
+ %r = or <2 x i32> %shr, %shl
+ ret <2 x i32> %r
+}
+
+; Vectors follow the same rules.
+
+define <3 x i16> @rotr_safe_v3i16(<3 x i16> %x, <3 x i16> %y) {
+; CHECK-LABEL: @rotr_safe_v3i16(
+; CHECK-NEXT: [[R:%.*]] = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> [[X:%.*]], <3 x i16> [[X]], <3 x i16> [[Y:%.*]])
+; CHECK-NEXT: ret <3 x i16> [[R]]
+;
+ %negy = sub <3 x i16> zeroinitializer, %y
+ %ymask = and <3 x i16> %y, <i16 15, i16 15, i16 15>
+ %negymask = and <3 x i16> %negy, <i16 15, i16 15, i16 15>
+ %shl = shl <3 x i16> %x, %negymask
+ %shr = lshr <3 x i16> %x, %ymask
+ %r = or <3 x i16> %shr, %shl
+ ret <3 x i16> %r
+}
+
+; These are optionally UB-free rotate left/right patterns that are narrowed to a smaller bitwidth.
+; See PR34046, PR16726, and PR39624 for motivating examples:
+; https://bugs.llvm.org/show_bug.cgi?id=34046
+; https://bugs.llvm.org/show_bug.cgi?id=16726
+; https://bugs.llvm.org/show_bug.cgi?id=39624
+
+define i16 @rotate_left_16bit(i16 %v, i32 %shift) {
+; CHECK-LABEL: @rotate_left_16bit(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[SHIFT:%.*]] to i16
+; CHECK-NEXT: [[CONV2:%.*]] = call i16 @llvm.fshl.i16(i16 [[V:%.*]], i16 [[V]], i16 [[TMP1]])
+; CHECK-NEXT: ret i16 [[CONV2]]
+;
+ %and = and i32 %shift, 15
+ %conv = zext i16 %v to i32
+ %shl = shl i32 %conv, %and
+ %sub = sub i32 16, %and
+ %shr = lshr i32 %conv, %sub
+ %or = or i32 %shr, %shl
+ %conv2 = trunc i32 %or to i16
+ ret i16 %conv2
+}
+
+; Commute the 'or' operands and try a vector type.
+
+define <2 x i16> @rotate_left_commute_16bit_vec(<2 x i16> %v, <2 x i32> %shift) {
+; CHECK-LABEL: @rotate_left_commute_16bit_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[SHIFT:%.*]] to <2 x i16>
+; CHECK-NEXT: [[CONV2:%.*]] = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> [[V:%.*]], <2 x i16> [[V]], <2 x i16> [[TMP1]])
+; CHECK-NEXT: ret <2 x i16> [[CONV2]]
+;
+ %and = and <2 x i32> %shift, <i32 15, i32 15>
+ %conv = zext <2 x i16> %v to <2 x i32>
+ %shl = shl <2 x i32> %conv, %and
+ %sub = sub <2 x i32> <i32 16, i32 16>, %and
+ %shr = lshr <2 x i32> %conv, %sub
+ %or = or <2 x i32> %shl, %shr
+ %conv2 = trunc <2 x i32> %or to <2 x i16>
+ ret <2 x i16> %conv2
+}
+
+; Change the size, rotation direction (the subtract is on the left-shift), and mask op.
+
+define i8 @rotate_right_8bit(i8 %v, i3 %shift) {
+; CHECK-LABEL: @rotate_right_8bit(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i3 [[SHIFT:%.*]] to i8
+; CHECK-NEXT: [[CONV2:%.*]] = call i8 @llvm.fshr.i8(i8 [[V:%.*]], i8 [[V]], i8 [[TMP1]])
+; CHECK-NEXT: ret i8 [[CONV2]]
+;
+ %and = zext i3 %shift to i32
+ %conv = zext i8 %v to i32
+ %shr = lshr i32 %conv, %and
+ %sub = sub i32 8, %and
+ %shl = shl i32 %conv, %sub
+ %or = or i32 %shl, %shr
+ %conv2 = trunc i32 %or to i8
+ ret i8 %conv2
+}
+
+; The shifted value does not need to be a zexted value; here it is masked.
+; The shift mask could be less than the bitwidth, but this is still ok.
+
+define i8 @rotate_right_commute_8bit(i32 %v, i32 %shift) {
+; CHECK-LABEL: @rotate_right_commute_8bit(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[SHIFT:%.*]] to i8
+; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[V:%.*]] to i8
+; CHECK-NEXT: [[CONV2:%.*]] = call i8 @llvm.fshr.i8(i8 [[TMP3]], i8 [[TMP3]], i8 [[TMP2]])
+; CHECK-NEXT: ret i8 [[CONV2]]
+;
+ %and = and i32 %shift, 3
+ %conv = and i32 %v, 255
+ %shr = lshr i32 %conv, %and
+ %sub = sub i32 8, %and
+ %shl = shl i32 %conv, %sub
+ %or = or i32 %shr, %shl
+ %conv2 = trunc i32 %or to i8
+ ret i8 %conv2
+}
+
+; If the original source does not mask the shift amount,
+; we still do the transform by adding masks to make it safe.
+
+define i8 @rotate8_not_safe(i8 %v, i32 %shamt) {
+; CHECK-LABEL: @rotate8_not_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT:%.*]] to i8
+; CHECK-NEXT: [[RET:%.*]] = call i8 @llvm.fshl.i8(i8 [[V:%.*]], i8 [[V]], i8 [[TMP1]])
+; CHECK-NEXT: ret i8 [[RET]]
+;
+ %conv = zext i8 %v to i32
+ %sub = sub i32 8, %shamt
+ %shr = lshr i32 %conv, %sub
+ %shl = shl i32 %conv, %shamt
+ %or = or i32 %shr, %shl
+ %ret = trunc i32 %or to i8
+ ret i8 %ret
+}
+
+; A non-power-of-2 destination type can't be masked as above.
+
+define i9 @rotate9_not_safe(i9 %v, i32 %shamt) {
+; CHECK-LABEL: @rotate9_not_safe(
+; CHECK-NEXT: [[CONV:%.*]] = zext i9 [[V:%.*]] to i32
+; CHECK-NEXT: [[SUB:%.*]] = sub i32 9, [[SHAMT:%.*]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[CONV]], [[SUB]]
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[SHAMT]]
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
+; CHECK-NEXT: [[RET:%.*]] = trunc i32 [[OR]] to i9
+; CHECK-NEXT: ret i9 [[RET]]
+;
+ %conv = zext i9 %v to i32
+ %sub = sub i32 9, %shamt
+ %shr = lshr i32 %conv, %sub
+ %shl = shl i32 %conv, %shamt
+ %or = or i32 %shr, %shl
+ %ret = trunc i32 %or to i9
+ ret i9 %ret
+}
+
+; We should narrow (v << (s & 15)) | (v >> (-s & 15))
+; when both v and s have been promoted.
+
+define i16 @rotateleft_16_neg_mask(i16 %v, i16 %shamt) {
+; CHECK-LABEL: @rotateleft_16_neg_mask(
+; CHECK-NEXT: [[RET:%.*]] = call i16 @llvm.fshl.i16(i16 [[V:%.*]], i16 [[V]], i16 [[SHAMT:%.*]])
+; CHECK-NEXT: ret i16 [[RET]]
+;
+ %neg = sub i16 0, %shamt
+ %lshamt = and i16 %shamt, 15
+ %lshamtconv = zext i16 %lshamt to i32
+ %rshamt = and i16 %neg, 15
+ %rshamtconv = zext i16 %rshamt to i32
+ %conv = zext i16 %v to i32
+ %shl = shl i32 %conv, %lshamtconv
+ %shr = lshr i32 %conv, %rshamtconv
+ %or = or i32 %shr, %shl
+ %ret = trunc i32 %or to i16
+ ret i16 %ret
+}
+
+define i16 @rotateleft_16_neg_mask_commute(i16 %v, i16 %shamt) {
+; CHECK-LABEL: @rotateleft_16_neg_mask_commute(
+; CHECK-NEXT: [[RET:%.*]] = call i16 @llvm.fshl.i16(i16 [[V:%.*]], i16 [[V]], i16 [[SHAMT:%.*]])
+; CHECK-NEXT: ret i16 [[RET]]
+;
+ %neg = sub i16 0, %shamt
+ %lshamt = and i16 %shamt, 15
+ %lshamtconv = zext i16 %lshamt to i32
+ %rshamt = and i16 %neg, 15
+ %rshamtconv = zext i16 %rshamt to i32
+ %conv = zext i16 %v to i32
+ %shl = shl i32 %conv, %lshamtconv
+ %shr = lshr i32 %conv, %rshamtconv
+ %or = or i32 %shl, %shr
+ %ret = trunc i32 %or to i16
+ ret i16 %ret
+}
+
+define i8 @rotateright_8_neg_mask(i8 %v, i8 %shamt) {
+; CHECK-LABEL: @rotateright_8_neg_mask(
+; CHECK-NEXT: [[RET:%.*]] = call i8 @llvm.fshr.i8(i8 [[V:%.*]], i8 [[V]], i8 [[SHAMT:%.*]])
+; CHECK-NEXT: ret i8 [[RET]]
+;
+ %neg = sub i8 0, %shamt
+ %rshamt = and i8 %shamt, 7
+ %rshamtconv = zext i8 %rshamt to i32
+ %lshamt = and i8 %neg, 7
+ %lshamtconv = zext i8 %lshamt to i32
+ %conv = zext i8 %v to i32
+ %shl = shl i32 %conv, %lshamtconv
+ %shr = lshr i32 %conv, %rshamtconv
+ %or = or i32 %shr, %shl
+ %ret = trunc i32 %or to i8
+ ret i8 %ret
+}
+
+define i8 @rotateright_8_neg_mask_commute(i8 %v, i8 %shamt) {
+; CHECK-LABEL: @rotateright_8_neg_mask_commute(
+; CHECK-NEXT: [[RET:%.*]] = call i8 @llvm.fshr.i8(i8 [[V:%.*]], i8 [[V]], i8 [[SHAMT:%.*]])
+; CHECK-NEXT: ret i8 [[RET]]
+;
+ %neg = sub i8 0, %shamt
+ %rshamt = and i8 %shamt, 7
+ %rshamtconv = zext i8 %rshamt to i32
+ %lshamt = and i8 %neg, 7
+ %lshamtconv = zext i8 %lshamt to i32
+ %conv = zext i8 %v to i32
+ %shl = shl i32 %conv, %lshamtconv
+ %shr = lshr i32 %conv, %rshamtconv
+ %or = or i32 %shl, %shr
+ %ret = trunc i32 %or to i8
+ ret i8 %ret
+}
+
+; The shift amount may already be in the wide type,
+; so we need to truncate it going into the rotate pattern.
+
+define i16 @rotateright_16_neg_mask_wide_amount(i16 %v, i32 %shamt) {
+; CHECK-LABEL: @rotateright_16_neg_mask_wide_amount(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT:%.*]] to i16
+; CHECK-NEXT: [[RET:%.*]] = call i16 @llvm.fshr.i16(i16 [[V:%.*]], i16 [[V]], i16 [[TMP1]])
+; CHECK-NEXT: ret i16 [[RET]]
+;
+ %neg = sub i32 0, %shamt
+ %rshamt = and i32 %shamt, 15
+ %lshamt = and i32 %neg, 15
+ %conv = zext i16 %v to i32
+ %shl = shl i32 %conv, %lshamt
+ %shr = lshr i32 %conv, %rshamt
+ %or = or i32 %shr, %shl
+ %ret = trunc i32 %or to i16
+ ret i16 %ret
+}
+
+define i16 @rotateright_16_neg_mask_wide_amount_commute(i16 %v, i32 %shamt) {
+; CHECK-LABEL: @rotateright_16_neg_mask_wide_amount_commute(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT:%.*]] to i16
+; CHECK-NEXT: [[RET:%.*]] = call i16 @llvm.fshr.i16(i16 [[V:%.*]], i16 [[V]], i16 [[TMP1]])
+; CHECK-NEXT: ret i16 [[RET]]
+;
+ %neg = sub i32 0, %shamt
+ %rshamt = and i32 %shamt, 15
+ %lshamt = and i32 %neg, 15
+ %conv = zext i16 %v to i32
+ %shl = shl i32 %conv, %lshamt
+ %shr = lshr i32 %conv, %rshamt
+ %or = or i32 %shl, %shr
+ %ret = trunc i32 %or to i16
+ ret i16 %ret
+}
+
+define i8 @rotateleft_8_neg_mask_wide_amount(i8 %v, i32 %shamt) {
+; CHECK-LABEL: @rotateleft_8_neg_mask_wide_amount(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT:%.*]] to i8
+; CHECK-NEXT: [[RET:%.*]] = call i8 @llvm.fshl.i8(i8 [[V:%.*]], i8 [[V]], i8 [[TMP1]])
+; CHECK-NEXT: ret i8 [[RET]]
+;
+ %neg = sub i32 0, %shamt
+ %lshamt = and i32 %shamt, 7
+ %rshamt = and i32 %neg, 7
+ %conv = zext i8 %v to i32
+ %shl = shl i32 %conv, %lshamt
+ %shr = lshr i32 %conv, %rshamt
+ %or = or i32 %shr, %shl
+ %ret = trunc i32 %or to i8
+ ret i8 %ret
+}
+
+define i8 @rotateleft_8_neg_mask_wide_amount_commute(i8 %v, i32 %shamt) {
+; CHECK-LABEL: @rotateleft_8_neg_mask_wide_amount_commute(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT:%.*]] to i8
+; CHECK-NEXT: [[RET:%.*]] = call i8 @llvm.fshl.i8(i8 [[V:%.*]], i8 [[V]], i8 [[TMP1]])
+; CHECK-NEXT: ret i8 [[RET]]
+;
+ %neg = sub i32 0, %shamt
+ %lshamt = and i32 %shamt, 7
+ %rshamt = and i32 %neg, 7
+ %conv = zext i8 %v to i32
+ %shl = shl i32 %conv, %lshamt
+ %shr = lshr i32 %conv, %rshamt
+ %or = or i32 %shl, %shr
+ %ret = trunc i32 %or to i8
+ ret i8 %ret
+}
+
+; Non-power-of-2 types. This could be transformed, but it's not a typical rotate pattern.
+
+define i9 @rotateleft_9_neg_mask_wide_amount_commute(i9 %v, i33 %shamt) {
+; CHECK-LABEL: @rotateleft_9_neg_mask_wide_amount_commute(
+; CHECK-NEXT: [[NEG:%.*]] = sub i33 0, [[SHAMT:%.*]]
+; CHECK-NEXT: [[LSHAMT:%.*]] = and i33 [[SHAMT]], 8
+; CHECK-NEXT: [[RSHAMT:%.*]] = and i33 [[NEG]], 8
+; CHECK-NEXT: [[CONV:%.*]] = zext i9 [[V:%.*]] to i33
+; CHECK-NEXT: [[SHL:%.*]] = shl i33 [[CONV]], [[LSHAMT]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr i33 [[CONV]], [[RSHAMT]]
+; CHECK-NEXT: [[OR:%.*]] = or i33 [[SHL]], [[SHR]]
+; CHECK-NEXT: [[RET:%.*]] = trunc i33 [[OR]] to i9
+; CHECK-NEXT: ret i9 [[RET]]
+;
+ %neg = sub i33 0, %shamt
+ %lshamt = and i33 %shamt, 8
+ %rshamt = and i33 %neg, 8
+ %conv = zext i9 %v to i33
+ %shl = shl i33 %conv, %lshamt
+ %shr = lshr i33 %conv, %rshamt
+ %or = or i33 %shl, %shr
+ %ret = trunc i33 %or to i9
+ ret i9 %ret
+}
+
+; Convert select pattern to masked shift that ends in 'or'.
+
+define i32 @rotr_select(i32 %x, i32 %shamt) {
+; CHECK-LABEL: @rotr_select(
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshr.i32(i32 [[X:%.*]], i32 [[X]], i32 [[SHAMT:%.*]])
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %cmp = icmp eq i32 %shamt, 0
+ %sub = sub i32 32, %shamt
+ %shr = lshr i32 %x, %shamt
+ %shl = shl i32 %x, %sub
+ %or = or i32 %shr, %shl
+ %r = select i1 %cmp, i32 %x, i32 %or
+ ret i32 %r
+}
+
+; Convert select pattern to masked shift that ends in 'or'.
+
+define i8 @rotr_select_commute(i8 %x, i8 %shamt) {
+; CHECK-LABEL: @rotr_select_commute(
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[X]], i8 [[SHAMT:%.*]])
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %cmp = icmp eq i8 %shamt, 0
+ %sub = sub i8 8, %shamt
+ %shr = lshr i8 %x, %shamt
+ %shl = shl i8 %x, %sub
+ %or = or i8 %shl, %shr
+ %r = select i1 %cmp, i8 %x, i8 %or
+ ret i8 %r
+}
+
+; Convert select pattern to masked shift that ends in 'or'.
+
+define i16 @rotl_select(i16 %x, i16 %shamt) {
+; CHECK-LABEL: @rotl_select(
+; CHECK-NEXT: [[R:%.*]] = call i16 @llvm.fshl.i16(i16 [[X:%.*]], i16 [[X]], i16 [[SHAMT:%.*]])
+; CHECK-NEXT: ret i16 [[R]]
+;
+ %cmp = icmp eq i16 %shamt, 0
+ %sub = sub i16 16, %shamt
+ %shr = lshr i16 %x, %sub
+ %shl = shl i16 %x, %shamt
+ %or = or i16 %shr, %shl
+ %r = select i1 %cmp, i16 %x, i16 %or
+ ret i16 %r
+}
+
+; Convert select pattern to masked shift that ends in 'or'.
+
+define <2 x i64> @rotl_select_commute(<2 x i64> %x, <2 x i64> %shamt) {
+; CHECK-LABEL: @rotl_select_commute(
+; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[X:%.*]], <2 x i64> [[X]], <2 x i64> [[SHAMT:%.*]])
+; CHECK-NEXT: ret <2 x i64> [[R]]
+;
+ %cmp = icmp eq <2 x i64> %shamt, zeroinitializer
+ %sub = sub <2 x i64> <i64 64, i64 64>, %shamt
+ %shr = lshr <2 x i64> %x, %sub
+ %shl = shl <2 x i64> %x, %shamt
+ %or = or <2 x i64> %shl, %shr
+ %r = select <2 x i1> %cmp, <2 x i64> %x, <2 x i64> %or
+ ret <2 x i64> %r
+}
+
+; Negative test - the transform is only valid with power-of-2 types.
+
+define i24 @rotl_select_weird_type(i24 %x, i24 %shamt) {
+; CHECK-LABEL: @rotl_select_weird_type(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i24 [[SHAMT:%.*]], 0
+; CHECK-NEXT: [[SUB:%.*]] = sub i24 24, [[SHAMT]]
+; CHECK-NEXT: [[SHR:%.*]] = lshr i24 [[X:%.*]], [[SUB]]
+; CHECK-NEXT: [[SHL:%.*]] = shl i24 [[X]], [[SHAMT]]
+; CHECK-NEXT: [[OR:%.*]] = or i24 [[SHL]], [[SHR]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i24 [[X]], i24 [[OR]]
+; CHECK-NEXT: ret i24 [[R]]
+;
+ %cmp = icmp eq i24 %shamt, 0
+ %sub = sub i24 24, %shamt
+ %shr = lshr i24 %x, %sub
+ %shl = shl i24 %x, %shamt
+ %or = or i24 %shl, %shr
+ %r = select i1 %cmp, i24 %x, i24 %or
+ ret i24 %r
+}
+
+; Test that the transform doesn't crash when there's an "or" with a ConstantExpr operand.
+
+ at external_global = external global i8
+
+define i32 @rotl_constant_expr(i32 %shamt) {
+; CHECK-LABEL: @rotl_constant_expr(
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 ptrtoint (i8* @external_global to i32), [[SHAMT:%.*]]
+; CHECK-NEXT: [[R:%.*]] = or i32 [[SHR]], shl (i32 ptrtoint (i8* @external_global to i32), i32 11)
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %shr = lshr i32 ptrtoint (i8* @external_global to i32), %shamt
+ %r = or i32 %shr, shl (i32 ptrtoint (i8* @external_global to i32), i32 11)
+ ret i32 %r
+}
Added: llvm/trunk/test/Transforms/InstCombine/round.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/round.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/round.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/round.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,90 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+declare float @llvm.round.f32(float) #0
+declare double @llvm.round.f64(double) #0
+
+; CHECK-LABEL: @constant_fold_round_f32_01
+; CHECK-NEXT: ret float 1.000000e+00
+define float @constant_fold_round_f32_01() #0 {
+ %x = call float @llvm.round.f32(float 1.25) #0
+ ret float %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f32_02
+; CHECK-NEXT: ret float -1.000000e+00
+define float @constant_fold_round_f32_02() #0 {
+ %x = call float @llvm.round.f32(float -1.25) #0
+ ret float %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f32_03
+; CHECK-NEXT: ret float 2.000000e+00
+define float @constant_fold_round_f32_03() #0 {
+ %x = call float @llvm.round.f32(float 1.5) #0
+ ret float %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f32_04
+; CHECK-NEXT: ret float -2.000000e+00
+define float @constant_fold_round_f32_04() #0 {
+ %x = call float @llvm.round.f32(float -1.5) #0
+ ret float %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f32_05
+; CHECK-NEXT: ret float 3.000000e+00
+define float @constant_fold_round_f32_05() #0 {
+ %x = call float @llvm.round.f32(float 2.75) #0
+ ret float %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f32_06
+; CHECK-NEXT: ret float -3.000000e+00
+define float @constant_fold_round_f32_06() #0 {
+ %x = call float @llvm.round.f32(float -2.75) #0
+ ret float %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f64_01
+; CHECK-NEXT: ret double 1.000000e+00
+define double @constant_fold_round_f64_01() #0 {
+ %x = call double @llvm.round.f64(double 1.3) #0
+ ret double %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f64_02
+; CHECK-NEXT: ret double -1.000000e+00
+define double @constant_fold_round_f64_02() #0 {
+ %x = call double @llvm.round.f64(double -1.3) #0
+ ret double %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f64_03
+; CHECK-NEXT: ret double 2.000000e+00
+define double @constant_fold_round_f64_03() #0 {
+ %x = call double @llvm.round.f64(double 1.5) #0
+ ret double %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f64_04
+; CHECK-NEXT: ret double -2.000000e+00
+define double @constant_fold_round_f64_04() #0 {
+ %x = call double @llvm.round.f64(double -1.5) #0
+ ret double %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f64_05
+; CHECK-NEXT: ret double 3.000000e+00
+define double @constant_fold_round_f64_05() #0 {
+ %x = call double @llvm.round.f64(double 2.7) #0
+ ret double %x
+}
+
+; CHECK-LABEL: @constant_fold_round_f64_06
+; CHECK-NEXT: ret double -3.000000e+00
+define double @constant_fold_round_f64_06() #0 {
+ %x = call double @llvm.round.f64(double -2.7) #0
+ ret double %x
+}
+
+attributes #0 = { nounwind readnone }
Added: llvm/trunk/test/Transforms/InstCombine/sadd-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sadd-with-overflow.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sadd-with-overflow.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sadd-with-overflow.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,124 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32>, <2 x i32>)
+
+declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
+
+declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8)
+
+define { i32, i1 } @simple_fold(i32 %x) {
+; CHECK-LABEL: @simple_fold(
+; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 20)
+; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+;
+ %a = add nsw i32 %x, 7
+ %b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 13)
+ ret { i32, i1 } %b
+}
+
+define { i32, i1 } @fold_mixed_signs(i32 %x) {
+; CHECK-LABEL: @fold_mixed_signs(
+; CHECK-NEXT: [[B:%.*]] = add nsw i32 [[X:%.*]], 6
+; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { i32, i1 } { i32 undef, i1 false }, i32 [[B]], 0
+; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+;
+ %a = add nsw i32 %x, 13
+ %b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 -7)
+ ret { i32, i1 } %b
+}
+
+define { i8, i1 } @fold_on_constant_add_no_overflow(i8 %x) {
+; CHECK-LABEL: @fold_on_constant_add_no_overflow(
+; CHECK-NEXT: [[TMP1:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X:%.*]], i8 127)
+; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
+;
+ %a = add nsw i8 %x, 100
+ %b = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %a, i8 27)
+ ret { i8, i1 } %b
+}
+
+define { i8, i1 } @no_fold_on_constant_add_overflow(i8 %x) {
+; CHECK-LABEL: @no_fold_on_constant_add_overflow(
+; CHECK-NEXT: [[A:%.*]] = add nsw i8 [[X:%.*]], 100
+; CHECK-NEXT: [[B:%.*]] = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A]], i8 28)
+; CHECK-NEXT: ret { i8, i1 } [[B]]
+;
+ %a = add nsw i8 %x, 100
+ %b = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %a, i8 28)
+ ret { i8, i1 } %b
+}
+
+define { <2 x i32>, <2 x i1> } @fold_simple_splat_constant(<2 x i32> %x) {
+; CHECK-LABEL: @fold_simple_splat_constant(
+; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 42, i32 42>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP1]]
+;
+ %a = add nsw <2 x i32> %x, <i32 12, i32 12>
+ %b = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
+ ret { <2 x i32>, <2 x i1> } %b
+}
+
+define { <2 x i32>, <2 x i1> } @no_fold_splat_undef_constant(<2 x i32> %x) {
+; CHECK-LABEL: @no_fold_splat_undef_constant(
+; CHECK-NEXT: [[A:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 12, i32 undef>
+; CHECK-NEXT: [[B:%.*]] = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[A]], <2 x i32> <i32 30, i32 30>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[B]]
+;
+ %a = add nsw <2 x i32> %x, <i32 12, i32 undef>
+ %b = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
+ ret { <2 x i32>, <2 x i1> } %b
+}
+
+define { <2 x i32>, <2 x i1> } @no_fold_splat_not_constant(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @no_fold_splat_not_constant(
+; CHECK-NEXT: [[A:%.*]] = add nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B:%.*]] = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[A]], <2 x i32> <i32 30, i32 30>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[B]]
+;
+ %a = add nsw <2 x i32> %x, %y
+ %b = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
+ ret { <2 x i32>, <2 x i1> } %b
+}
+
+define { i32, i1 } @fold_nuwnsw(i32 %x) {
+; CHECK-LABEL: @fold_nuwnsw(
+; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
+; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+;
+ %a = add nuw nsw i32 %x, 12
+ %b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 30)
+ ret { i32, i1 } %b
+}
+
+define { i32, i1 } @no_fold_nuw(i32 %x) {
+; CHECK-LABEL: @no_fold_nuw(
+; CHECK-NEXT: [[A:%.*]] = add nuw i32 [[X:%.*]], 12
+; CHECK-NEXT: [[B:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A]], i32 30)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
+;
+ %a = add nuw i32 %x, 12
+ %b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 30)
+ ret { i32, i1 } %b
+}
+
+define { i32, i1 } @no_fold_wrapped_add(i32 %x) {
+; CHECK-LABEL: @no_fold_wrapped_add(
+; CHECK-NEXT: [[A:%.*]] = add i32 [[X:%.*]], 12
+; CHECK-NEXT: [[B:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A]], i32 30)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
+;
+ %a = add i32 %x, 12
+ %b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 30, i32 %a)
+ ret { i32, i1 } %b
+}
+
+define { i32, i1 } @fold_sub_simple(i32 %x) {
+; CHECK-LABEL: @fold_sub_simple(
+; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
+; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+;
+ %a = sub nsw i32 %x, -12
+ %b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 30)
+ ret { i32, i1 } %b
+}
Added: llvm/trunk/test/Transforms/InstCombine/salvage-dbg-declare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/salvage-dbg-declare.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/salvage-dbg-declare.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/salvage-dbg-declare.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,49 @@
+; RUN: opt -instcombine -S -o - %s | FileCheck %s
+
+declare dso_local i32 @bar(i8*)
+
+; Function Attrs: nounwind
+define internal i32 @foo() #0 !dbg !1 {
+; CHECK: %[[VLA:.*]] = alloca [2 x i32]
+; CHECK: call void @llvm.dbg.declare(metadata [2 x i32]* %[[VLA]], {{.*}}, metadata !DIExpression())
+
+entry:
+ %vla = alloca i32, i64 2, align 4, !dbg !16
+ call void @llvm.dbg.declare(metadata i32* %vla, metadata !19, metadata !DIExpression()), !dbg !20
+ %0 = bitcast i32* %vla to i8*, !dbg !21
+ %call = call i32 @bar(i8* %0), !dbg !22
+ unreachable
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone speculatable }
+
+!llvm.dbg.cu = !{!5}
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DISubprogram(name: "a", scope: !2, file: !2, line: 232, type: !3, isLocal: true, isDefinition: true, scopeLine: 234, flags: DIFlagPrototyped, isOptimized: true, unit: !5, retainedNodes: !6)
+!2 = !DIFile(filename: "b", directory: "c")
+!3 = !DISubroutineType(types: !4)
+!4 = !{}
+!5 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, producer: "clang version", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4, globals: !4)
+!6 = !{!7, !11}
+!7 = !DILocalVariable(name: "__vla_expr", scope: !8, type: !10, flags: DIFlagArtificial)
+!8 = distinct !DILexicalBlock(scope: !9, file: !2, line: 238, column: 39)
+!9 = distinct !DILexicalBlock(scope: !1, file: !2, line: 238, column: 6)
+!10 = !DIBasicType(name: "long unsigned int", size: 64, encoding: DW_ATE_unsigned)
+!11 = !DILocalVariable(name: "ptr32", scope: !8, file: !2, line: 240, type: !12)
+!12 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, elements: !14)
+!13 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
+!14 = !{!15}
+!15 = !DISubrange(count: !7)
+!16 = !DILocation(line: 240, column: 3, scope: !17)
+!17 = distinct !DILexicalBlock(scope: !18, file: !2, line: 238, column: 39)
+!18 = distinct !DILexicalBlock(scope: !1, file: !2, line: 238, column: 6)
+!19 = !DILocalVariable(name: "ptr32", scope: !17, file: !2, line: 240, type: !12)
+!20 = !DILocation(line: 240, column: 12, scope: !17)
+!21 = !DILocation(line: 241, column: 65, scope: !17)
+!22 = !DILocation(line: 241, column: 11, scope: !17)
Added: llvm/trunk/test/Transforms/InstCombine/saturating-add-sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/saturating-add-sub.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/saturating-add-sub.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/saturating-add-sub.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1462 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+;
+; Saturating addition.
+;
+
+declare i8 @llvm.uadd.sat.i8(i8, i8)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
+
+; Constant uadd argument is canonicalized to the right.
+define i8 @test_scalar_uadd_canonical(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_canonical(
+; CHECK-NEXT: [[X:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[A:%.*]], i8 10)
+; CHECK-NEXT: ret i8 [[X]]
+;
+ %x = call i8 @llvm.uadd.sat.i8(i8 10, i8 %a)
+ ret i8 %x
+}
+
+define <2 x i8> @test_vector_uadd_canonical(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_canonical(
+; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 10, i8 20>)
+; CHECK-NEXT: ret <2 x i8> [[X]]
+;
+ %x = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> <i8 10, i8 20>, <2 x i8> %a)
+ ret <2 x i8> %x
+}
+
+; Constant sadd argument is canonicalized to the right.
+define i8 @test_scalar_sadd_canonical(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_canonical(
+; CHECK-NEXT: [[X:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 -10)
+; CHECK-NEXT: ret i8 [[X]]
+;
+ %x = call i8 @llvm.sadd.sat.i8(i8 -10, i8 %a)
+ ret i8 %x
+}
+
+define <2 x i8> @test_vector_sadd_canonical(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_sadd_canonical(
+; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 10, i8 -20>)
+; CHECK-NEXT: ret <2 x i8> [[X]]
+;
+ %x = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> <i8 10, i8 -20>, <2 x i8> %a)
+ ret <2 x i8> %x
+}
+
+; Can combine uadds with constant operands.
+define i8 @test_scalar_uadd_combine(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_combine(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[A:%.*]], i8 30)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %x1 = call i8 @llvm.uadd.sat.i8(i8 %a, i8 10)
+ %x2 = call i8 @llvm.uadd.sat.i8(i8 %x1, i8 20)
+ ret i8 %x2
+}
+
+define <2 x i8> @test_vector_uadd_combine(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_combine(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 30, i8 30>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %x1 = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 10>)
+ %x2 = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x1, <2 x i8> <i8 20, i8 20>)
+ ret <2 x i8> %x2
+}
+
+; This could simplify, but currently doesn't.
+define <2 x i8> @test_vector_uadd_combine_non_splat(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_combine_non_splat(
+; CHECK-NEXT: [[X1:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 10, i8 20>)
+; CHECK-NEXT: [[X2:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X1]], <2 x i8> <i8 30, i8 40>)
+; CHECK-NEXT: ret <2 x i8> [[X2]]
+;
+ %x1 = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 20>)
+ %x2 = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x1, <2 x i8> <i8 30, i8 40>)
+ ret <2 x i8> %x2
+}
+
+; Can combine uadds even if they overflow.
+define i8 @test_scalar_uadd_overflow(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_overflow(
+; CHECK-NEXT: ret i8 -1
+;
+ %y1 = call i8 @llvm.uadd.sat.i8(i8 %a, i8 100)
+ %y2 = call i8 @llvm.uadd.sat.i8(i8 %y1, i8 200)
+ ret i8 %y2
+}
+
+define <2 x i8> @test_vector_uadd_overflow(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_overflow(
+; CHECK-NEXT: ret <2 x i8> <i8 -1, i8 -1>
+;
+ %y1 = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 100, i8 100>)
+ %y2 = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %y1, <2 x i8> <i8 200, i8 200>)
+ ret <2 x i8> %y2
+}
+
+; Can combine sadds if sign matches.
+define i8 @test_scalar_sadd_both_positive(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_both_positive(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 30)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %z1 = call i8 @llvm.sadd.sat.i8(i8 %a, i8 10)
+ %z2 = call i8 @llvm.sadd.sat.i8(i8 %z1, i8 20)
+ ret i8 %z2
+}
+
+define <2 x i8> @test_vector_sadd_both_positive(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_sadd_both_positive(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 30, i8 30>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %z1 = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 10>)
+ %z2 = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %z1, <2 x i8> <i8 20, i8 20>)
+ ret <2 x i8> %z2
+}
+
+define i8 @test_scalar_sadd_both_negative(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_both_negative(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 -30)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %u1 = call i8 @llvm.sadd.sat.i8(i8 %a, i8 -10)
+ %u2 = call i8 @llvm.sadd.sat.i8(i8 %u1, i8 -20)
+ ret i8 %u2
+}
+
+define <2 x i8> @test_vector_sadd_both_negative(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_sadd_both_negative(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 -30, i8 -30>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %u1 = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 -10, i8 -10>)
+ %u2 = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %u1, <2 x i8> <i8 -20, i8 -20>)
+ ret <2 x i8> %u2
+}
+
+; Can't combine sadds if constants have different sign.
+define i8 @test_scalar_sadd_different_sign(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_different_sign(
+; CHECK-NEXT: [[V1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 10)
+; CHECK-NEXT: [[V2:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[V1]], i8 -20)
+; CHECK-NEXT: ret i8 [[V2]]
+;
+ %v1 = call i8 @llvm.sadd.sat.i8(i8 %a, i8 10)
+ %v2 = call i8 @llvm.sadd.sat.i8(i8 %v1, i8 -20)
+ ret i8 %v2
+}
+
+; Can't combine sadds if they overflow.
+define i8 @test_scalar_sadd_overflow(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_overflow(
+; CHECK-NEXT: [[W1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 100)
+; CHECK-NEXT: [[W2:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[W1]], i8 100)
+; CHECK-NEXT: ret i8 [[W2]]
+;
+ %w1 = call i8 @llvm.sadd.sat.i8(i8 %a, i8 100)
+ %w2 = call i8 @llvm.sadd.sat.i8(i8 %w1, i8 100)
+ ret i8 %w2
+}
+
+; neg uadd neg always overflows.
+define i8 @test_scalar_uadd_neg_neg(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_neg_neg(
+; CHECK-NEXT: ret i8 -1
+;
+ %a_neg = or i8 %a, -128
+ %r = call i8 @llvm.uadd.sat.i8(i8 %a_neg, i8 -10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_uadd_neg_neg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_neg_neg(
+; CHECK-NEXT: ret <2 x i8> <i8 -1, i8 -1>
+;
+ %a_neg = or <2 x i8> %a, <i8 -128, i8 -128>
+ %r = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a_neg, <2 x i8> <i8 -10, i8 -20>)
+ ret <2 x i8> %r
+}
+
+; nneg uadd nneg never overflows.
+define i8 @test_scalar_uadd_nneg_nneg(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_nneg_nneg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and i8 [[A:%.*]], 127
+; CHECK-NEXT: [[R:%.*]] = add nuw i8 [[A_NNEG]], 10
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_nneg = and i8 %a, 127
+ %r = call i8 @llvm.uadd.sat.i8(i8 %a_nneg, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_uadd_nneg_nneg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_nneg_nneg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and <2 x i8> [[A:%.*]], <i8 127, i8 127>
+; CHECK-NEXT: [[R:%.*]] = add nuw <2 x i8> [[A_NNEG]], <i8 10, i8 20>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_nneg = and <2 x i8> %a, <i8 127, i8 127>
+ %r = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a_nneg, <2 x i8> <i8 10, i8 20>)
+ ret <2 x i8> %r
+}
+
+; neg uadd nneg might overflow.
+define i8 @test_scalar_uadd_neg_nneg(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or i8 [[A:%.*]], -128
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[A_NEG]], i8 10)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_neg = or i8 %a, -128
+ %r = call i8 @llvm.uadd.sat.i8(i8 %a_neg, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_uadd_neg_nneg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or <2 x i8> [[A:%.*]], <i8 -128, i8 -128>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[A_NEG]], <2 x i8> <i8 10, i8 20>)
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_neg = or <2 x i8> %a, <i8 -128, i8 -128>
+ %r = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a_neg, <2 x i8> <i8 10, i8 20>)
+ ret <2 x i8> %r
+}
+
+define i8 @test_scalar_uadd_never_overflows(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_never_overflows(
+; CHECK-NEXT: [[A_MASKED:%.*]] = and i8 [[A:%.*]], -127
+; CHECK-NEXT: [[R:%.*]] = add nuw nsw i8 [[A_MASKED]], 1
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_masked = and i8 %a, 129
+ %r = call i8 @llvm.uadd.sat.i8(i8 %a_masked, i8 1)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_uadd_never_overflows(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_never_overflows(
+; CHECK-NEXT: [[A_MASKED:%.*]] = and <2 x i8> [[A:%.*]], <i8 -127, i8 -127>
+; CHECK-NEXT: [[R:%.*]] = add nuw nsw <2 x i8> [[A_MASKED]], <i8 1, i8 1>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_masked = and <2 x i8> %a, <i8 129, i8 129>
+ %r = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a_masked, <2 x i8> <i8 1, i8 1>)
+ ret <2 x i8> %r
+}
+
+define i8 @test_scalar_uadd_always_overflows(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_always_overflows(
+; CHECK-NEXT: ret i8 -1
+;
+ %a_masked = or i8 %a, 192
+ %r = call i8 @llvm.uadd.sat.i8(i8 %a_masked, i8 64)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_uadd_always_overflows(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_uadd_always_overflows(
+; CHECK-NEXT: ret <2 x i8> <i8 -1, i8 -1>
+;
+ %a_masked = or <2 x i8> %a, <i8 192, i8 192>
+ %r = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %a_masked, <2 x i8> <i8 64, i8 64>)
+ ret <2 x i8> %r
+}
+
+; neg sadd nneg never overflows.
+define i8 @test_scalar_sadd_neg_nneg(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or i8 [[A:%.*]], -128
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[A_NEG]], 10
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_neg = or i8 %a, -128
+ %r = call i8 @llvm.sadd.sat.i8(i8 %a_neg, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_sadd_neg_nneg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_sadd_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or <2 x i8> [[A:%.*]], <i8 -128, i8 -128>
+; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i8> [[A_NEG]], <i8 10, i8 20>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_neg = or <2 x i8> %a, <i8 -128, i8 -128>
+ %r = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %a_neg, <2 x i8> <i8 10, i8 20>)
+ ret <2 x i8> %r
+}
+
+; nneg sadd neg never overflows.
+define i8 @test_scalar_sadd_nneg_neg(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_nneg_neg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and i8 [[A:%.*]], 127
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[A_NNEG]], -10
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_nneg = and i8 %a, 127
+ %r = call i8 @llvm.sadd.sat.i8(i8 %a_nneg, i8 -10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_sadd_nneg_neg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_sadd_nneg_neg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and <2 x i8> [[A:%.*]], <i8 127, i8 127>
+; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i8> [[A_NNEG]], <i8 -10, i8 -20>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_nneg = and <2 x i8> %a, <i8 127, i8 127>
+ %r = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %a_nneg, <2 x i8> <i8 -10, i8 -20>)
+ ret <2 x i8> %r
+}
+
+; neg sadd neg might overflow.
+define i8 @test_scalar_sadd_neg_neg(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_neg_neg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or i8 [[A:%.*]], -128
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A_NEG]], i8 -10)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_neg = or i8 %a, -128
+ %r = call i8 @llvm.sadd.sat.i8(i8 %a_neg, i8 -10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_sadd_neg_neg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_sadd_neg_neg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or <2 x i8> [[A:%.*]], <i8 -128, i8 -128>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A_NEG]], <2 x i8> <i8 -10, i8 -20>)
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_neg = or <2 x i8> %a, <i8 -128, i8 -128>
+ %r = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %a_neg, <2 x i8> <i8 -10, i8 -20>)
+ ret <2 x i8> %r
+}
+
+; While this is a no-overflow condition, the nuw flag gets lost due to
+; canonicalization and we can no longer determine this
+define i8 @test_scalar_uadd_sub_nuw_lost_no_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_sub_nuw_lost_no_ov(
+; CHECK-NEXT: [[B:%.*]] = add i8 [[A:%.*]], -10
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[B]], i8 9)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = sub nuw i8 %a, 10
+ %r = call i8 @llvm.uadd.sat.i8(i8 %b, i8 9)
+ ret i8 %r
+}
+
+define i8 @test_scalar_uadd_urem_no_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_urem_no_ov(
+; CHECK-NEXT: [[B:%.*]] = urem i8 [[A:%.*]], 100
+; CHECK-NEXT: [[R:%.*]] = add nuw nsw i8 [[B]], -100
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = urem i8 %a, 100
+ %r = call i8 @llvm.uadd.sat.i8(i8 %b, i8 156)
+ ret i8 %r
+}
+
+define i8 @test_scalar_uadd_urem_may_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_uadd_urem_may_ov(
+; CHECK-NEXT: [[B:%.*]] = urem i8 [[A:%.*]], 100
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[B]], i8 -99)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = urem i8 %a, 100
+ %r = call i8 @llvm.uadd.sat.i8(i8 %b, i8 157)
+ ret i8 %r
+}
+
+; We have a constant range for the LHS, but only known bits for the RHS
+define i8 @test_scalar_uadd_udiv_known_bits(i8 %a, i8 %b) {
+; CHECK-LABEL: @test_scalar_uadd_udiv_known_bits(
+; CHECK-NEXT: [[AA:%.*]] = udiv i8 -66, [[A:%.*]]
+; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 63
+; CHECK-NEXT: [[R:%.*]] = add nuw i8 [[AA]], [[BB]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %aa = udiv i8 190, %a
+ %bb = and i8 %b, 63
+ %r = call i8 @llvm.uadd.sat.i8(i8 %aa, i8 %bb)
+ ret i8 %r
+}
+
+define i8 @test_scalar_sadd_srem_no_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_srem_no_ov(
+; CHECK-NEXT: [[B:%.*]] = srem i8 [[A:%.*]], 100
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[B]], 28
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = srem i8 %a, 100
+ %r = call i8 @llvm.sadd.sat.i8(i8 %b, i8 28)
+ ret i8 %r
+}
+
+define i8 @test_scalar_sadd_srem_may_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_srem_may_ov(
+; CHECK-NEXT: [[B:%.*]] = srem i8 [[A:%.*]], 100
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[B]], i8 29)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = srem i8 %a, 100
+ %r = call i8 @llvm.sadd.sat.i8(i8 %b, i8 29)
+ ret i8 %r
+}
+
+define i8 @test_scalar_sadd_srem_and_no_ov(i8 %a, i8 %b) {
+; CHECK-LABEL: @test_scalar_sadd_srem_and_no_ov(
+; CHECK-NEXT: [[AA:%.*]] = srem i8 [[A:%.*]], 100
+; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 15
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[AA]], [[BB]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %aa = srem i8 %a, 100
+ %bb = and i8 %b, 15
+ %r = call i8 @llvm.sadd.sat.i8(i8 %aa, i8 %bb)
+ ret i8 %r
+}
+
+;
+; Saturating subtraction.
+;
+
+declare i8 @llvm.usub.sat.i8(i8, i8)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>)
+declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
+
+; Cannot canonicalize usub to uadd.
+define i8 @test_scalar_usub_canonical(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_canonical(
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[A:%.*]], i8 10)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %r = call i8 @llvm.usub.sat.i8(i8 %a, i8 10)
+ ret i8 %r
+}
+
+; Canonicalize ssub to sadd.
+define i8 @test_scalar_ssub_canonical(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_canonical(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 -10)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %r = call i8 @llvm.ssub.sat.i8(i8 %a, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_ssub_canonical(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_canonical(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 -10, i8 -10>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 10>)
+ ret <2 x i8> %r
+}
+
+define <2 x i8> @test_vector_ssub_canonical_min_non_splat(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_canonical_min_non_splat(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 -10, i8 10>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 -10>)
+ ret <2 x i8> %r
+}
+
+; Cannot canonicalize signed min.
+define i8 @test_scalar_ssub_canonical_min(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_canonical_min(
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.ssub.sat.i8(i8 [[A:%.*]], i8 -128)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %r = call i8 @llvm.ssub.sat.i8(i8 %a, i8 -128)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_ssub_canonical_min(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_canonical_min(
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 -128, i8 -10>)
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 -128, i8 -10>)
+ ret <2 x i8> %r
+}
+
+; Can combine usubs with constant operands.
+define i8 @test_scalar_usub_combine(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_combine(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[A:%.*]], i8 30)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %x1 = call i8 @llvm.usub.sat.i8(i8 %a, i8 10)
+ %x2 = call i8 @llvm.usub.sat.i8(i8 %x1, i8 20)
+ ret i8 %x2
+}
+
+define <2 x i8> @test_vector_usub_combine(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_combine(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 30, i8 30>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %x1 = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 10>)
+ %x2 = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x1, <2 x i8> <i8 20, i8 20>)
+ ret <2 x i8> %x2
+}
+
+; This could simplify, but currently doesn't.
+define <2 x i8> @test_vector_usub_combine_non_splat(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_combine_non_splat(
+; CHECK-NEXT: [[X1:%.*]] = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 10, i8 20>)
+; CHECK-NEXT: [[X2:%.*]] = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> [[X1]], <2 x i8> <i8 30, i8 40>)
+; CHECK-NEXT: ret <2 x i8> [[X2]]
+;
+ %x1 = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 20>)
+ %x2 = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x1, <2 x i8> <i8 30, i8 40>)
+ ret <2 x i8> %x2
+}
+
+; Can combine usubs even if they overflow.
+define i8 @test_scalar_usub_overflow(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_overflow(
+; CHECK-NEXT: ret i8 0
+;
+ %y1 = call i8 @llvm.usub.sat.i8(i8 %a, i8 100)
+ %y2 = call i8 @llvm.usub.sat.i8(i8 %y1, i8 200)
+ ret i8 %y2
+}
+
+define <2 x i8> @test_vector_usub_overflow(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_overflow(
+; CHECK-NEXT: ret <2 x i8> zeroinitializer
+;
+ %y1 = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 100, i8 100>)
+ %y2 = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %y1, <2 x i8> <i8 200, i8 200>)
+ ret <2 x i8> %y2
+}
+
+; Can combine ssubs if sign matches.
+define i8 @test_scalar_ssub_both_positive(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_both_positive(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 -30)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %z1 = call i8 @llvm.ssub.sat.i8(i8 %a, i8 10)
+ %z2 = call i8 @llvm.ssub.sat.i8(i8 %z1, i8 20)
+ ret i8 %z2
+}
+
+define <2 x i8> @test_vector_ssub_both_positive(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_both_positive(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 -30, i8 -30>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %z1 = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 10, i8 10>)
+ %z2 = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %z1, <2 x i8> <i8 20, i8 20>)
+ ret <2 x i8> %z2
+}
+
+define i8 @test_scalar_ssub_both_negative(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_both_negative(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 30)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %u1 = call i8 @llvm.ssub.sat.i8(i8 %a, i8 -10)
+ %u2 = call i8 @llvm.ssub.sat.i8(i8 %u1, i8 -20)
+ ret i8 %u2
+}
+
+define <2 x i8> @test_vector_ssub_both_negative(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_both_negative(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 30, i8 30>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %u1 = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a, <2 x i8> <i8 -10, i8 -10>)
+ %u2 = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %u1, <2 x i8> <i8 -20, i8 -20>)
+ ret <2 x i8> %u2
+}
+
+; Can't combine ssubs if constants have different sign.
+define i8 @test_scalar_ssub_different_sign(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_different_sign(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 -10)
+; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[TMP1]], i8 20)
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+ %v1 = call i8 @llvm.ssub.sat.i8(i8 %a, i8 10)
+ %v2 = call i8 @llvm.ssub.sat.i8(i8 %v1, i8 -20)
+ ret i8 %v2
+}
+
+; Can combine sadd and ssub with appropriate signs.
+define i8 @test_scalar_sadd_ssub(i8 %a) {
+; CHECK-LABEL: @test_scalar_sadd_ssub(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 30)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %v1 = call i8 @llvm.sadd.sat.i8(i8 10, i8 %a)
+ %v2 = call i8 @llvm.ssub.sat.i8(i8 %v1, i8 -20)
+ ret i8 %v2
+}
+
+define <2 x i8> @test_vector_sadd_ssub(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_sadd_ssub(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A:%.*]], <2 x i8> <i8 -30, i8 -30>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %v1 = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> <i8 -10, i8 -10>, <2 x i8> %a)
+ %v2 = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %v1, <2 x i8> <i8 20, i8 20>)
+ ret <2 x i8> %v2
+}
+
+; Can't combine ssubs if they overflow.
+define i8 @test_scalar_ssub_overflow(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_overflow(
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A:%.*]], i8 -100)
+; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[TMP1]], i8 -100)
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+ %w1 = call i8 @llvm.ssub.sat.i8(i8 %a, i8 100)
+ %w2 = call i8 @llvm.ssub.sat.i8(i8 %w1, i8 100)
+ ret i8 %w2
+}
+
+; nneg usub neg always overflows.
+define i8 @test_scalar_usub_nneg_neg(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_nneg_neg(
+; CHECK-NEXT: ret i8 0
+;
+ %a_nneg = and i8 %a, 127
+ %r = call i8 @llvm.usub.sat.i8(i8 %a_nneg, i8 -10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_usub_nneg_neg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_nneg_neg(
+; CHECK-NEXT: ret <2 x i8> zeroinitializer
+;
+ %a_nneg = and <2 x i8> %a, <i8 127, i8 127>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a_nneg, <2 x i8> <i8 -10, i8 -20>)
+ ret <2 x i8> %r
+}
+
+; neg usub nneg never overflows.
+define i8 @test_scalar_usub_neg_nneg(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or i8 [[A:%.*]], -128
+; CHECK-NEXT: [[R:%.*]] = add i8 [[A_NEG]], -10
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_neg = or i8 %a, -128
+ %r = call i8 @llvm.usub.sat.i8(i8 %a_neg, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_usub_neg_nneg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or <2 x i8> [[A:%.*]], <i8 -128, i8 -128>
+; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[A_NEG]], <i8 -10, i8 -20>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_neg = or <2 x i8> %a, <i8 -128, i8 -128>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a_neg, <2 x i8> <i8 10, i8 20>)
+ ret <2 x i8> %r
+}
+
+; nneg usub nneg never may overflow.
+define i8 @test_scalar_usub_nneg_nneg(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_nneg_nneg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and i8 [[A:%.*]], 127
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[A_NNEG]], i8 10)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_nneg = and i8 %a, 127
+ %r = call i8 @llvm.usub.sat.i8(i8 %a_nneg, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_usub_nneg_nneg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_nneg_nneg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and <2 x i8> [[A:%.*]], <i8 127, i8 127>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> [[A_NNEG]], <2 x i8> <i8 10, i8 20>)
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_nneg = and <2 x i8> %a, <i8 127, i8 127>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a_nneg, <2 x i8> <i8 10, i8 20>)
+ ret <2 x i8> %r
+}
+
+define i8 @test_scalar_usub_never_overflows(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_never_overflows(
+; CHECK-NEXT: [[A_MASKED:%.*]] = or i8 [[A:%.*]], 64
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[A_MASKED]], -10
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_masked = or i8 %a, 64
+ %r = call i8 @llvm.usub.sat.i8(i8 %a_masked, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_usub_never_overflows(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_never_overflows(
+; CHECK-NEXT: [[A_MASKED:%.*]] = or <2 x i8> [[A:%.*]], <i8 64, i8 64>
+; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i8> [[A_MASKED]], <i8 -10, i8 -10>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_masked = or <2 x i8> %a, <i8 64, i8 64>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a_masked, <2 x i8> <i8 10, i8 10>)
+ ret <2 x i8> %r
+}
+
+define i8 @test_scalar_usub_always_overflows(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_always_overflows(
+; CHECK-NEXT: ret i8 0
+;
+ %a_masked = and i8 %a, 64
+ %r = call i8 @llvm.usub.sat.i8(i8 %a_masked, i8 100)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_usub_always_overflows(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_always_overflows(
+; CHECK-NEXT: ret <2 x i8> zeroinitializer
+;
+ %a_masked = and <2 x i8> %a, <i8 64, i8 64>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %a_masked, <2 x i8> <i8 100, i8 100>)
+ ret <2 x i8> %r
+}
+
+; neg ssub neg never overflows.
+define i8 @test_scalar_ssub_neg_neg(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_neg_neg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or i8 [[A:%.*]], -128
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[A_NEG]], 10
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_neg = or i8 %a, -128
+ %r = call i8 @llvm.ssub.sat.i8(i8 %a_neg, i8 -10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_ssub_neg_neg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_neg_neg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or <2 x i8> [[A:%.*]], <i8 -128, i8 -128>
+; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i8> [[A_NEG]], <i8 10, i8 20>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_neg = or <2 x i8> %a, <i8 -128, i8 -128>
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a_neg, <2 x i8> <i8 -10, i8 -20>)
+ ret <2 x i8> %r
+}
+
+; nneg ssub nneg never overflows.
+define i8 @test_scalar_ssub_nneg_nneg(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_nneg_nneg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and i8 [[A:%.*]], 127
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[A_NNEG]], -10
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a_nneg = and i8 %a, 127
+ %r = call i8 @llvm.ssub.sat.i8(i8 %a_nneg, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_ssub_nneg_nneg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_nneg_nneg(
+; CHECK-NEXT: [[A_NNEG:%.*]] = and <2 x i8> [[A:%.*]], <i8 127, i8 127>
+; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i8> [[A_NNEG]], <i8 -10, i8 -20>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %a_nneg = and <2 x i8> %a, <i8 127, i8 127>
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a_nneg, <2 x i8> <i8 10, i8 20>)
+ ret <2 x i8> %r
+}
+
+; neg ssub nneg may overflow.
+define i8 @test_scalar_ssub_neg_nneg(i8 %a) {
+; CHECK-LABEL: @test_scalar_ssub_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or i8 [[A:%.*]], -128
+; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[A_NEG]], i8 -10)
+; CHECK-NEXT: ret i8 [[TMP1]]
+;
+ %a_neg = or i8 %a, -128
+ %r = call i8 @llvm.ssub.sat.i8(i8 %a_neg, i8 10)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_ssub_neg_nneg(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_ssub_neg_nneg(
+; CHECK-NEXT: [[A_NEG:%.*]] = or <2 x i8> [[A:%.*]], <i8 -128, i8 -128>
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[A_NEG]], <2 x i8> <i8 -10, i8 -20>)
+; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+;
+ %a_neg = or <2 x i8> %a, <i8 -128, i8 -128>
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %a_neg, <2 x i8> <i8 10, i8 20>)
+ ret <2 x i8> %r
+}
+
+define i8 @test_scalar_usub_add_nuw_no_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_add_nuw_no_ov(
+; CHECK-NEXT: [[R:%.*]] = add i8 [[A:%.*]], 1
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = add nuw i8 %a, 10
+ %r = call i8 @llvm.usub.sat.i8(i8 %b, i8 9)
+ ret i8 %r
+}
+
+define i8 @test_scalar_usub_add_nuw_eq(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_add_nuw_eq(
+; CHECK-NEXT: ret i8 [[A:%.*]]
+;
+ %b = add nuw i8 %a, 10
+ %r = call i8 @llvm.usub.sat.i8(i8 %b, i8 10)
+ ret i8 %r
+}
+
+define i8 @test_scalar_usub_add_nuw_may_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_add_nuw_may_ov(
+; CHECK-NEXT: [[B:%.*]] = add nuw i8 [[A:%.*]], 10
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[B]], i8 11)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = add nuw i8 %a, 10
+ %r = call i8 @llvm.usub.sat.i8(i8 %b, i8 11)
+ ret i8 %r
+}
+
+define i8 @test_scalar_usub_urem_must_ov(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_urem_must_ov(
+; CHECK-NEXT: ret i8 0
+;
+ %b = urem i8 %a, 10
+ %r = call i8 @llvm.usub.sat.i8(i8 %b, i8 10)
+ ret i8 %r
+}
+
+; Like the previous case, the result is always zero here. However, as there's
+; no actual overflow, we won't know about it.
+define i8 @test_scalar_usub_urem_must_zero(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_urem_must_zero(
+; CHECK-NEXT: [[B:%.*]] = urem i8 [[A:%.*]], 10
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[B]], i8 9)
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = urem i8 %a, 10
+ %r = call i8 @llvm.usub.sat.i8(i8 %b, i8 9)
+ ret i8 %r
+}
+
+; We have a constant range for the LHS, but only known bits for the RHS
+define i8 @test_scalar_usub_add_nuw_known_bits(i8 %a, i8 %b) {
+; CHECK-LABEL: @test_scalar_usub_add_nuw_known_bits(
+; CHECK-NEXT: [[AA:%.*]] = add nuw i8 [[A:%.*]], 10
+; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 7
+; CHECK-NEXT: [[R:%.*]] = sub nuw i8 [[AA]], [[BB]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %aa = add nuw i8 %a, 10
+ %bb = and i8 %b, 7
+ %r = call i8 @llvm.usub.sat.i8(i8 %aa, i8 %bb)
+ ret i8 %r
+}
+
+define i8 @test_scalar_usub_add_nuw_inferred(i8 %a) {
+; CHECK-LABEL: @test_scalar_usub_add_nuw_inferred(
+; CHECK-NEXT: [[B:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[A:%.*]], i8 10)
+; CHECK-NEXT: [[R:%.*]] = add nuw i8 [[B]], 9
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = call i8 @llvm.usub.sat.i8(i8 %a, i8 10)
+ %r = add i8 %b, 9
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_usub_add_nuw_no_ov(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_add_nuw_no_ov(
+; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[A:%.*]], <i8 1, i8 1>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %b = add nuw <2 x i8> %a, <i8 10, i8 10>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %b, <2 x i8> <i8 9, i8 9>)
+ ret <2 x i8> %r
+}
+
+; Can be optimized if the usub.sat RHS constant range handles non-splat vectors.
+define <2 x i8> @test_vector_usub_add_nuw_no_ov_nonsplat1(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_add_nuw_no_ov_nonsplat1(
+; CHECK-NEXT: [[B:%.*]] = add nuw <2 x i8> [[A:%.*]], <i8 10, i8 10>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> [[B]], <2 x i8> <i8 10, i8 9>)
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %b = add nuw <2 x i8> %a, <i8 10, i8 10>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %b, <2 x i8> <i8 10, i8 9>)
+ ret <2 x i8> %r
+}
+
+; Can be optimized if the add nuw RHS constant range handles non-splat vectors.
+define <2 x i8> @test_vector_usub_add_nuw_no_ov_nonsplat2(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_add_nuw_no_ov_nonsplat2(
+; CHECK-NEXT: [[B:%.*]] = add nuw <2 x i8> [[A:%.*]], <i8 10, i8 9>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> [[B]], <2 x i8> <i8 9, i8 9>)
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %b = add nuw <2 x i8> %a, <i8 10, i8 9>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %b, <2 x i8> <i8 9, i8 9>)
+ ret <2 x i8> %r
+}
+
+; Can be optimized if constant range is tracked per-element.
+define <2 x i8> @test_vector_usub_add_nuw_no_ov_nonsplat3(<2 x i8> %a) {
+; CHECK-LABEL: @test_vector_usub_add_nuw_no_ov_nonsplat3(
+; CHECK-NEXT: [[B:%.*]] = add nuw <2 x i8> [[A:%.*]], <i8 10, i8 9>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> [[B]], <2 x i8> <i8 10, i8 9>)
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %b = add nuw <2 x i8> %a, <i8 10, i8 9>
+ %r = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %b, <2 x i8> <i8 10, i8 9>)
+ ret <2 x i8> %r
+}
+
+define i8 @test_scalar_ssub_add_nsw_no_ov(i8 %a, i8 %b) {
+; CHECK-LABEL: @test_scalar_ssub_add_nsw_no_ov(
+; CHECK-NEXT: [[AA:%.*]] = add nsw i8 [[A:%.*]], 7
+; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 7
+; CHECK-NEXT: [[R:%.*]] = sub nsw i8 [[AA]], [[BB]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %aa = add nsw i8 %a, 7
+ %bb = and i8 %b, 7
+ %r = call i8 @llvm.ssub.sat.i8(i8 %aa, i8 %bb)
+ ret i8 %r
+}
+
+define i8 @test_scalar_ssub_add_nsw_may_ov(i8 %a, i8 %b) {
+; CHECK-LABEL: @test_scalar_ssub_add_nsw_may_ov(
+; CHECK-NEXT: [[AA:%.*]] = add nsw i8 [[A:%.*]], 6
+; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 7
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.ssub.sat.i8(i8 [[AA]], i8 [[BB]])
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %aa = add nsw i8 %a, 6
+ %bb = and i8 %b, 7
+ %r = call i8 @llvm.ssub.sat.i8(i8 %aa, i8 %bb)
+ ret i8 %r
+}
+
+define <2 x i8> @test_vector_ssub_add_nsw_no_ov_splat(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_splat(
+; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 7>
+; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 7>
+; CHECK-NEXT: [[R:%.*]] = sub nsw <2 x i8> [[AA]], [[BB]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %aa = add nsw <2 x i8> %a, <i8 7, i8 7>
+ %bb = and <2 x i8> %b, <i8 7, i8 7>
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
+ ret <2 x i8> %r
+}
+
+define <2 x i8> @test_vector_ssub_add_nsw_no_ov_nonsplat1(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_nonsplat1(
+; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 7>
+; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 6>
+; CHECK-NEXT: [[R:%.*]] = sub nsw <2 x i8> [[AA]], [[BB]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %aa = add nsw <2 x i8> %a, <i8 7, i8 7>
+ %bb = and <2 x i8> %b, <i8 7, i8 6>
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
+ ret <2 x i8> %r
+}
+
+define <2 x i8> @test_vector_ssub_add_nsw_no_ov_nonsplat2(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_nonsplat2(
+; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 8>
+; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 7>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> [[AA]], <2 x i8> [[BB]])
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %aa = add nsw <2 x i8> %a, <i8 7, i8 8>
+ %bb = and <2 x i8> %b, <i8 7, i8 7>
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
+ ret <2 x i8> %r
+}
+
+define <2 x i8> @test_vector_ssub_add_nsw_no_ov_nonsplat3(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_nonsplat3(
+; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 6>
+; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 6>
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> [[AA]], <2 x i8> [[BB]])
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %aa = add nsw <2 x i8> %a, <i8 7, i8 6>
+ %bb = and <2 x i8> %b, <i8 7, i8 6>
+ %r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
+ ret <2 x i8> %r
+}
+
+; Raw IR tests
+
+define i32 @uadd_sat(i32 %x, i32 %y) {
+; CHECK-LABEL: @uadd_sat(
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %notx = xor i32 %x, -1
+ %a = add i32 %y, %x
+ %c = icmp ult i32 %notx, %y
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define i32 @uadd_sat_commute_add(i32 %xp, i32 %y) {
+; CHECK-LABEL: @uadd_sat_commute_add(
+; CHECK-NEXT: [[X:%.*]] = urem i32 42, [[XP:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %x = urem i32 42, %xp ; thwart complexity-based-canonicalization
+ %notx = xor i32 %x, -1
+ %a = add i32 %x, %y
+ %c = icmp ult i32 %notx, %y
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define i32 @uadd_sat_ugt(i32 %x, i32 %yp) {
+; CHECK-LABEL: @uadd_sat_ugt(
+; CHECK-NEXT: [[Y:%.*]] = sdiv i32 [[YP:%.*]], 2442
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %y = sdiv i32 %yp, 2442 ; thwart complexity-based-canonicalization
+ %notx = xor i32 %x, -1
+ %a = add i32 %y, %x
+ %c = icmp ugt i32 %y, %notx
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define <2 x i32> @uadd_sat_ugt_commute_add(<2 x i32> %xp, <2 x i32> %yp) {
+; CHECK-LABEL: @uadd_sat_ugt_commute_add(
+; CHECK-NEXT: [[Y:%.*]] = sdiv <2 x i32> [[YP:%.*]], <i32 2442, i32 4242>
+; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> <i32 42, i32 43>, [[XP:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %y = sdiv <2 x i32> %yp, <i32 2442, i32 4242> ; thwart complexity-based-canonicalization
+ %x = srem <2 x i32> <i32 42, i32 43>, %xp ; thwart complexity-based-canonicalization
+ %notx = xor <2 x i32> %x, <i32 -1, i32 -1>
+ %a = add <2 x i32> %x, %y
+ %c = icmp ugt <2 x i32> %y, %notx
+ %r = select <2 x i1> %c, <2 x i32> <i32 -1, i32 -1>, <2 x i32> %a
+ ret <2 x i32> %r
+}
+
+define i32 @uadd_sat_commute_select(i32 %x, i32 %yp) {
+; CHECK-LABEL: @uadd_sat_commute_select(
+; CHECK-NEXT: [[Y:%.*]] = sdiv i32 [[YP:%.*]], 2442
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %y = sdiv i32 %yp, 2442 ; thwart complexity-based-canonicalization
+ %notx = xor i32 %x, -1
+ %a = add i32 %y, %x
+ %c = icmp ult i32 %y, %notx
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+define i32 @uadd_sat_commute_select_commute_add(i32 %xp, i32 %yp) {
+; CHECK-LABEL: @uadd_sat_commute_select_commute_add(
+; CHECK-NEXT: [[X:%.*]] = urem i32 42, [[XP:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = sdiv i32 [[YP:%.*]], 2442
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %x = urem i32 42, %xp ; thwart complexity-based-canonicalization
+ %y = sdiv i32 %yp, 2442 ; thwart complexity-based-canonicalization
+ %notx = xor i32 %x, -1
+ %a = add i32 %x, %y
+ %c = icmp ult i32 %y, %notx
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+define <2 x i32> @uadd_sat_commute_select_ugt(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @uadd_sat_commute_select_ugt(
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %notx = xor <2 x i32> %x, <i32 -1, i32 -1>
+ %a = add <2 x i32> %y, %x
+ %c = icmp ugt <2 x i32> %notx, %y
+ %r = select <2 x i1> %c, <2 x i32> %a, <2 x i32> <i32 -1, i32 -1>
+ ret <2 x i32> %r
+}
+
+define i32 @uadd_sat_commute_select_ugt_commute_add(i32 %xp, i32 %y) {
+; CHECK-LABEL: @uadd_sat_commute_select_ugt_commute_add(
+; CHECK-NEXT: [[X:%.*]] = srem i32 42, [[XP:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %x = srem i32 42, %xp ; thwart complexity-based-canonicalization
+ %notx = xor i32 %x, -1
+ %a = add i32 %x, %y
+ %c = icmp ugt i32 %notx, %y
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+; Negative test - make sure we have a -1 in the select.
+
+define i32 @not_uadd_sat(i32 %x, i32 %y) {
+; CHECK-LABEL: @not_uadd_sat(
+; CHECK-NEXT: [[A:%.*]] = add i32 [[X:%.*]], -2
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X]], 1
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %a = add i32 %x, -2
+ %c = icmp ugt i32 %x, 1
+ %r = select i1 %c, i32 %a, i32 %y
+ ret i32 %r
+}
+
+; Negative test - make sure the predicate is 'ult'.
+
+define i32 @not_uadd_sat2(i32 %x, i32 %y) {
+; CHECK-LABEL: @not_uadd_sat2(
+; CHECK-NEXT: [[A:%.*]] = add i32 [[X:%.*]], -2
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X]], 1
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A]], i32 -1
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %a = add i32 %x, -2
+ %c = icmp ugt i32 %x, 1
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+; The add may include a 'not' op rather than the cmp.
+
+define i32 @uadd_sat_not(i32 %x, i32 %y) {
+; CHECK-LABEL: @uadd_sat_not(
+; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[NOTX]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %notx = xor i32 %x, -1
+ %a = add i32 %notx, %y
+ %c = icmp ult i32 %x, %y
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define i32 @uadd_sat_not_commute_add(i32 %xp, i32 %yp) {
+; CHECK-LABEL: @uadd_sat_not_commute_add(
+; CHECK-NEXT: [[X:%.*]] = srem i32 42, [[XP:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = urem i32 42, [[YP:%.*]]
+; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[Y]], i32 [[NOTX]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %x = srem i32 42, %xp ; thwart complexity-based-canonicalization
+ %y = urem i32 42, %yp ; thwart complexity-based-canonicalization
+ %notx = xor i32 %x, -1
+ %a = add i32 %y, %notx
+ %c = icmp ult i32 %x, %y
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define i32 @uadd_sat_not_ugt(i32 %x, i32 %y) {
+; CHECK-LABEL: @uadd_sat_not_ugt(
+; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[NOTX]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %notx = xor i32 %x, -1
+ %a = add i32 %notx, %y
+ %c = icmp ugt i32 %y, %x
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define <2 x i32> @uadd_sat_not_ugt_commute_add(<2 x i32> %x, <2 x i32> %yp) {
+; CHECK-LABEL: @uadd_sat_not_ugt_commute_add(
+; CHECK-NEXT: [[Y:%.*]] = sdiv <2 x i32> [[YP:%.*]], <i32 2442, i32 4242>
+; CHECK-NEXT: [[NOTX:%.*]] = xor <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[Y]], <2 x i32> [[NOTX]])
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %y = sdiv <2 x i32> %yp, <i32 2442, i32 4242> ; thwart complexity-based-canonicalization
+ %notx = xor <2 x i32> %x, <i32 -1, i32 -1>
+ %a = add <2 x i32> %y, %notx
+ %c = icmp ugt <2 x i32> %y, %x
+ %r = select <2 x i1> %c, <2 x i32> <i32 -1, i32 -1>, <2 x i32> %a
+ ret <2 x i32> %r
+}
+
+define i32 @uadd_sat_not_commute_select(i32 %x, i32 %y) {
+; CHECK-LABEL: @uadd_sat_not_commute_select(
+; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[NOTX]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %notx = xor i32 %x, -1
+ %a = add i32 %notx, %y
+ %c = icmp ult i32 %y, %x
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+define i32 @uadd_sat_not_commute_select_commute_add(i32 %x, i32 %yp) {
+; CHECK-LABEL: @uadd_sat_not_commute_select_commute_add(
+; CHECK-NEXT: [[Y:%.*]] = sdiv i32 42, [[YP:%.*]]
+; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[Y]], i32 [[NOTX]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %y = sdiv i32 42, %yp ; thwart complexity-based-canonicalization
+ %notx = xor i32 %x, -1
+ %a = add i32 %y, %notx
+ %c = icmp ult i32 %y, %x
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+define <2 x i32> @uadd_sat_not_commute_select_ugt(<2 x i32> %xp, <2 x i32> %yp) {
+; CHECK-LABEL: @uadd_sat_not_commute_select_ugt(
+; CHECK-NEXT: [[X:%.*]] = urem <2 x i32> <i32 42, i32 -42>, [[XP:%.*]]
+; CHECK-NEXT: [[Y:%.*]] = srem <2 x i32> <i32 12, i32 412>, [[YP:%.*]]
+; CHECK-NEXT: [[NOTX:%.*]] = xor <2 x i32> [[X]], <i32 -1, i32 -1>
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[Y]], <2 x i32> [[NOTX]])
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %x = urem <2 x i32> <i32 42, i32 -42>, %xp ; thwart complexity-based-canonicalization
+ %y = srem <2 x i32> <i32 12, i32 412>, %yp ; thwart complexity-based-canonicalization
+ %notx = xor <2 x i32> %x, <i32 -1, i32 -1>
+ %a = add <2 x i32> %y, %notx
+ %c = icmp ugt <2 x i32> %x, %y
+ %r = select <2 x i1> %c, <2 x i32> %a, <2 x i32> <i32 -1, i32 -1>
+ ret <2 x i32> %r
+}
+
+define i32 @uadd_sat_not_commute_select_ugt_commute_add(i32 %x, i32 %y) {
+; CHECK-LABEL: @uadd_sat_not_commute_select_ugt_commute_add(
+; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[NOTX]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %notx = xor i32 %x, -1
+ %a = add i32 %notx, %y
+ %c = icmp ugt i32 %x, %y
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+define i32 @uadd_sat_constant(i32 %x) {
+; CHECK-LABEL: @uadd_sat_constant(
+; CHECK-NEXT: [[A:%.*]] = add i32 [[X:%.*]], 42
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X]], -43
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 -1, i32 [[A]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %a = add i32 %x, 42
+ %c = icmp ugt i32 %x, -43
+ %r = select i1 %c, i32 -1, i32 %a
+ ret i32 %r
+}
+
+define i32 @uadd_sat_constant_commute(i32 %x) {
+; CHECK-LABEL: @uadd_sat_constant_commute(
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 42)
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %a = add i32 %x, 42
+ %c = icmp ult i32 %x, -43
+ %r = select i1 %c, i32 %a, i32 -1
+ ret i32 %r
+}
+
+define <4 x i32> @uadd_sat_constant_vec(<4 x i32> %x) {
+; CHECK-LABEL: @uadd_sat_constant_vec(
+; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 42, i32 42, i32 42>
+; CHECK-NEXT: [[C:%.*]] = icmp ugt <4 x i32> [[X]], <i32 -43, i32 -43, i32 -43, i32 -43>
+; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[A]]
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
+ %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
+ %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @uadd_sat_constant_vec_commute(<4 x i32> %x) {
+; CHECK-LABEL: @uadd_sat_constant_vec_commute(
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> [[X:%.*]], <4 x i32> <i32 42, i32 42, i32 42, i32 42>)
+; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+;
+ %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
+ %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
+ %r = select <4 x i1> %c, <4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @uadd_sat_constant_vec_commute_undefs(<4 x i32> %x) {
+; CHECK-LABEL: @uadd_sat_constant_vec_commute_undefs(
+; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 42, i32 42, i32 undef>
+; CHECK-NEXT: [[C:%.*]] = icmp ult <4 x i32> [[X]], <i32 -43, i32 -43, i32 undef, i32 -43>
+; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i32> [[A]], <4 x i32> <i32 -1, i32 undef, i32 -1, i32 -1>
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 undef>
+ %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 undef, i32 -43>
+ %r = select <4 x i1> %c, <4 x i32> %a, <4 x i32> <i32 -1, i32 undef, i32 -1, i32 -1>
+ ret <4 x i32> %r
+}
+
+declare i32 @get_i32()
+declare <2 x i8> @get_v2i8()
+
+define i32 @unsigned_sat_variable_using_min_add(i32 %x) {
+; CHECK-LABEL: @unsigned_sat_variable_using_min_add(
+; CHECK-NEXT: [[Y:%.*]] = call i32 @get_i32()
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %y = call i32 @get_i32() ; thwart complexity-based canonicalization
+ %noty = xor i32 %y, -1
+ %c = icmp ult i32 %x, %noty
+ %s = select i1 %c, i32 %x, i32 %noty
+ %r = add i32 %s, %y
+ ret i32 %r
+}
+
+define i32 @unsigned_sat_variable_using_min_commute_add(i32 %x) {
+; CHECK-LABEL: @unsigned_sat_variable_using_min_commute_add(
+; CHECK-NEXT: [[Y:%.*]] = call i32 @get_i32()
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %y = call i32 @get_i32() ; thwart complexity-based canonicalization
+ %noty = xor i32 %y, -1
+ %c = icmp ult i32 %x, %noty
+ %s = select i1 %c, i32 %x, i32 %noty
+ %r = add i32 %y, %s
+ ret i32 %r
+}
+
+define <2 x i8> @unsigned_sat_variable_using_min_commute_select(<2 x i8> %x) {
+; CHECK-LABEL: @unsigned_sat_variable_using_min_commute_select(
+; CHECK-NEXT: [[Y:%.*]] = call <2 x i8> @get_v2i8()
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y]])
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %y = call <2 x i8> @get_v2i8() ; thwart complexity-based canonicalization
+ %noty = xor <2 x i8> %y, <i8 -1, i8 -1>
+ %c = icmp ult <2 x i8> %noty, %x
+ %s = select <2 x i1> %c, <2 x i8> %noty, <2 x i8> %x
+ %r = add <2 x i8> %s, %y
+ ret <2 x i8> %r
+}
+
+define <2 x i8> @unsigned_sat_variable_using_min_commute_add_select(<2 x i8> %x) {
+; CHECK-LABEL: @unsigned_sat_variable_using_min_commute_add_select(
+; CHECK-NEXT: [[Y:%.*]] = call <2 x i8> @get_v2i8()
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y]])
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %y = call <2 x i8> @get_v2i8() ; thwart complexity-based canonicalization
+ %noty = xor <2 x i8> %y, <i8 -1, i8 -1>
+ %c = icmp ult <2 x i8> %noty, %x
+ %s = select <2 x i1> %c, <2 x i8> %noty, <2 x i8> %x
+ %r = add <2 x i8> %y, %s
+ ret <2 x i8> %r
+}
+
+; Negative test
+
+define i32 @unsigned_sat_variable_using_wrong_min(i32 %x) {
+; CHECK-LABEL: @unsigned_sat_variable_using_wrong_min(
+; CHECK-NEXT: [[Y:%.*]] = call i32 @get_i32()
+; CHECK-NEXT: [[NOTY:%.*]] = xor i32 [[Y]], -1
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[NOTY]], [[X:%.*]]
+; CHECK-NEXT: [[S:%.*]] = select i1 [[C]], i32 [[X]], i32 [[NOTY]]
+; CHECK-NEXT: [[R:%.*]] = add i32 [[Y]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %y = call i32 @get_i32() ; thwart complexity-based canonicalization
+ %noty = xor i32 %y, -1
+ %c = icmp slt i32 %x, %noty
+ %s = select i1 %c, i32 %x, i32 %noty
+ %r = add i32 %y, %s
+ ret i32 %r
+}
+
+; Negative test
+
+define i32 @unsigned_sat_variable_using_wrong_value(i32 %x, i32 %z) {
+; CHECK-LABEL: @unsigned_sat_variable_using_wrong_value(
+; CHECK-NEXT: [[Y:%.*]] = call i32 @get_i32()
+; CHECK-NEXT: [[NOTY:%.*]] = xor i32 [[Y]], -1
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[NOTY]], [[X:%.*]]
+; CHECK-NEXT: [[S:%.*]] = select i1 [[C]], i32 [[X]], i32 [[NOTY]]
+; CHECK-NEXT: [[R:%.*]] = add i32 [[S]], [[Z:%.*]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %y = call i32 @get_i32() ; thwart complexity-based canonicalization
+ %noty = xor i32 %y, -1
+ %c = icmp ult i32 %x, %noty
+ %s = select i1 %c, i32 %x, i32 %noty
+ %r = add i32 %z, %s
+ ret i32 %r
+}
+
+; If we have a constant operand, there's no commutativity variation.
+
+define i32 @unsigned_sat_constant_using_min(i32 %x) {
+; CHECK-LABEL: @unsigned_sat_constant_using_min(
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 -43)
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %c = icmp ult i32 %x, 42
+ %s = select i1 %c, i32 %x, i32 42
+ %r = add i32 %s, -43
+ ret i32 %r
+}
+
+define <2 x i32> @unsigned_sat_constant_using_min_splat(<2 x i32> %x) {
+; CHECK-LABEL: @unsigned_sat_constant_using_min_splat(
+; CHECK-NEXT: [[R:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 -15, i32 -15>)
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %c = icmp ult <2 x i32> %x, <i32 14, i32 14>
+ %s = select <2 x i1> %c, <2 x i32> %x, <2 x i32> <i32 14, i32 14>
+ %r = add <2 x i32> %s, <i32 -15, i32 -15>
+ ret <2 x i32> %r
+}
+
+; Negative test
+
+define i32 @unsigned_sat_constant_using_min_wrong_constant(i32 %x) {
+; CHECK-LABEL: @unsigned_sat_constant_using_min_wrong_constant(
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], 42
+; CHECK-NEXT: [[S:%.*]] = select i1 [[C]], i32 [[X]], i32 42
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[S]], -42
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %c = icmp ult i32 %x, 42
+ %s = select i1 %c, i32 %x, i32 42
+ %r = add i32 %s, -42
+ ret i32 %r
+}
Added: llvm/trunk/test/Transforms/InstCombine/scalarization.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/scalarization.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/scalarization.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/scalarization.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,335 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+define i32 @extract_load(<4 x i32>* %p) {
+; CHECK-LABEL: @extract_load(
+; CHECK-NEXT: [[X:%.*]] = load <4 x i32>, <4 x i32>* [[P:%.*]], align 4
+; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x i32> [[X]], i32 1
+; CHECK-NEXT: ret i32 [[EXT]]
+;
+ %x = load <4 x i32>, <4 x i32>* %p, align 4
+ %ext = extractelement <4 x i32> %x, i32 1
+ ret i32 %ext
+}
+
+define double @extract_load_fp(<4 x double>* %p) {
+; CHECK-LABEL: @extract_load_fp(
+; CHECK-NEXT: [[X:%.*]] = load <4 x double>, <4 x double>* [[P:%.*]], align 32
+; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 3
+; CHECK-NEXT: ret double [[EXT]]
+;
+ %x = load <4 x double>, <4 x double>* %p, align 32
+ %ext = extractelement <4 x double> %x, i32 3
+ ret double %ext
+}
+
+define double @extract_load_volatile(<4 x double>* %p) {
+; CHECK-LABEL: @extract_load_volatile(
+; CHECK-NEXT: [[X:%.*]] = load volatile <4 x double>, <4 x double>* [[P:%.*]], align 32
+; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 2
+; CHECK-NEXT: ret double [[EXT]]
+;
+ %x = load volatile <4 x double>, <4 x double>* %p
+ %ext = extractelement <4 x double> %x, i32 2
+ ret double %ext
+}
+
+define double @extract_load_extra_use(<4 x double>* %p, <4 x double>* %p2) {
+; CHECK-LABEL: @extract_load_extra_use(
+; CHECK-NEXT: [[X:%.*]] = load <4 x double>, <4 x double>* [[P:%.*]], align 8
+; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 0
+; CHECK-NEXT: store <4 x double> [[X]], <4 x double>* [[P2:%.*]], align 32
+; CHECK-NEXT: ret double [[EXT]]
+;
+ %x = load <4 x double>, <4 x double>* %p, align 8
+ %ext = extractelement <4 x double> %x, i32 0
+ store <4 x double> %x, <4 x double>* %p2
+ ret double %ext
+}
+
+define double @extract_load_variable_index(<4 x double>* %p, i32 %y) {
+; CHECK-LABEL: @extract_load_variable_index(
+; CHECK-NEXT: [[X:%.*]] = load <4 x double>, <4 x double>* [[P:%.*]], align 32
+; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret double [[EXT]]
+;
+ %x = load <4 x double>, <4 x double>* %p
+ %ext = extractelement <4 x double> %x, i32 %y
+ ret double %ext
+}
+
+define void @scalarize_phi(i32 * %n, float * %inout) {
+; CHECK-LABEL: @scalarize_phi(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[T0:%.*]] = load volatile float, float* [[INOUT:%.*]], align 4
+; CHECK-NEXT: br label [[FOR_COND:%.*]]
+; CHECK: for.cond:
+; CHECK-NEXT: [[TMP0:%.*]] = phi float [ [[T0]], [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[FOR_BODY:%.*]] ]
+; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[N:%.*]], align 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[I_0]], [[T1]]
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK: for.body:
+; CHECK-NEXT: store volatile float [[TMP0]], float* [[INOUT]], align 4
+; CHECK-NEXT: [[TMP1]] = fmul float [[TMP0]], 0x4002A3D700000000
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
+; CHECK-NEXT: br label [[FOR_COND]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
+entry:
+ %t0 = load volatile float, float * %inout, align 4
+ %insert = insertelement <4 x float> undef, float %t0, i32 0
+ %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer
+ %insert1 = insertelement <4 x float> undef, float 3.0, i32 0
+ br label %for.cond
+
+for.cond:
+ %x.0 = phi <4 x float> [ %splat, %entry ], [ %mul, %for.body ]
+ %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+ %t1 = load i32, i32 * %n, align 4
+ %cmp = icmp ne i32 %i.0, %t1
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body:
+ %t2 = extractelement <4 x float> %x.0, i32 1
+ store volatile float %t2, float * %inout, align 4
+ %mul = fmul <4 x float> %x.0, <float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000>
+ %inc = add nsw i32 %i.0, 1
+ br label %for.cond
+
+for.end:
+ ret void
+}
+
+define float @extract_element_binop_splat_constant_index(<4 x float> %x) {
+; CHECK-LABEL: @extract_element_binop_splat_constant_index(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i32 2
+; CHECK-NEXT: [[R:%.*]] = fadd float [[TMP1]], 0x4002A3D700000000
+; CHECK-NEXT: ret float [[R]]
+;
+ %b = fadd <4 x float> %x, <float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000>
+ %r = extractelement <4 x float> %b, i32 2
+ ret float %r
+}
+
+define double @extract_element_binop_splat_with_undef_constant_index(<2 x double> %x) {
+; CHECK-LABEL: @extract_element_binop_splat_with_undef_constant_index(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[X:%.*]], i32 0
+; CHECK-NEXT: [[R:%.*]] = fdiv double 4.200000e+01, [[TMP1]]
+; CHECK-NEXT: ret double [[R]]
+;
+ %b = fdiv <2 x double> <double 42.0, double undef>, %x
+ %r = extractelement <2 x double> %b, i32 0
+ ret double %r
+}
+
+define float @extract_element_binop_nonsplat_constant_index(<2 x float> %x) {
+; CHECK-LABEL: @extract_element_binop_nonsplat_constant_index(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X:%.*]], i32 1
+; CHECK-NEXT: [[R:%.*]] = fmul float [[TMP1]], 4.300000e+01
+; CHECK-NEXT: ret float [[R]]
+;
+ %b = fmul <2 x float> %x, <float 42.0, float 43.0>
+ %r = extractelement <2 x float> %b, i32 1
+ ret float %r
+}
+
+define i8 @extract_element_binop_splat_variable_index(<4 x i8> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_binop_splat_variable_index(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[TMP1]], 42
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = sdiv <4 x i8> %x, <i8 42, i8 42, i8 42, i8 42>
+ %r = extractelement <4 x i8> %b, i32 %y
+ ret i8 %r
+}
+
+define i8 @extract_element_binop_splat_with_undef_variable_index(<4 x i8> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_binop_splat_with_undef_variable_index(
+; CHECK-NEXT: [[B:%.*]] = mul <4 x i8> [[X:%.*]], <i8 42, i8 42, i8 undef, i8 42>
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i8> [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = mul <4 x i8> %x, <i8 42, i8 42, i8 undef, i8 42>
+ %r = extractelement <4 x i8> %b, i32 %y
+ ret i8 %r
+}
+
+define i8 @extract_element_binop_nonsplat_variable_index(<4 x i8> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_binop_nonsplat_variable_index(
+; CHECK-NEXT: [[B:%.*]] = lshr <4 x i8> [[X:%.*]], <i8 4, i8 3, i8 undef, i8 2>
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i8> [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %b = lshr <4 x i8> %x, <i8 4, i8 3, i8 undef, i8 2>
+ %r = extractelement <4 x i8> %b, i32 %y
+ ret i8 %r
+}
+
+define float @extract_element_load(<4 x float> %x, <4 x float>* %ptr) {
+; CHECK-LABEL: @extract_element_load(
+; CHECK-NEXT: [[LOAD:%.*]] = load <4 x float>, <4 x float>* [[PTR:%.*]], align 16
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[LOAD]], i32 2
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[X:%.*]], i32 2
+; CHECK-NEXT: [[R:%.*]] = fadd float [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret float [[R]]
+;
+ %load = load <4 x float>, <4 x float>* %ptr
+ %add = fadd <4 x float> %x, %load
+ %r = extractelement <4 x float> %add, i32 2
+ ret float %r
+}
+
+define float @extract_element_multi_Use_load(<4 x float> %x, <4 x float>* %ptr0, <4 x float>* %ptr1) {
+; CHECK-LABEL: @extract_element_multi_Use_load(
+; CHECK-NEXT: [[LOAD:%.*]] = load <4 x float>, <4 x float>* [[PTR0:%.*]], align 16
+; CHECK-NEXT: store <4 x float> [[LOAD]], <4 x float>* [[PTR1:%.*]], align 16
+; CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[LOAD]], [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[ADD]], i32 2
+; CHECK-NEXT: ret float [[R]]
+;
+ %load = load <4 x float>, <4 x float>* %ptr0
+ store <4 x float> %load, <4 x float>* %ptr1
+ %add = fadd <4 x float> %x, %load
+ %r = extractelement <4 x float> %add, i32 2
+ ret float %r
+}
+
+define float @extract_element_variable_index(<4 x float> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_variable_index(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = fadd float [[TMP1]], 1.000000e+00
+; CHECK-NEXT: ret float [[R]]
+;
+ %add = fadd <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
+ %r = extractelement <4 x float> %add, i32 %y
+ ret float %r
+}
+
+define float @extelt_binop_insertelt(<4 x float> %A, <4 x float> %B, float %f) {
+; CHECK-LABEL: @extelt_binop_insertelt(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[B:%.*]], i32 0
+; CHECK-NEXT: [[E:%.*]] = fmul nnan float [[TMP1]], [[F:%.*]]
+; CHECK-NEXT: ret float [[E]]
+;
+ %C = insertelement <4 x float> %A, float %f, i32 0
+ %D = fmul nnan <4 x float> %C, %B
+ %E = extractelement <4 x float> %D, i32 0
+ ret float %E
+}
+
+; We recurse to find a scalarizable operand.
+; FIXME: We should propagate the IR flags including wrapping flags.
+
+define i32 @extelt_binop_binop_insertelt(<4 x i32> %A, <4 x i32> %B, i32 %f) {
+; CHECK-LABEL: @extelt_binop_binop_insertelt(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[B:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], [[F:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[B]], i32 0
+; CHECK-NEXT: [[E:%.*]] = mul i32 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: ret i32 [[E]]
+;
+ %v = insertelement <4 x i32> %A, i32 %f, i32 0
+ %C = add <4 x i32> %v, %B
+ %D = mul nsw <4 x i32> %C, %B
+ %E = extractelement <4 x i32> %D, i32 0
+ ret i32 %E
+}
+
+define float @extract_element_constant_vector_variable_index(i32 %y) {
+; CHECK-LABEL: @extract_element_constant_vector_variable_index(
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>, i32 [[Y:%.*]]
+; CHECK-NEXT: ret float [[R]]
+;
+ %r = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %y
+ ret float %r
+}
+
+define i1 @cheap_to_extract_icmp(<4 x i32> %x, <4 x i1> %y) {
+; CHECK-LABEL: @cheap_to_extract_icmp(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 2
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[Y:%.*]], i32 2
+; CHECK-NEXT: [[R:%.*]] = and i1 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %cmp = icmp eq <4 x i32> %x, zeroinitializer
+ %and = and <4 x i1> %cmp, %y
+ %r = extractelement <4 x i1> %and, i32 2
+ ret i1 %r
+}
+
+define i1 @cheap_to_extract_fcmp(<4 x float> %x, <4 x i1> %y) {
+; CHECK-LABEL: @cheap_to_extract_fcmp(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i32 2
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], 0.000000e+00
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[Y:%.*]], i32 2
+; CHECK-NEXT: [[R:%.*]] = and i1 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %cmp = fcmp oeq <4 x float> %x, zeroinitializer
+ %and = and <4 x i1> %cmp, %y
+ %r = extractelement <4 x i1> %and, i32 2
+ ret i1 %r
+}
+
+define i1 @extractelt_vector_icmp_constrhs(<2 x i32> %arg) {
+; CHECK-LABEL: @extractelt_vector_icmp_constrhs(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[ARG:%.*]], i32 0
+; CHECK-NEXT: [[EXT:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[EXT]]
+;
+ %cmp = icmp eq <2 x i32> %arg, zeroinitializer
+ %ext = extractelement <2 x i1> %cmp, i32 0
+ ret i1 %ext
+}
+
+define i1 @extractelt_vector_fcmp_constrhs(<2 x float> %arg) {
+; CHECK-LABEL: @extractelt_vector_fcmp_constrhs(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[ARG:%.*]], i32 0
+; CHECK-NEXT: [[EXT:%.*]] = fcmp oeq float [[TMP1]], 0.000000e+00
+; CHECK-NEXT: ret i1 [[EXT]]
+;
+ %cmp = fcmp oeq <2 x float> %arg, zeroinitializer
+ %ext = extractelement <2 x i1> %cmp, i32 0
+ ret i1 %ext
+}
+
+define i1 @extractelt_vector_icmp_constrhs_dynidx(<2 x i32> %arg, i32 %idx) {
+; CHECK-LABEL: @extractelt_vector_icmp_constrhs_dynidx(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[ARG:%.*]], i32 [[IDX:%.*]]
+; CHECK-NEXT: [[EXT:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[EXT]]
+;
+ %cmp = icmp eq <2 x i32> %arg, zeroinitializer
+ %ext = extractelement <2 x i1> %cmp, i32 %idx
+ ret i1 %ext
+}
+
+define i1 @extractelt_vector_fcmp_constrhs_dynidx(<2 x float> %arg, i32 %idx) {
+; CHECK-LABEL: @extractelt_vector_fcmp_constrhs_dynidx(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[ARG:%.*]], i32 [[IDX:%.*]]
+; CHECK-NEXT: [[EXT:%.*]] = fcmp oeq float [[TMP1]], 0.000000e+00
+; CHECK-NEXT: ret i1 [[EXT]]
+;
+ %cmp = fcmp oeq <2 x float> %arg, zeroinitializer
+ %ext = extractelement <2 x i1> %cmp, i32 %idx
+ ret i1 %ext
+}
+
+define i1 @extractelt_vector_fcmp_not_cheap_to_scalarize_multi_use(<2 x float> %arg0, <2 x float> %arg1, <2 x float> %arg2, i32 %idx) {
+; CHECK-LABEL: @extractelt_vector_fcmp_not_cheap_to_scalarize_multi_use(
+; CHECK-NEXT: [[ADD:%.*]] = fadd <2 x float> [[ARG1:%.*]], [[ARG2:%.*]]
+; CHECK-NEXT: store volatile <2 x float> [[ADD]], <2 x float>* undef, align 8
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x float> [[ADD]], [[ARG0:%.*]]
+; CHECK-NEXT: [[EXT:%.*]] = extractelement <2 x i1> [[CMP]], i32 0
+; CHECK-NEXT: ret i1 [[EXT]]
+;
+ %add = fadd <2 x float> %arg1, %arg2
+ store volatile <2 x float> %add, <2 x float>* undef
+ %cmp = fcmp oeq <2 x float> %arg0, %add
+ %ext = extractelement <2 x i1> %cmp, i32 0
+ ret i1 %ext
+}
Added: llvm/trunk/test/Transforms/InstCombine/sdiv-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sdiv-1.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sdiv-1.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sdiv-1.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -inline -S | FileCheck %s
+; PR3142
+
+define i32 @a(i32 %X) {
+; CHECK-LABEL: @a(
+; CHECK-NEXT: [[T0:%.*]] = sub i32 0, [[X:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[T0]], -3
+; CHECK-NEXT: ret i32 [[T1]]
+;
+ %t0 = sub i32 0, %X
+ %t1 = sdiv i32 %t0, -3
+ ret i32 %t1
+}
+
+define i32 @b(i32 %X) {
+; CHECK-LABEL: @b(
+; CHECK-NEXT: ret i32 715827882
+;
+ %t0 = call i32 @a(i32 -2147483648)
+ ret i32 %t0
+}
+
+define i32 @c(i32 %X) {
+; CHECK-LABEL: @c(
+; CHECK-NEXT: ret i32 715827882
+;
+ %t0 = sub i32 0, -2147483648
+ %t1 = sdiv i32 %t0, -3
+ ret i32 %t1
+}
Added: llvm/trunk/test/Transforms/InstCombine/sdiv-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sdiv-2.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sdiv-2.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sdiv-2.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,28 @@
+; RUN: opt < %s -instcombine -disable-output
+; PR3144
+
+define fastcc i32 @func(i32 %length) nounwind {
+entry:
+ %0 = icmp ne i32 %length, -1 ; <i1> [#uses=1]
+ %iftmp.13.0 = select i1 %0, i128 0, i128 200000000 ; <i128> [#uses=2]
+ %1 = sdiv i128 %iftmp.13.0, 10 ; <i128> [#uses=1]
+ br label %bb5
+
+bb5: ; preds = %bb8, %entry
+ %v.0 = phi i128 [ 0, %entry ], [ %6, %bb8 ] ; <i128> [#uses=2]
+ %2 = icmp sgt i128 %v.0, %1 ; <i1> [#uses=1]
+ br i1 %2, label %overflow, label %bb7
+
+bb7: ; preds = %bb5
+ %3 = mul i128 %v.0, 10 ; <i128> [#uses=2]
+ %4 = sub i128 %iftmp.13.0, 0 ; <i128> [#uses=1]
+ %5 = icmp slt i128 %4, %3 ; <i1> [#uses=1]
+ br i1 %5, label %overflow, label %bb8
+
+bb8: ; preds = %bb7
+ %6 = add i128 0, %3 ; <i128> [#uses=1]
+ br label %bb5
+
+overflow: ; preds = %bb7, %bb5
+ ret i32 1
+}
Added: llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @test_sdiv_canonicalize_op0(i32 %x, i32 %y) {
+; CHECK-LABEL: @test_sdiv_canonicalize_op0(
+; CHECK-NEXT: [[SDIV1:%.*]] = sdiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[SDIV:%.*]] = sub nsw i32 0, [[SDIV1]]
+; CHECK-NEXT: ret i32 [[SDIV]]
+;
+ %neg = sub nsw i32 0, %x
+ %sdiv = sdiv i32 %neg, %y
+ ret i32 %sdiv
+}
+
+define i32 @test_sdiv_canonicalize_op0_exact(i32 %x, i32 %y) {
+; CHECK-LABEL: @test_sdiv_canonicalize_op0_exact(
+; CHECK-NEXT: [[SDIV1:%.*]] = sdiv exact i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[SDIV:%.*]] = sub nsw i32 0, [[SDIV1]]
+; CHECK-NEXT: ret i32 [[SDIV]]
+;
+ %neg = sub nsw i32 0, %x
+ %sdiv = sdiv exact i32 %neg, %y
+ ret i32 %sdiv
+}
+
+; (X/-Y) is not equal to -(X/Y), don't canonicalize.
+define i32 @test_sdiv_canonicalize_op1(i32 %x, i32 %z) {
+; CHECK-LABEL: @test_sdiv_canonicalize_op1(
+; CHECK-NEXT: [[Y:%.*]] = mul i32 [[Z:%.*]], 3
+; CHECK-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[X:%.*]]
+; CHECK-NEXT: [[SDIV:%.*]] = sdiv i32 [[Y]], [[NEG]]
+; CHECK-NEXT: ret i32 [[SDIV]]
+;
+ %y = mul i32 %z, 3
+ %neg = sub nsw i32 0, %x
+ %sdiv = sdiv i32 %y, %neg
+ ret i32 %sdiv
+}
+
+define i32 @test_sdiv_canonicalize_nonsw(i32 %x, i32 %y) {
+; CHECK-LABEL: @test_sdiv_canonicalize_nonsw(
+; CHECK-NEXT: [[NEG:%.*]] = sub i32 0, [[X:%.*]]
+; CHECK-NEXT: [[SDIV:%.*]] = sdiv i32 [[NEG]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SDIV]]
+;
+ %neg = sub i32 0, %x
+ %sdiv = sdiv i32 %neg, %y
+ ret i32 %sdiv
+}
+
+define <2 x i32> @test_sdiv_canonicalize_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @test_sdiv_canonicalize_vec(
+; CHECK-NEXT: [[SDIV1:%.*]] = sdiv <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[SDIV:%.*]] = sub nsw <2 x i32> zeroinitializer, [[SDIV1]]
+; CHECK-NEXT: ret <2 x i32> [[SDIV]]
+;
+ %neg = sub nsw <2 x i32> <i32 0, i32 0>, %x
+ %sdiv = sdiv <2 x i32> %neg, %y
+ ret <2 x i32> %sdiv
+}
+
+define i32 @test_sdiv_canonicalize_multiple_uses(i32 %x, i32 %y) {
+; CHECK-LABEL: @test_sdiv_canonicalize_multiple_uses(
+; CHECK-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[X:%.*]]
+; CHECK-NEXT: [[SDIV:%.*]] = sdiv i32 [[NEG]], [[Y:%.*]]
+; CHECK-NEXT: [[SDIV2:%.*]] = sdiv i32 [[SDIV]], [[NEG]]
+; CHECK-NEXT: ret i32 [[SDIV2]]
+;
+ %neg = sub nsw i32 0, %x
+ %sdiv = sdiv i32 %neg, %y
+ %sdiv2 = sdiv i32 %sdiv, %neg
+ ret i32 %sdiv2
+}
+
+; There is combination: -(X/CE) -> (X/-CE).
+; If combines (X/-CE) to -(X/CE), make sure don't combine them endless.
+
+ at X = global i32 5
+
+define i64 @test_sdiv_canonicalize_constexpr(i64 %L1) {
+; currently opt folds (sub nsw i64 0, constexpr) -> (sub i64, 0, constexpr).
+; sdiv canonicalize requires a nsw sub.
+; CHECK-LABEL: @test_sdiv_canonicalize_constexpr(
+; CHECK-NEXT: [[B4:%.*]] = sdiv i64 [[L1:%.*]], sub (i64 0, i64 ptrtoint (i32* @X to i64))
+; CHECK-NEXT: ret i64 [[B4]]
+;
+ %v1 = ptrtoint i32* @X to i64
+ %B8 = sub nsw i64 0, %v1
+ %B4 = sdiv i64 %L1, %B8
+ ret i64 %B4
+}
Added: llvm/trunk/test/Transforms/InstCombine/sdiv-guard.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sdiv-guard.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sdiv-guard.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sdiv-guard.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare void @llvm.experimental.guard(i1, ...)
+
+; Regression test. If %flag is false then %s == 0 and guard should be triggered.
+define i32 @a(i1 %flag, i32 %X) nounwind readnone {
+; CHECK-LABEL: @a(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: [[CMP:%.*]] = and i1 [[CMP1]], [[FLAG:%.*]]
+; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) #1 [ "deopt"() ]
+; CHECK-NEXT: [[R:%.*]] = sdiv i32 100, [[X]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %s = select i1 %flag, i32 %X, i32 0
+ %cmp = icmp ne i32 %s, 0
+ call void(i1, ...) @llvm.experimental.guard( i1 %cmp )[ "deopt"() ]
+ %r = sdiv i32 100, %s
+ ret i32 %r
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-2.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-2.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-2.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,31 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; CHECK: select
+; CHECK: select
+
+; Make sure instcombine don't fold select into operands. We don't want to emit
+; select of two integers unless it's selecting 0 / 1.
+
+define i32 @t1(i32 %c, i32 %x) nounwind {
+ %t1 = icmp eq i32 %c, 0
+ %t2 = lshr i32 %x, 18
+ %t3 = select i1 %t1, i32 %t2, i32 %x
+ ret i32 %t3
+}
+
+define i32 @t2(i32 %c, i32 %x) nounwind {
+ %t1 = icmp eq i32 %c, 0
+ %t2 = and i32 %x, 18
+ %t3 = select i1 %t1, i32 %t2, i32 %x
+ ret i32 %t3
+}
+
+define float @t3(float %x, float %y) nounwind {
+ %t1 = fcmp ogt float %x, %y
+ %t2 = select i1 %t1, float %x, float 1.0
+ %t3 = fadd fast float %t2, 1.0
+ ret float %t3
+; CHECK-LABEL: @t3(
+; CHECK: fadd fast
+; CHECK: select
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-binop-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-binop-cmp.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-binop-cmp.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-binop-cmp.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1088 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare void @use(<2 x i1>)
+declare void @use2(i1)
+
+define i32 @select_xor_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_xor_icmp2(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_icmp2(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %y, i32 %B
+ ret i32 %C
+}
+
+define i32 @select_xor_icmp_meta(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_icmp_meta(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]], !prof !0
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y, !prof !0
+ ret i32 %C
+}
+
+define i32 @select_mul_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_mul_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 1
+ %B = mul i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_add_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_add_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = add i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_or_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_or_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = or i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_and_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_and_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], -1
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, -1
+ %B = and i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define <2 x i8> @select_xor_icmp_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
+; CHECK-LABEL: @select_xor_icmp_vec(
+; CHECK-NEXT: [[A:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[Z:%.*]], <2 x i8> [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i8> [[C]]
+;
+ %A = icmp eq <2 x i8> %x, <i8 0, i8 0>
+ %B = xor <2 x i8> %x, %z
+ %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y
+ ret <2 x i8> %C
+}
+
+define <2 x i8> @select_xor_icmp_vec_use(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
+; CHECK-LABEL: @select_xor_icmp_vec_use(
+; CHECK-NEXT: [[A:%.*]] = icmp ne <2 x i8> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: call void @use(<2 x i1> [[A]])
+; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[Y:%.*]], <2 x i8> [[Z:%.*]]
+; CHECK-NEXT: ret <2 x i8> [[C]]
+;
+ %A = icmp ne <2 x i8> %x, <i8 0, i8 0>
+ call void @use(<2 x i1> %A)
+ %B = xor <2 x i8> %x, %z
+ %C = select <2 x i1> %A, <2 x i8> %y, <2 x i8> %B
+ ret <2 x i8> %C
+}
+
+define i32 @select_xor_inv_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_inv_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = xor i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_xor_inv_icmp2(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_inv_icmp2(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Y:%.*]], i32 [[Z:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ call void @use2(i1 %A) ; thwart predicate canonicalization
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %y, i32 %B
+ ret i32 %C
+}
+
+define float @select_fadd_fcmp(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z:%.*]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -0.0
+ %B = fadd nsz float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; This is logically equivalent to the previous test - fcmp ignores the sign of 0.0.
+
+define float @select_fadd_fcmp_poszero(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_poszero(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z:%.*]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 0.0
+ %B = fadd nsz float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fadd_fcmp_2(float %x, float %y, float %v) {
+; CHECK-LABEL: @select_fadd_fcmp_2(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[Z:%.*]] = fadd float [[V:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[Z]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, -0.0
+ %z = fadd float %v, 0.0 ; cannot produce -0.0
+ %B = fadd float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; This is logically equivalent to the previous test - fcmp ignores the sign of 0.0.
+
+define float @select_fadd_fcmp_2_poszero(float %x, float %y, float %v) {
+; CHECK-LABEL: @select_fadd_fcmp_2_poszero(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[Z:%.*]] = fadd float [[V:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[Z]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, 0.0
+ %z = fadd float %v, 0.0 ; cannot produce -0.0
+ %B = fadd float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+define float @select_fadd_fcmp_3(float %x, float %y) {
+; CHECK-LABEL: @select_fadd_fcmp_3(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float 6.000000e+00
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, -0.0
+ %B = fadd float 6.0, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; This is logically equivalent to the previous test - fcmp ignores the sign of 0.0.
+
+define float @select_fadd_fcmp_3_poszero(float %x, float %y) {
+; CHECK-LABEL: @select_fadd_fcmp_3_poszero(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float 6.000000e+00
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, 0.0
+ %B = fadd float 6.0, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+define float @select_fadd_fcmp_4(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_4(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[Z:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, -0.0
+ %B = fadd nsz float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; This is logically equivalent to the previous test - fcmp ignores the sign of 0.0.
+
+define float @select_fadd_fcmp_4_poszero(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_4_poszero(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[Z:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, 0.0
+ %B = fadd nsz float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+define float @select_fadd_fcmp_5(float %x, float %y, float %v) {
+; CHECK-LABEL: @select_fadd_fcmp_5(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[Z:%.*]] = fadd float [[V:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -0.0
+ %z = fadd float %v, 0.0 ; cannot produce -0.0
+ %B = fadd float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; This is logically equivalent to the previous test - fcmp ignores the sign of 0.0.
+
+define float @select_fadd_fcmp_5_poszero(float %x, float %y, float %v) {
+; CHECK-LABEL: @select_fadd_fcmp_5_poszero(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[Z:%.*]] = fadd float [[V:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 0.0
+ %z = fadd float %v, 0.0 ; cannot produce -0.0
+ %B = fadd float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fadd_fcmp_6(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_6(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float 6.000000e+00, float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -0.0
+ %B = fadd float %x, 6.0
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; This is logically equivalent to the previous test - fcmp ignores the sign of 0.0.
+
+define float @select_fadd_fcmp_6_poszero(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_6_poszero(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float 6.000000e+00, float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 0.0
+ %B = fadd float %x, 6.0
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fmul_fcmp(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fmul_fcmp(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z:%.*]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 1.0
+ %B = fmul nsz float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fsub_fcmp(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fsub_fcmp(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z:%.*]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 0.0
+ %B = fsub nsz float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; This is logically equivalent to the previous test - fcmp ignores the sign of 0.0.
+
+define float @select_fsub_fcmp_negzero(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fsub_fcmp_negzero(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z:%.*]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -0.0
+ %B = fsub nsz float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fdiv_fcmp(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fdiv_fcmp(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Z:%.*]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 1.0
+ %B = fdiv nsz float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define i32 @select_sub_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sub_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = sub i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sub_icmp_2(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sub_icmp_2(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ call void @use2(i1 %A)
+ %B = sub i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sub_icmp_3(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sub_icmp_3(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Y:%.*]], i32 [[Z:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ call void @use2(i1 %A)
+ %B = sub i32 %z, %x
+ %C = select i1 %A, i32 %y, i32 %B
+ ret i32 %C
+}
+
+define <2 x i8> @select_sub_icmp_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
+; CHECK-LABEL: @select_sub_icmp_vec(
+; CHECK-NEXT: [[A:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[Z:%.*]], <2 x i8> [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i8> [[C]]
+;
+ %A = icmp eq <2 x i8> %x, <i8 0, i8 0>
+ %B = sub <2 x i8> %z, %x
+ %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y
+ ret <2 x i8> %C
+}
+
+define i32 @select_shl_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_shl_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Y:%.*]], i32 [[Z:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ call void @use2(i1 %A) ; thwart predicate canonicalization
+ %B = shl i32 %z, %x
+ %C = select i1 %A, i32 %y, i32 %B
+ ret i32 %C
+}
+
+define i32 @select_lshr_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_lshr_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = lshr i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_ashr_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_ashr_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Y:%.*]], i32 [[Z:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ call void @use2(i1 %A) ; thwart predicate canonicalization
+ %B = ashr i32 %z, %x
+ %C = select i1 %A, i32 %y, i32 %B
+ ret i32 %C
+}
+
+define i32 @select_udiv_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_udiv_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 1
+ %B = udiv i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sdiv_icmp(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sdiv_icmp(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 1
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Y:%.*]], i32 [[Z:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 1
+ call void @use2(i1 %A) ; thwart predicate canonicalization
+ %B = sdiv i32 %z, %x
+ %C = select i1 %A, i32 %y, i32 %B
+ ret i32 %C
+}
+
+; Negative tests
+define i32 @select_xor_icmp_bad_1(i32 %x, i32 %y, i32 %z, i32 %k) {
+; CHECK-LABEL: @select_xor_icmp_bad_1(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[K:%.*]]
+; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, %k
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_xor_icmp_bad_2(i32 %x, i32 %y, i32 %z, i32 %k) {
+; CHECK-LABEL: @select_xor_icmp_bad_2(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = xor i32 [[K:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = xor i32 %k, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_xor_icmp_bad_3(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_icmp_bad_3(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 3
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_xor_fcmp_bad_4(i32 %x, i32 %y, i32 %z, float %k) {
+; CHECK-LABEL: @select_xor_fcmp_bad_4(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[K:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = xor i32 [[X:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = fcmp oeq float %k, 0.0
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_xor_icmp_bad_5(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_icmp_bad_5(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Y:%.*]], i32 [[B]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_xor_icmp_bad_6(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_xor_icmp_bad_6(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 1
+ %B = xor i32 %x, %z
+ %C = select i1 %A, i32 %y, i32 %B
+ ret i32 %C
+}
+
+define <2 x i8> @select_xor_icmp_vec_bad(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
+; CHECK-LABEL: @select_xor_icmp_vec_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 5, i8 3>
+; CHECK-NEXT: [[B:%.*]] = xor <2 x i8> [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[B]], <2 x i8> [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i8> [[C]]
+;
+ %A = icmp eq <2 x i8> %x, <i8 5, i8 3>
+ %B = xor <2 x i8> %x, %z
+ %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y
+ ret <2 x i8> %C
+}
+
+; TODO: support for undefs, check for an identity constant does not handle them yet
+define <2 x i8> @select_xor_icmp_vec_bad_2(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
+; CHECK-LABEL: @select_xor_icmp_vec_bad_2(
+; CHECK-NEXT: [[A:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 0, i8 undef>
+; CHECK-NEXT: [[B:%.*]] = xor <2 x i8> [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[B]], <2 x i8> [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i8> [[C]]
+;
+ %A = icmp eq <2 x i8> %x, <i8 0, i8 undef>
+ %B = xor <2 x i8> %x, %z
+ %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y
+ ret <2 x i8> %C
+}
+
+define i32 @select_mul_icmp_bad(i32 %x, i32 %y, i32 %z, i32 %k) {
+; CHECK-LABEL: @select_mul_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[B:%.*]] = mul i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 3
+ %B = mul i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_add_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_add_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[B:%.*]] = add i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 1
+ %B = add i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_and_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_and_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = and i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = and i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_or_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_or_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[B:%.*]] = or i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 3
+ %B = or i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+; Invalid identity constant for FP op
+define float @select_fadd_fcmp_bad(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], -1.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd nsz float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -1.0
+ %B = fadd nsz float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; Invalid comparison type
+define float @select_fadd_fcmp_bad_2(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_2(
+; CHECK-NEXT: [[A:%.*]] = fcmp ueq float [[X:%.*]], -1.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp ueq float %x, -1.0
+ %B = fadd float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; Invalid comparison type
+define float @select_fadd_fcmp_bad_3(float %x, float %y, float %z, float %k) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_3(
+; CHECK-NEXT: [[A:%.*]] = fcmp one float [[X:%.*]], [[K:%.*]]
+; CHECK-NEXT: [[B:%.*]] = fadd float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp one float %x, %k
+ %B = fadd float %x, %z
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Invalid order of operands of select
+define float @select_fadd_fcmp_bad_4(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_4(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, -0.0
+ %B = fadd float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; Invalid comparison type
+define float @select_fadd_fcmp_bad_5(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_5(
+; CHECK-NEXT: [[A:%.*]] = fcmp one float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd nsz float [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp one float %x, -0.0
+ %B = fadd nsz float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Invalid order of operands of select
+define float @select_fadd_fcmp_bad_6(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_6(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd nsz float [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -0.0
+ %B = fadd nsz float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Do not transform if we have signed zeros and if Z is possibly negative zero
+define float @select_fadd_fcmp_bad_7(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_7(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -0.0
+ %B = fadd float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; Invalid comparison type
+define float @select_fadd_fcmp_bad_8(float %x, float %y, float %v) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_8(
+; CHECK-NEXT: [[A:%.*]] = fcmp one float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[Z:%.*]] = fadd float [[V:%.*]], -1.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd float [[Z]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp one float %x, -0.0
+ %z = fadd float %v, -1.0
+ %B = fadd float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Invalid comparison type
+define float @select_fadd_fcmp_bad_9(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_9(
+; CHECK-NEXT: [[A:%.*]] = fcmp one float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd nsz float [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp one float %x, -0.0
+ %B = fadd nsz float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Invalid comparison type
+define float @select_fadd_fcmp_bad_10(float %x, float %y, float %v) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_10(
+; CHECK-NEXT: [[A:%.*]] = fcmp one float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[Z:%.*]] = fadd float [[V:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd float [[Z]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp one float %x, -0.0
+ %z = fadd float %v, 0.0 ; cannot produce -0.0
+ %B = fadd float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Do not transform if Z is possibly negative zero
+define float @select_fadd_fcmp_bad_11(float %x, float %y, float %v) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_11(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[Z:%.*]] = fadd float [[V:%.*]], -1.000000e+00
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[Z]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, -0.0
+ %z = fadd float %v, -1.0
+ %B = fadd nsz float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Do not transform if we have signed zeros and if Z is possibly negative zero
+define float @select_fadd_fcmp_bad_12(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_12(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd float [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, -0.0
+ %B = fadd float %z, %x
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Invalid order of operands of select
+define float @select_fadd_fcmp_bad_13(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_13(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd nsz float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, -0.0
+ %B = fadd nsz float %x, %z
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+; Invalid identity constant for FP op
+define float @select_fadd_fcmp_bad_14(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fadd_fcmp_bad_14(
+; CHECK-NEXT: [[A:%.*]] = fcmp une float [[X:%.*]], -1.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fadd nsz float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[Y:%.*]], float [[B]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp une float %x, -1.0
+ %B = fadd nsz float %x, %z
+ %C = select i1 %A, float %y, float %B
+ ret float %C
+}
+
+define float @select_fmul_fcmp_bad(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fmul_fcmp_bad(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 3.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fmul nsz float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 3.0
+ %B = fmul nsz float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fmul_fcmp_bad_2(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fmul_fcmp_bad_2(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fmul float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 1.0
+ %B = fmul float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fmul_icmp_bad(float %x, float %y, float %z, i32 %k) {
+; CHECK-LABEL: @select_fmul_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[K:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = fmul float [[X:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = icmp eq i32 %k, 0
+ %B = fmul float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fmul_icmp_bad_2(float %x, float %y, float %z, i32 %k) {
+; CHECK-LABEL: @select_fmul_icmp_bad_2(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[K:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = fmul nsz float [[X:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = icmp eq i32 %k, 0
+ %B = fmul nsz float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fdiv_fcmp_bad(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fdiv_fcmp_bad(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fdiv float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 1.0
+ %B = fdiv float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fdiv_fcmp_bad_2(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fdiv_fcmp_bad_2(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 3.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fdiv nsz float [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 3.0
+ %B = fdiv nsz float %x, %z
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+; The transform is not valid when x = -0.0 and z = -0.0
+; (optimized code would return -0.0, but this returns +0.0).
+
+define float @select_fsub_fcmp_bad(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fsub_fcmp_bad(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fsub float [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 0.0
+ %B = fsub float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define float @select_fsub_fcmp_bad_2(float %x, float %y, float %z) {
+; CHECK-LABEL: @select_fsub_fcmp_bad_2(
+; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[B:%.*]] = fsub nsz float [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]]
+; CHECK-NEXT: ret float [[C]]
+;
+ %A = fcmp oeq float %x, 1.0
+ %B = fsub nsz float %z, %x
+ %C = select i1 %A, float %B, float %y
+ ret float %C
+}
+
+define i32 @select_sub_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sub_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = sub i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = sub i32 %x, %z
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sub_icmp_bad_2(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sub_icmp_bad_2(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[B:%.*]] = sub i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 1
+ %B = sub i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sub_icmp_bad_3(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sub_icmp_bad_3(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[B:%.*]] = sub i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ call void @use2(i1 %A)
+ %B = sub i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sub_icmp_4(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sub_icmp_4(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: call void @use2(i1 [[A]])
+; CHECK-NEXT: [[B:%.*]] = sub i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp ne i32 %x, 0
+ call void @use2(i1 %A)
+ %B = sub i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sub_icmp_bad_4(i32 %x, i32 %y, i32 %z, i32 %k) {
+; CHECK-LABEL: @select_sub_icmp_bad_4(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = sub i32 [[Z:%.*]], [[K:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = sub i32 %z, %k
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sub_icmp_bad_5(i32 %x, i32 %y, i32 %z, i32 %k) {
+; CHECK-LABEL: @select_sub_icmp_bad_5(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[K:%.*]]
+; CHECK-NEXT: [[B:%.*]] = sub i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, %k
+ %B = sub i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_shl_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_shl_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[B:%.*]] = shl i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 1
+ %B = shl i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_lshr_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_lshr_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[B:%.*]] = lshr i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 1
+ %B = lshr i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_ashr_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_ashr_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[B:%.*]] = ashr i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 1
+ %B = ashr i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_udiv_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_udiv_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[B:%.*]] = udiv i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 3
+ %B = udiv i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+define i32 @select_sdiv_icmp_bad(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_sdiv_icmp_bad(
+; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[B:%.*]] = sdiv i32 [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = icmp eq i32 %x, 3
+ %B = sdiv i32 %z, %x
+ %C = select i1 %A, i32 %B, i32 %y
+ ret i32 %C
+}
+
+!0 = !{!"branch_weights", i32 2, i32 10}
Added: llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,111 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl nuw nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_shl_of_true_val2(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val2(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl nuw nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %2, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
+; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 60
+ %2 = lshr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_lshr_of_true_val2(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val2(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, 60
+ %2 = lshr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %2, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
+; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, -2147483588
+ %2 = ashr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, -2147483588
+ %2 = ashr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %2, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/select-bitext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-bitext.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-bitext.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-bitext.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,619 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Widen a select of constants to eliminate an extend.
+
+define i16 @sel_sext_constants(i1 %cmp) {
+; CHECK-LABEL: @sel_sext_constants(
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i16 -1, i16 42
+; CHECK-NEXT: ret i16 [[EXT]]
+;
+ %sel = select i1 %cmp, i8 255, i8 42
+ %ext = sext i8 %sel to i16
+ ret i16 %ext
+}
+
+define i16 @sel_zext_constants(i1 %cmp) {
+; CHECK-LABEL: @sel_zext_constants(
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i16 255, i16 42
+; CHECK-NEXT: ret i16 [[EXT]]
+;
+ %sel = select i1 %cmp, i8 255, i8 42
+ %ext = zext i8 %sel to i16
+ ret i16 %ext
+}
+
+define double @sel_fpext_constants(i1 %cmp) {
+; CHECK-LABEL: @sel_fpext_constants(
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], double -2.550000e+02, double 4.200000e+01
+; CHECK-NEXT: ret double [[EXT]]
+;
+ %sel = select i1 %cmp, float -255.0, float 42.0
+ %ext = fpext float %sel to double
+ ret double %ext
+}
+
+; FIXME: We should not grow the size of the select in the next 4 cases.
+
+define i64 @sel_sext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @sel_sext(
+; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
+; CHECK-NEXT: ret i64 [[EXT]]
+;
+ %sel = select i1 %cmp, i32 %a, i32 42
+ %ext = sext i32 %sel to i64
+ ret i64 %ext
+}
+
+define <4 x i64> @sel_sext_vec(<4 x i32> %a, <4 x i1> %cmp) {
+; CHECK-LABEL: @sel_sext_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> [[A:%.*]] to <4 x i64>
+; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
+; CHECK-NEXT: ret <4 x i64> [[EXT]]
+;
+ %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
+ %ext = sext <4 x i32> %sel to <4 x i64>
+ ret <4 x i64> %ext
+}
+
+define i64 @sel_zext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @sel_zext(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
+; CHECK-NEXT: ret i64 [[EXT]]
+;
+ %sel = select i1 %cmp, i32 %a, i32 42
+ %ext = zext i32 %sel to i64
+ ret i64 %ext
+}
+
+define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) {
+; CHECK-LABEL: @sel_zext_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i32> [[A:%.*]] to <4 x i64>
+; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
+; CHECK-NEXT: ret <4 x i64> [[EXT]]
+;
+ %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
+ %ext = zext <4 x i32> %sel to <4 x i64>
+ ret <4 x i64> %ext
+}
+
+; FIXME: The next 18 tests cycle through trunc+select and {larger,smaller,equal} {sext,zext,fpext} {scalar,vector}.
+; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's probably the only
+; way to justify widening the select.
+
+define i64 @trunc_sel_larger_sext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_larger_sext(
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[A:%.*]] to i16
+; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i64
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
+; CHECK-NEXT: ret i64 [[EXT]]
+;
+ %trunc = trunc i32 %a to i16
+ %sel = select i1 %cmp, i16 %trunc, i16 42
+ %ext = sext i16 %sel to i64
+ ret i64 %ext
+}
+
+define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_larger_sext_vec(
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i32> [[A:%.*]] to <2 x i16>
+; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TRUNC]] to <2 x i64>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
+; CHECK-NEXT: ret <2 x i64> [[EXT]]
+;
+ %trunc = trunc <2 x i32> %a to <2 x i16>
+ %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
+ %ext = sext <2 x i16> %sel to <2 x i64>
+ ret <2 x i64> %ext
+}
+
+define i32 @trunc_sel_smaller_sext(i64 %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_smaller_sext(
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[A:%.*]] to i16
+; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP1]], i32 42
+; CHECK-NEXT: ret i32 [[EXT]]
+;
+ %trunc = trunc i64 %a to i16
+ %sel = select i1 %cmp, i16 %trunc, i16 42
+ %ext = sext i16 %sel to i32
+ ret i32 %ext
+}
+
+define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_smaller_sext_vec(
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i16>
+; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TRUNC]] to <2 x i32>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT: ret <2 x i32> [[EXT]]
+;
+ %trunc = trunc <2 x i64> %a to <2 x i16>
+ %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
+ %ext = sext <2 x i16> %sel to <2 x i32>
+ ret <2 x i32> %ext
+}
+
+define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_equal_sext(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A:%.*]], 16
+; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 16
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP2]], i32 42
+; CHECK-NEXT: ret i32 [[EXT]]
+;
+ %trunc = trunc i32 %a to i16
+ %sel = select i1 %cmp, i16 %trunc, i16 42
+ %ext = sext i16 %sel to i32
+ ret i32 %ext
+}
+
+define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_equal_sext_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[A:%.*]], <i32 16, i32 16>
+; CHECK-NEXT: [[TMP2:%.*]] = ashr exact <2 x i32> [[TMP1]], <i32 16, i32 16>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP2]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT: ret <2 x i32> [[EXT]]
+;
+ %trunc = trunc <2 x i32> %a to <2 x i16>
+ %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
+ %ext = sext <2 x i16> %sel to <2 x i32>
+ ret <2 x i32> %ext
+}
+
+define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_larger_zext(
+; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and i32 [[A:%.*]], 65535
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TRUNC_MASK]] to i64
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
+; CHECK-NEXT: ret i64 [[EXT]]
+;
+ %trunc = trunc i32 %a to i16
+ %sel = select i1 %cmp, i16 %trunc, i16 42
+ %ext = zext i16 %sel to i64
+ ret i64 %ext
+}
+
+define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_larger_zext_vec(
+; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and <2 x i32> [[A:%.*]], <i32 65535, i32 65535>
+; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[TRUNC_MASK]] to <2 x i64>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
+; CHECK-NEXT: ret <2 x i64> [[EXT]]
+;
+ %trunc = trunc <2 x i32> %a to <2 x i16>
+ %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
+ %ext = zext <2 x i16> %sel to <2 x i64>
+ ret <2 x i64> %ext
+}
+
+define i32 @trunc_sel_smaller_zext(i64 %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_smaller_zext(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A:%.*]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65535
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP2]], i32 42
+; CHECK-NEXT: ret i32 [[EXT]]
+;
+ %trunc = trunc i64 %a to i16
+ %sel = select i1 %cmp, i16 %trunc, i16 42
+ %ext = zext i16 %sel to i32
+ ret i32 %ext
+}
+
+define <2 x i32> @trunc_sel_smaller_zext_vec(<2 x i64> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_smaller_zext_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 65535, i32 65535>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP2]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT: ret <2 x i32> [[EXT]]
+;
+ %trunc = trunc <2 x i64> %a to <2 x i16>
+ %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
+ %ext = zext <2 x i16> %sel to <2 x i32>
+ ret <2 x i32> %ext
+}
+
+define i32 @trunc_sel_equal_zext(i32 %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_equal_zext(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 65535
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP1]], i32 42
+; CHECK-NEXT: ret i32 [[EXT]]
+;
+ %trunc = trunc i32 %a to i16
+ %sel = select i1 %cmp, i16 %trunc, i16 42
+ %ext = zext i16 %sel to i32
+ ret i32 %ext
+}
+
+define <2 x i32> @trunc_sel_equal_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_equal_zext_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 65535, i32 65535>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT: ret <2 x i32> [[EXT]]
+;
+ %trunc = trunc <2 x i32> %a to <2 x i16>
+ %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
+ %ext = zext <2 x i16> %sel to <2 x i32>
+ ret <2 x i32> %ext
+}
+
+define double @trunc_sel_larger_fpext(float %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_larger_fpext(
+; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float [[A:%.*]] to half
+; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to double
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], double [[TMP1]], double 4.200000e+01
+; CHECK-NEXT: ret double [[EXT]]
+;
+ %trunc = fptrunc float %a to half
+ %sel = select i1 %cmp, half %trunc, half 42.0
+ %ext = fpext half %sel to double
+ ret double %ext
+}
+
+define <2 x double> @trunc_sel_larger_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_larger_fpext_vec(
+; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> [[A:%.*]] to <2 x half>
+; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x double>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x double> [[TMP1]], <2 x double> <double 4.200000e+01, double 4.300000e+01>
+; CHECK-NEXT: ret <2 x double> [[EXT]]
+;
+ %trunc = fptrunc <2 x float> %a to <2 x half>
+ %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
+ %ext = fpext <2 x half> %sel to <2 x double>
+ ret <2 x double> %ext
+}
+
+define float @trunc_sel_smaller_fpext(double %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_smaller_fpext(
+; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[A:%.*]] to half
+; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], float [[TMP1]], float 4.200000e+01
+; CHECK-NEXT: ret float [[EXT]]
+;
+ %trunc = fptrunc double %a to half
+ %sel = select i1 %cmp, half %trunc, half 42.0
+ %ext = fpext half %sel to float
+ ret float %ext
+}
+
+define <2 x float> @trunc_sel_smaller_fpext_vec(<2 x double> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_smaller_fpext_vec(
+; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x double> [[A:%.*]] to <2 x half>
+; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
+; CHECK-NEXT: ret <2 x float> [[EXT]]
+;
+ %trunc = fptrunc <2 x double> %a to <2 x half>
+ %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
+ %ext = fpext <2 x half> %sel to <2 x float>
+ ret <2 x float> %ext
+}
+
+define float @trunc_sel_equal_fpext(float %a, i1 %cmp) {
+; CHECK-LABEL: @trunc_sel_equal_fpext(
+; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float [[A:%.*]] to half
+; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
+; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], float [[TMP1]], float 4.200000e+01
+; CHECK-NEXT: ret float [[EXT]]
+;
+ %trunc = fptrunc float %a to half
+ %sel = select i1 %cmp, half %trunc, half 42.0
+ %ext = fpext half %sel to float
+ ret float %ext
+}
+
+define <2 x float> @trunc_sel_equal_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
+; CHECK-LABEL: @trunc_sel_equal_fpext_vec(
+; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> [[A:%.*]] to <2 x half>
+; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
+; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
+; CHECK-NEXT: ret <2 x float> [[EXT]]
+;
+ %trunc = fptrunc <2 x float> %a to <2 x half>
+ %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
+ %ext = fpext <2 x half> %sel to <2 x float>
+ ret <2 x float> %ext
+}
+
+define i32 @test_sext1(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_sext1(
+; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = sext i1 %cca to i32
+ %r = select i1 %ccb, i32 %ccax, i32 0
+ ret i32 %r
+}
+
+define i32 @test_sext2(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_sext2(
+; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = sext i1 %cca to i32
+ %r = select i1 %ccb, i32 -1, i32 %ccax
+ ret i32 %r
+}
+
+define i32 @test_sext3(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_sext3(
+; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
+; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = sext i1 %cca to i32
+ %r = select i1 %ccb, i32 0, i32 %ccax
+ ret i32 %r
+}
+
+define i32 @test_sext4(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_sext4(
+; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
+; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = sext i1 %cca to i32
+ %r = select i1 %ccb, i32 %ccax, i32 -1
+ ret i32 %r
+}
+
+define i32 @test_zext1(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_zext1(
+; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = zext i1 %cca to i32
+ %r = select i1 %ccb, i32 %ccax, i32 0
+ ret i32 %r
+}
+
+define i32 @test_zext2(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_zext2(
+; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = zext i1 %cca to i32
+ %r = select i1 %ccb, i32 1, i32 %ccax
+ ret i32 %r
+}
+
+define i32 @test_zext3(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_zext3(
+; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
+; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = zext i1 %cca to i32
+ %r = select i1 %ccb, i32 0, i32 %ccax
+ ret i32 %r
+}
+
+define i32 @test_zext4(i1 %cca, i1 %ccb) {
+; CHECK-LABEL: @test_zext4(
+; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
+; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[NOT_CCB]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %ccax = zext i1 %cca to i32
+ %r = select i1 %ccb, i32 %ccax, i32 1
+ ret i32 %r
+}
+
+define i32 @test_negative_sext(i1 %a, i1 %cc) {
+; CHECK-LABEL: @test_negative_sext(
+; CHECK-NEXT: [[A_EXT:%.*]] = sext i1 [[A:%.*]] to i32
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 1
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %a.ext = sext i1 %a to i32
+ %r = select i1 %cc, i32 %a.ext, i32 1
+ ret i32 %r
+}
+
+define i32 @test_negative_zext(i1 %a, i1 %cc) {
+; CHECK-LABEL: @test_negative_zext(
+; CHECK-NEXT: [[A_EXT:%.*]] = zext i1 [[A:%.*]] to i32
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 -1
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %a.ext = zext i1 %a to i32
+ %r = select i1 %cc, i32 %a.ext, i32 -1
+ ret i32 %r
+}
+
+define i32 @test_bits_sext(i8 %a, i1 %cc) {
+; CHECK-LABEL: @test_bits_sext(
+; CHECK-NEXT: [[A_EXT:%.*]] = sext i8 [[A:%.*]] to i32
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 -128
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %a.ext = sext i8 %a to i32
+ %r = select i1 %cc, i32 %a.ext, i32 -128
+ ret i32 %r
+}
+
+define i32 @test_bits_zext(i8 %a, i1 %cc) {
+; CHECK-LABEL: @test_bits_zext(
+; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 255
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %a.ext = zext i8 %a to i32
+ %r = select i1 %cc, i32 %a.ext, i32 255
+ ret i32 %r
+}
+
+define i32 @test_op_op(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @test_op_op(
+; CHECK-NEXT: [[CCA:%.*]] = icmp sgt i32 [[A:%.*]], 0
+; CHECK-NEXT: [[CCB:%.*]] = icmp sgt i32 [[B:%.*]], 0
+; CHECK-NEXT: [[CCC:%.*]] = icmp sgt i32 [[C:%.*]], 0
+; CHECK-NEXT: [[R_V:%.*]] = select i1 [[CCC]], i1 [[CCA]], i1 [[CCB]]
+; CHECK-NEXT: [[R:%.*]] = sext i1 [[R_V]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %cca = icmp sgt i32 %a, 0
+ %ccax = sext i1 %cca to i32
+ %ccb = icmp sgt i32 %b, 0
+ %ccbx = sext i1 %ccb to i32
+ %ccc = icmp sgt i32 %c, 0
+ %r = select i1 %ccc, i32 %ccax, i32 %ccbx
+ ret i32 %r
+}
+
+define <2 x i32> @test_vectors_sext(<2 x i1> %cca, <2 x i1> %ccb) {
+; CHECK-LABEL: @test_vectors_sext(
+; CHECK-NEXT: [[NARROW:%.*]] = and <2 x i1> [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %ccax = sext <2 x i1> %cca to <2 x i32>
+ %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @test_vectors_sext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {
+; CHECK-LABEL: @test_vectors_sext_nonsplat(
+; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> <i1 false, i1 true>
+; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %ccax = sext <2 x i1> %cca to <2 x i32>
+ %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 -1>
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @test_vectors_zext(<2 x i1> %cca, <2 x i1> %ccb) {
+; CHECK-LABEL: @test_vectors_zext(
+; CHECK-NEXT: [[NARROW:%.*]] = and <2 x i1> [[CCB:%.*]], [[CCA:%.*]]
+; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %ccax = zext <2 x i1> %cca to <2 x i32>
+ %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @test_vectors_zext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {
+; CHECK-LABEL: @test_vectors_zext_nonsplat(
+; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> <i1 true, i1 false>
+; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %ccax = zext <2 x i1> %cca to <2 x i32>
+ %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 1, i32 0>
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {
+; CHECK-LABEL: @scalar_select_of_vectors_sext(
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %ccax = sext <2 x i1> %cca to <2 x i32>
+ %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @scalar_select_of_vectors_zext(<2 x i1> %cca, i1 %ccb) {
+; CHECK-LABEL: @scalar_select_of_vectors_zext(
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %ccax = zext <2 x i1> %cca to <2 x i32>
+ %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
+ ret <2 x i32> %r
+}
+
+define i32 @sext_true_val_must_be_all_ones(i1 %x) {
+; CHECK-LABEL: @sext_true_val_must_be_all_ones(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 -1, i32 42, !prof !0
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ext = sext i1 %x to i32
+ %sel = select i1 %x, i32 %ext, i32 42, !prof !0
+ ret i32 %sel
+}
+
+define <2 x i32> @sext_true_val_must_be_all_ones_vec(<2 x i1> %x) {
+; CHECK-LABEL: @sext_true_val_must_be_all_ones_vec(
+; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 42, i32 12>, !prof !0
+; CHECK-NEXT: ret <2 x i32> [[SEL]]
+;
+ %ext = sext <2 x i1> %x to <2 x i32>
+ %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0
+ ret <2 x i32> %sel
+}
+
+define i32 @zext_true_val_must_be_one(i1 %x) {
+; CHECK-LABEL: @zext_true_val_must_be_one(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 1, i32 42, !prof !0
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ext = zext i1 %x to i32
+ %sel = select i1 %x, i32 %ext, i32 42, !prof !0
+ ret i32 %sel
+}
+
+define <2 x i32> @zext_true_val_must_be_one_vec(<2 x i1> %x) {
+; CHECK-LABEL: @zext_true_val_must_be_one_vec(
+; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 42, i32 12>, !prof !0
+; CHECK-NEXT: ret <2 x i32> [[SEL]]
+;
+ %ext = zext <2 x i1> %x to <2 x i32>
+ %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0
+ ret <2 x i32> %sel
+}
+
+define i32 @sext_false_val_must_be_zero(i1 %x) {
+; CHECK-LABEL: @sext_false_val_must_be_zero(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 42, i32 0, !prof !0
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ext = sext i1 %x to i32
+ %sel = select i1 %x, i32 42, i32 %ext, !prof !0
+ ret i32 %sel
+}
+
+define <2 x i32> @sext_false_val_must_be_zero_vec(<2 x i1> %x) {
+; CHECK-LABEL: @sext_false_val_must_be_zero_vec(
+; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0
+; CHECK-NEXT: ret <2 x i32> [[SEL]]
+;
+ %ext = sext <2 x i1> %x to <2 x i32>
+ %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0
+ ret <2 x i32> %sel
+}
+
+define i32 @zext_false_val_must_be_zero(i1 %x) {
+; CHECK-LABEL: @zext_false_val_must_be_zero(
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 42, i32 0, !prof !0
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ext = zext i1 %x to i32
+ %sel = select i1 %x, i32 42, i32 %ext, !prof !0
+ ret i32 %sel
+}
+
+define <2 x i32> @zext_false_val_must_be_zero_vec(<2 x i1> %x) {
+; CHECK-LABEL: @zext_false_val_must_be_zero_vec(
+; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0
+; CHECK-NEXT: ret <2 x i32> [[SEL]]
+;
+ %ext = zext <2 x i1> %x to <2 x i32>
+ %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0
+ ret <2 x i32> %sel
+}
+
+!0 = !{!"branch_weights", i32 3, i32 5}
+
Added: llvm/trunk/test/Transforms/InstCombine/select-cmp-br.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-cmp-br.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-cmp-br.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-cmp-br.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,263 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; Replace a 'select' with 'or' in 'select - cmp [eq|ne] - br' sequence
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+%struct.S = type { i64*, i32, i32 }
+%C = type <{ %struct.S }>
+
+declare void @bar(%struct.S*)
+declare void @foobar()
+
+define void @test1(%C* %arg) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
+; CHECK-NEXT: [[M:%.*]] = load i64*, i64** [[TMP]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
+; CHECK-NEXT: [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
+; CHECK-NEXT: [[NOT_TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
+; CHECK-NEXT: [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
+; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP71]], [[NOT_TMP5]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: ret void
+; CHECK: bb8:
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
+; CHECK-NEXT: tail call void @bar(%struct.S* [[TMP9]])
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb10:
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, i64* [[M]], i64 9
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64* [[TMP2]] to i64 (%C*)**
+; CHECK-NEXT: [[TMP4:%.*]] = load i64 (%C*)*, i64 (%C*)** [[TMP3]], align 8
+; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
+; CHECK-NEXT: br label [[BB]]
+;
+entry:
+ %tmp = getelementptr inbounds %C, %C* %arg, i64 0, i32 0, i32 0
+ %m = load i64*, i64** %tmp, align 8
+ %tmp1 = getelementptr inbounds %C, %C* %arg, i64 1, i32 0, i32 0
+ %n = load i64*, i64** %tmp1, align 8
+ %tmp2 = getelementptr inbounds i64, i64* %m, i64 9
+ %tmp3 = bitcast i64* %tmp2 to i64 (%C*)**
+ %tmp4 = load i64 (%C*)*, i64 (%C*)** %tmp3, align 8
+ %tmp5 = icmp eq i64* %m, %n
+ %tmp6 = select i1 %tmp5, %C* %arg, %C* null
+ %tmp7 = icmp eq %C* %tmp6, null
+ br i1 %tmp7, label %bb10, label %bb8
+
+bb: ; preds = %bb10, %bb8
+ ret void
+
+bb8: ; preds = %entry
+ %tmp9 = getelementptr inbounds %C, %C* %tmp6, i64 0, i32 0
+ tail call void @bar(%struct.S* %tmp9)
+ br label %bb
+
+bb10: ; preds = %entry
+ %tmp11 = tail call i64 %tmp4(%C* %arg)
+ br label %bb
+}
+
+define void @test2(%C* %arg) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
+; CHECK-NEXT: [[M:%.*]] = load i64*, i64** [[TMP]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
+; CHECK-NEXT: [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64* [[M]], [[N]]
+; CHECK-NEXT: [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
+; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP71]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: ret void
+; CHECK: bb8:
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
+; CHECK-NEXT: tail call void @bar(%struct.S* [[TMP9]])
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb10:
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, i64* [[M]], i64 9
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64* [[TMP2]] to i64 (%C*)**
+; CHECK-NEXT: [[TMP4:%.*]] = load i64 (%C*)*, i64 (%C*)** [[TMP3]], align 8
+; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
+; CHECK-NEXT: br label [[BB]]
+;
+entry:
+ %tmp = getelementptr inbounds %C, %C* %arg, i64 0, i32 0, i32 0
+ %m = load i64*, i64** %tmp, align 8
+ %tmp1 = getelementptr inbounds %C, %C* %arg, i64 1, i32 0, i32 0
+ %n = load i64*, i64** %tmp1, align 8
+ %tmp2 = getelementptr inbounds i64, i64* %m, i64 9
+ %tmp3 = bitcast i64* %tmp2 to i64 (%C*)**
+ %tmp4 = load i64 (%C*)*, i64 (%C*)** %tmp3, align 8
+ %tmp5 = icmp eq i64* %m, %n
+ %tmp6 = select i1 %tmp5, %C* null, %C* %arg
+ %tmp7 = icmp eq %C* %tmp6, null
+ br i1 %tmp7, label %bb10, label %bb8
+
+bb: ; preds = %bb10, %bb8
+ ret void
+
+bb8: ; preds = %entry
+ %tmp9 = getelementptr inbounds %C, %C* %tmp6, i64 0, i32 0
+ tail call void @bar(%struct.S* %tmp9)
+ br label %bb
+
+bb10: ; preds = %entry
+ %tmp11 = tail call i64 %tmp4(%C* %arg)
+ br label %bb
+}
+
+define void @test3(%C* %arg) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
+; CHECK-NEXT: [[M:%.*]] = load i64*, i64** [[TMP]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
+; CHECK-NEXT: [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
+; CHECK-NEXT: [[NOT_TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
+; CHECK-NEXT: [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
+; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP71]], [[NOT_TMP5]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: ret void
+; CHECK: bb8:
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
+; CHECK-NEXT: tail call void @bar(%struct.S* [[TMP9]])
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb10:
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, i64* [[M]], i64 9
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64* [[TMP2]] to i64 (%C*)**
+; CHECK-NEXT: [[TMP4:%.*]] = load i64 (%C*)*, i64 (%C*)** [[TMP3]], align 8
+; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
+; CHECK-NEXT: br label [[BB]]
+;
+entry:
+ %tmp = getelementptr inbounds %C, %C* %arg, i64 0, i32 0, i32 0
+ %m = load i64*, i64** %tmp, align 8
+ %tmp1 = getelementptr inbounds %C, %C* %arg, i64 1, i32 0, i32 0
+ %n = load i64*, i64** %tmp1, align 8
+ %tmp2 = getelementptr inbounds i64, i64* %m, i64 9
+ %tmp3 = bitcast i64* %tmp2 to i64 (%C*)**
+ %tmp4 = load i64 (%C*)*, i64 (%C*)** %tmp3, align 8
+ %tmp5 = icmp eq i64* %m, %n
+ %tmp6 = select i1 %tmp5, %C* %arg, %C* null
+ %tmp7 = icmp ne %C* %tmp6, null
+ br i1 %tmp7, label %bb8, label %bb10
+
+bb: ; preds = %bb10, %bb8
+ ret void
+
+bb8: ; preds = %entry
+ %tmp9 = getelementptr inbounds %C, %C* %tmp6, i64 0, i32 0
+ tail call void @bar(%struct.S* %tmp9)
+ br label %bb
+
+bb10: ; preds = %entry
+ %tmp11 = tail call i64 %tmp4(%C* %arg)
+ br label %bb
+}
+
+define void @test4(%C* %arg) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
+; CHECK-NEXT: [[M:%.*]] = load i64*, i64** [[TMP]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
+; CHECK-NEXT: [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64* [[M]], [[N]]
+; CHECK-NEXT: [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
+; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP71]]
+; CHECK-NEXT: br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: ret void
+; CHECK: bb8:
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
+; CHECK-NEXT: tail call void @bar(%struct.S* [[TMP9]])
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb10:
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, i64* [[M]], i64 9
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64* [[TMP2]] to i64 (%C*)**
+; CHECK-NEXT: [[TMP4:%.*]] = load i64 (%C*)*, i64 (%C*)** [[TMP3]], align 8
+; CHECK-NEXT: [[TMP11:%.*]] = tail call i64 [[TMP4]](%C* [[ARG]])
+; CHECK-NEXT: br label [[BB]]
+;
+entry:
+ %tmp = getelementptr inbounds %C, %C* %arg, i64 0, i32 0, i32 0
+ %m = load i64*, i64** %tmp, align 8
+ %tmp1 = getelementptr inbounds %C, %C* %arg, i64 1, i32 0, i32 0
+ %n = load i64*, i64** %tmp1, align 8
+ %tmp2 = getelementptr inbounds i64, i64* %m, i64 9
+ %tmp3 = bitcast i64* %tmp2 to i64 (%C*)**
+ %tmp4 = load i64 (%C*)*, i64 (%C*)** %tmp3, align 8
+ %tmp5 = icmp eq i64* %m, %n
+ %tmp6 = select i1 %tmp5, %C* null, %C* %arg
+ %tmp7 = icmp ne %C* %tmp6, null
+ br i1 %tmp7, label %bb8, label %bb10
+
+bb: ; preds = %bb10, %bb8
+ ret void
+
+bb8: ; preds = %entry
+ %tmp9 = getelementptr inbounds %C, %C* %tmp6, i64 0, i32 0
+ tail call void @bar(%struct.S* %tmp9)
+ br label %bb
+
+bb10: ; preds = %entry
+ %tmp11 = tail call i64 %tmp4(%C* %arg)
+ br label %bb
+}
+
+define void @test5(%C* %arg, i1 %arg1) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP21:%.*]] = icmp eq %C* [[ARG:%.*]], null
+; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP21]], [[ARG1:%.*]]
+; CHECK-NEXT: br i1 [[TMP2]], label [[BB5:%.*]], label [[BB3:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: ret void
+; CHECK: bb3:
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG]], i64 0, i32 0
+; CHECK-NEXT: tail call void @bar(%struct.S* [[TMP4]])
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb5:
+; CHECK-NEXT: tail call void @foobar()
+; CHECK-NEXT: br label [[BB]]
+;
+entry:
+ %tmp = select i1 %arg1, %C* null, %C* %arg
+ %tmp2 = icmp ne %C* %tmp, null
+ br i1 %tmp2, label %bb3, label %bb5
+
+bb: ; preds = %bb5, %bb3
+ ret void
+
+bb3: ; preds = %entry
+ %tmp4 = getelementptr inbounds %C, %C* %tmp, i64 0, i32 0
+ tail call void @bar(%struct.S* %tmp4)
+ br label %bb
+
+bb5: ; preds = %entry
+ tail call void @foobar()
+ br label %bb
+}
+
+; Negative test. Must not trigger the select-cmp-br combine because the result
+; of the select is used in both flows following the br (the special case where
+; the conditional branch has the same target for both flows).
+define i32 @test6(i32 %arg, i1 %arg1) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 false, label [[BB:%.*]], label [[BB]]
+; CHECK: bb:
+; CHECK-NEXT: [[TMP:%.*]] = select i1 [[ARG1:%.*]], i32 [[ARG:%.*]], i32 0
+; CHECK-NEXT: ret i32 [[TMP]]
+;
+entry:
+ %tmp = select i1 %arg1, i32 %arg, i32 0
+ %tmp2 = icmp eq i32 %tmp, 0
+ br i1 %tmp2, label %bb, label %bb
+
+bb: ; preds = %entry, %entry
+ ret i32 %tmp
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,459 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+; This test is to verify that the instruction combiner is able to fold
+; a cttz/ctlz followed by a icmp + select into a single cttz/ctlz with
+; the 'is_zero_undef' flag cleared.
+
+define i16 @test1(i16 %x) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: ret i16 [[TMP1]]
+;
+ %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+ %tobool = icmp ne i16 %x, 0
+ %cond = select i1 %tobool, i16 %ct, i16 16
+ ret i16 %cond
+}
+
+define i32 @test2(i32 %x) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i32 %ct, i32 32
+ ret i32 %cond
+}
+
+define i64 @test3(i64 %x) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+ %tobool = icmp ne i64 %x, 0
+ %cond = select i1 %tobool, i64 %ct, i64 64
+ ret i64 %cond
+}
+
+define i16 @test4(i16 %x) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: ret i16 [[TMP1]]
+;
+ %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+ %tobool = icmp eq i16 %x, 0
+ %cond = select i1 %tobool, i16 16, i16 %ct
+ ret i16 %cond
+}
+
+define i32 @test5(i32 %x) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+ %tobool = icmp eq i32 %x, 0
+ %cond = select i1 %tobool, i32 32, i32 %ct
+ ret i32 %cond
+}
+
+define i64 @test6(i64 %x) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+ %tobool = icmp eq i64 %x, 0
+ %cond = select i1 %tobool, i64 64, i64 %ct
+ ret i64 %cond
+}
+
+define i16 @test1b(i16 %x) {
+; CHECK-LABEL: @test1b(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: ret i16 [[TMP1]]
+;
+ %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+ %tobool = icmp ne i16 %x, 0
+ %cond = select i1 %tobool, i16 %ct, i16 16
+ ret i16 %cond
+}
+
+define i32 @test2b(i32 %x) {
+; CHECK-LABEL: @test2b(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i32 %ct, i32 32
+ ret i32 %cond
+}
+
+define i64 @test3b(i64 %x) {
+; CHECK-LABEL: @test3b(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+ %tobool = icmp ne i64 %x, 0
+ %cond = select i1 %tobool, i64 %ct, i64 64
+ ret i64 %cond
+}
+
+define i16 @test4b(i16 %x) {
+; CHECK-LABEL: @test4b(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: ret i16 [[TMP1]]
+;
+ %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+ %tobool = icmp eq i16 %x, 0
+ %cond = select i1 %tobool, i16 16, i16 %ct
+ ret i16 %cond
+}
+
+define i32 @test5b(i32 %x) {
+; CHECK-LABEL: @test5b(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: ret i32 [[TMP0]]
+;
+entry:
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ %tobool = icmp eq i32 %x, 0
+ %cond = select i1 %tobool, i32 32, i32 %ct
+ ret i32 %cond
+}
+
+define i64 @test6b(i64 %x) {
+; CHECK-LABEL: @test6b(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+ %tobool = icmp eq i64 %x, 0
+ %cond = select i1 %tobool, i64 64, i64 %ct
+ ret i64 %cond
+}
+
+define i32 @test1c(i16 %x) {
+; CHECK-LABEL: @test1c(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+ %cast2 = zext i16 %ct to i32
+ %tobool = icmp ne i16 %x, 0
+ %cond = select i1 %tobool, i32 %cast2, i32 16
+ ret i32 %cond
+}
+
+define i64 @test2c(i16 %x) {
+; CHECK-LABEL: @test2c(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
+;
+ %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
+ %conv = zext i16 %ct to i64
+ %tobool = icmp ne i16 %x, 0
+ %cond = select i1 %tobool, i64 %conv, i64 16
+ ret i64 %cond
+}
+
+define i64 @test3c(i32 %x) {
+; CHECK-LABEL: @test3c(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
+;
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ %conv = zext i32 %ct to i64
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i64 %conv, i64 32
+ ret i64 %cond
+}
+
+define i32 @test4c(i16 %x) {
+; CHECK-LABEL: @test4c(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+ %cast = zext i16 %ct to i32
+ %tobool = icmp ne i16 %x, 0
+ %cond = select i1 %tobool, i32 %cast, i32 16
+ ret i32 %cond
+}
+
+define i64 @test5c(i16 %x) {
+; CHECK-LABEL: @test5c(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
+;
+ %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+ %cast = zext i16 %ct to i64
+ %tobool = icmp ne i16 %x, 0
+ %cond = select i1 %tobool, i64 %cast, i64 16
+ ret i64 %cond
+}
+
+define i64 @test6c(i32 %x) {
+; CHECK-LABEL: @test6c(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
+;
+ %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+ %cast = zext i32 %ct to i64
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i64 %cast, i64 32
+ ret i64 %cond
+}
+
+define i16 @test1d(i64 %x) {
+; CHECK-LABEL: @test1d(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i16
+; CHECK-NEXT: ret i16 [[TMP2]]
+;
+ %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+ %conv = trunc i64 %ct to i16
+ %tobool = icmp ne i64 %x, 0
+ %cond = select i1 %tobool, i16 %conv, i16 64
+ ret i16 %cond
+}
+
+define i32 @test2d(i64 %x) {
+; CHECK-LABEL: @test2d(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
+ %cast = trunc i64 %ct to i32
+ %tobool = icmp ne i64 %x, 0
+ %cond = select i1 %tobool, i32 %cast, i32 64
+ ret i32 %cond
+}
+
+define i16 @test3d(i32 %x) {
+; CHECK-LABEL: @test3d(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
+; CHECK-NEXT: ret i16 [[TMP2]]
+;
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ %cast = trunc i32 %ct to i16
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i16 %cast, i16 32
+ ret i16 %cond
+}
+
+define i16 @test4d(i64 %x) {
+; CHECK-LABEL: @test4d(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i16
+; CHECK-NEXT: ret i16 [[TMP2]]
+;
+ %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+ %cast = trunc i64 %ct to i16
+ %tobool = icmp ne i64 %x, 0
+ %cond = select i1 %tobool, i16 %cast, i16 64
+ ret i16 %cond
+}
+
+define i32 @test5d(i64 %x) {
+; CHECK-LABEL: @test5d(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range !2
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+ %cast = trunc i64 %ct to i32
+ %tobool = icmp ne i64 %x, 0
+ %cond = select i1 %tobool, i32 %cast, i32 64
+ ret i32 %cond
+}
+
+define i16 @test6d(i32 %x) {
+; CHECK-LABEL: @test6d(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
+; CHECK-NEXT: ret i16 [[TMP2]]
+;
+ %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+ %cast = trunc i32 %ct to i16
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i16 %cast, i16 32
+ ret i16 %cond
+}
+
+define i64 @select_bug1(i32 %x) {
+; CHECK-LABEL: @select_bug1(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[TMP2]]
+;
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ %conv = zext i32 %ct to i64
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i64 %conv, i64 32
+ ret i64 %cond
+}
+
+define i16 @select_bug2(i32 %x) {
+; CHECK-LABEL: @select_bug2(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
+; CHECK-NEXT: ret i16 [[TMP2]]
+;
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ %conv = trunc i32 %ct to i16
+ %tobool = icmp ne i32 %x, 0
+ %cond = select i1 %tobool, i16 %conv, i16 32
+ ret i16 %cond
+}
+
+define i128 @test7(i128 %x) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i128 @llvm.ctlz.i128(i128 [[X:%.*]], i1 false), !range !3
+; CHECK-NEXT: ret i128 [[TMP1]]
+;
+ %ct = tail call i128 @llvm.ctlz.i128(i128 %x, i1 true)
+ %tobool = icmp ne i128 %x, 0
+ %cond = select i1 %tobool, i128 %ct, i128 128
+ ret i128 %cond
+}
+
+define i128 @test8(i128 %x) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i128 @llvm.cttz.i128(i128 [[X:%.*]], i1 false), !range !3
+; CHECK-NEXT: ret i128 [[TMP1]]
+;
+ %ct = tail call i128 @llvm.cttz.i128(i128 %x, i1 true)
+ %tobool = icmp ne i128 %x, 0
+ %cond = select i1 %tobool, i128 %ct, i128 128
+ ret i128 %cond
+}
+
+define i32 @test_ctlz_not_bw(i32 %x) {
+; CHECK-LABEL: @test_ctlz_not_bw(
+; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range !1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 123, i32 [[CT]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+ %cmp = icmp ne i32 %x, 0
+ %res = select i1 %cmp, i32 %ct, i32 123
+ ret i32 %res
+}
+
+define i32 @test_ctlz_not_bw_multiuse(i32 %x) {
+; CHECK-LABEL: @test_ctlz_not_bw_multiuse(
+; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 123, i32 [[CT]]
+; CHECK-NEXT: [[RES:%.*]] = or i32 [[SEL]], [[CT]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+ %cmp = icmp ne i32 %x, 0
+ %sel = select i1 %cmp, i32 %ct, i32 123
+ %res = or i32 %sel, %ct
+ ret i32 %res
+}
+
+define i32 @test_cttz_not_bw(i32 %x) {
+; CHECK-LABEL: @test_cttz_not_bw(
+; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range !1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 123, i32 [[CT]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ %cmp = icmp ne i32 %x, 0
+ %res = select i1 %cmp, i32 %ct, i32 123
+ ret i32 %res
+}
+
+define i32 @test_cttz_not_bw_multiuse(i32 %x) {
+; CHECK-LABEL: @test_cttz_not_bw_multiuse(
+; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 123, i32 [[CT]]
+; CHECK-NEXT: [[RES:%.*]] = or i32 [[SEL]], [[CT]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ %cmp = icmp ne i32 %x, 0
+ %sel = select i1 %cmp, i32 %ct, i32 123
+ %res = or i32 %sel, %ct
+ ret i32 %res
+}
+
+define <2 x i32> @test_ctlz_bw_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test_ctlz_bw_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false)
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %ct = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true)
+ %cmp = icmp ne <2 x i32> %x, zeroinitializer
+ %res = select <2 x i1> %cmp, <2 x i32> %ct, <2 x i32> <i32 32, i32 32>
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_ctlz_not_bw_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test_ctlz_not_bw_vec(
+; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer
+; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> [[CT]]
+; CHECK-NEXT: ret <2 x i32> [[RES]]
+;
+ %ct = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 false)
+ %cmp = icmp ne <2 x i32> %x, zeroinitializer
+ %res = select <2 x i1> %cmp, <2 x i32> %ct, <2 x i32> <i32 0, i32 0>
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_cttz_bw_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test_cttz_bw_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false)
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %ct = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true)
+ %cmp = icmp ne <2 x i32> %x, zeroinitializer
+ %res = select <2 x i1> %cmp, <2 x i32> %ct, <2 x i32> <i32 32, i32 32>
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_cttz_not_bw_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test_cttz_not_bw_vec(
+; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer
+; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> [[CT]]
+; CHECK-NEXT: ret <2 x i32> [[RES]]
+;
+ %ct = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 false)
+ %cmp = icmp ne <2 x i32> %x, zeroinitializer
+ %res = select <2 x i1> %cmp, <2 x i32> %ct, <2 x i32> <i32 0, i32 0>
+ ret <2 x i32> %res
+}
+
+declare i16 @llvm.ctlz.i16(i16, i1)
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i128 @llvm.ctlz.i128(i128, i1)
+declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1)
+declare i16 @llvm.cttz.i16(i16, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
+declare i128 @llvm.cttz.i128(i128, i1)
+declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)
Added: llvm/trunk/test/Transforms/InstCombine/select-cmpxchg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-cmpxchg.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-cmpxchg.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-cmpxchg.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,39 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i64 @cmpxchg_0(i64* %ptr, i64 %compare, i64 %new_value) {
+; CHECK-LABEL: @cmpxchg_0(
+; CHECK-NEXT: %tmp0 = cmpxchg i64* %ptr, i64 %compare, i64 %new_value seq_cst seq_cst
+; CHECK-NEXT: %tmp2 = extractvalue { i64, i1 } %tmp0, 0
+; CHECK-NEXT: ret i64 %tmp2
+;
+ %tmp0 = cmpxchg i64* %ptr, i64 %compare, i64 %new_value seq_cst seq_cst
+ %tmp1 = extractvalue { i64, i1 } %tmp0, 1
+ %tmp2 = extractvalue { i64, i1 } %tmp0, 0
+ %tmp3 = select i1 %tmp1, i64 %compare, i64 %tmp2
+ ret i64 %tmp3
+}
+
+define i64 @cmpxchg_1(i64* %ptr, i64 %compare, i64 %new_value) {
+; CHECK-LABEL: @cmpxchg_1(
+; CHECK-NEXT: %tmp0 = cmpxchg i64* %ptr, i64 %compare, i64 %new_value seq_cst seq_cst
+; CHECK-NEXT: ret i64 %compare
+;
+ %tmp0 = cmpxchg i64* %ptr, i64 %compare, i64 %new_value seq_cst seq_cst
+ %tmp1 = extractvalue { i64, i1 } %tmp0, 1
+ %tmp2 = extractvalue { i64, i1 } %tmp0, 0
+ %tmp3 = select i1 %tmp1, i64 %tmp2, i64 %compare
+ ret i64 %tmp3
+}
+
+define i64 @cmpxchg_2(i64* %ptr, i64 %compare, i64 %new_value) {
+; CHECK-LABEL: @cmpxchg_2(
+; CHECK-NEXT: %tmp0 = cmpxchg i64* %ptr, i64 %compare, i64 %new_value acq_rel monotonic
+; CHECK-NEXT: ret i64 %compare
+;
+ %tmp0 = cmpxchg i64* %ptr, i64 %compare, i64 %new_value acq_rel monotonic
+ %tmp1 = extractvalue { i64, i1 } %tmp0, 1
+ %tmp2 = extractvalue { i64, i1 } %tmp0, 0
+ %tmp3 = select i1 %tmp1, i64 %compare, i64 %tmp2
+ %tmp4 = select i1 %tmp1, i64 %tmp3, i64 %compare
+ ret i64 %tmp4
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-crash-noverify.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-crash-noverify.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-crash-noverify.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-crash-noverify.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,19 @@
+; RUN: opt < %s -disable-verify -instcombine -S | opt -S | FileCheck %s
+; Formerly crashed, PR8490.
+
+; CHECK-LABEL: @test3(
+define i32 @test3(i1 %bool, i32 %a) {
+entry:
+ %cond = or i1 %bool, true
+ br i1 %cond, label %return, label %xpto
+
+; technically reachable, but this malformed IR may appear as a result of constant propagation
+xpto:
+ %select = select i1 %bool, i32 %a, i32 %select
+ %select2 = select i1 %bool, i32 %select2, i32 %a
+ %sum = add i32 %select, %select2
+ ret i32 %sum
+
+return:
+ ret i32 7
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-crash.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-crash.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-crash.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,32 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+; Formerly crashed, PR8490.
+
+define fastcc double @gimp_operation_color_balance_map(float %value, double %highlights) nounwind readnone inlinehint {
+entry:
+; CHECK: gimp_operation_color_balance_map
+; CHECK: fsub double -0.000000
+ %conv = fpext float %value to double
+ %div = fdiv double %conv, 1.600000e+01
+ %add = fadd double %div, 1.000000e+00
+ %div1 = fdiv double 1.000000e+00, %add
+ %sub = fsub double 1.075000e+00, %div1
+ %sub24 = fsub double 1.000000e+00, %sub
+ %add26 = fadd double %sub, 1.000000e+00
+ %cmp86 = fcmp ogt double %highlights, 0.000000e+00
+ %cond90 = select i1 %cmp86, double %sub24, double %add26
+ %mul91 = fmul double %highlights, %cond90
+ %add94 = fadd double %mul91, %mul91
+ ret double %add94
+}
+
+; PR10180: same crash, but with vectors
+define <4 x float> @foo(i1 %b, <4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; CHECK-LABEL: @foo(
+; CHECK: fsub <4 x float>
+; CHECK: select
+; CHECK: fadd <4 x float>
+ %a = fadd <4 x float> %x, %y
+ %sub = fsub <4 x float> %x, %z
+ %sel = select i1 %b, <4 x float> %a, <4 x float> %sub
+ ret <4 x float> %sel
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-extractelement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-extractelement.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-extractelement.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-extractelement.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,146 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+declare void @v4float_user(<4 x float>) #0
+
+define float @extract_one_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
+; CHECK-LABEL: @extract_one_select(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %c, 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <4 x float> [[SEL]], i32 2
+; CHECK-NEXT: ret float [[EXTRACT]]
+;
+ %cmp = icmp ne i32 %c, 0
+ %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
+ %extract = extractelement <4 x float> %sel, i32 2
+ ret float %extract
+}
+
+; Multiple extractelements
+define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
+; CHECK-LABEL: @extract_two_select(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %c, 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> [[BUILD2]]
+;
+ %cmp = icmp ne i32 %c, 0
+ %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
+ %extract1 = extractelement <4 x float> %sel, i32 1
+ %extract2 = extractelement <4 x float> %sel, i32 2
+ %build1 = insertelement <2 x float> undef, float %extract1, i32 0
+ %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
+ ret <2 x float> %build2
+}
+
+; Select has an extra non-extractelement user, don't change it
+define float @extract_one_select_user(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
+; CHECK-LABEL: @extract_one_select_user(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %c, 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <4 x float> [[SEL]], i32 2
+; CHECK-NEXT: call void @v4float_user(<4 x float> [[SEL]])
+; CHECK-NEXT: ret float [[EXTRACT]]
+;
+ %cmp = icmp ne i32 %c, 0
+ %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
+ %extract = extractelement <4 x float> %sel, i32 2
+ call void @v4float_user(<4 x float> %sel)
+ ret float %extract
+}
+
+define float @extract_one_vselect_user(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @extract_one_vselect_user(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> %c, zeroinitializer
+; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <4 x float> [[SEL]], i32 2
+; CHECK-NEXT: call void @v4float_user(<4 x float> [[SEL]])
+; CHECK-NEXT: ret float [[EXTRACT]]
+;
+ %cmp = icmp ne <4 x i32> %c, zeroinitializer
+ %sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
+ %extract = extractelement <4 x float> %sel, i32 2
+ call void @v4float_user(<4 x float> %sel)
+ ret float %extract
+}
+
+; Do not convert the vector select into a scalar select. That would increase
+; the instruction count and potentially obfuscate a vector min/max idiom.
+
+define float @extract_one_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @extract_one_vselect(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> %c, zeroinitializer
+; CHECK-NEXT: [[SELECT:%.*]] = select <4 x i1> [[CMP]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <4 x float> [[SELECT]], i32 0
+; CHECK-NEXT: ret float [[EXTRACT]]
+;
+ %cmp = icmp ne <4 x i32> %c, zeroinitializer
+ %select = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
+ %extract = extractelement <4 x float> %select, i32 0
+ ret float %extract
+}
+
+; Multiple extractelements from a vector select
+define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @extract_two_vselect(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> %c, zeroinitializer
+; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> [[BUILD2]]
+;
+ %cmp = icmp ne <4 x i32> %c, zeroinitializer
+ %sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
+ %extract1 = extractelement <4 x float> %sel, i32 1
+ %extract2 = extractelement <4 x float> %sel, i32 2
+ %build1 = insertelement <2 x float> undef, float %extract1, i32 0
+ %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
+ ret <2 x float> %build2
+}
+
+; The vector selects are not decomposed into scalar selects because that would increase
+; the instruction count. Extract+insert is converted to non-lane-crossing shuffles.
+; Test multiple extractelements
+define <4 x float> @simple_vector_select(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_vector_select(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> %c, i32 0
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT: [[A_SINK:%.*]] = select i1 [[TOBOOL]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> %c, i32 1
+; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[A_SINK1:%.*]] = select i1 [[TOBOOL1]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[A_SINK]], <4 x float> [[A_SINK1]], <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> %c, i32 2
+; CHECK-NEXT: [[TOBOOL6:%.*]] = icmp eq i32 [[TMP3]], 0
+; CHECK-NEXT: [[A_SINK2:%.*]] = select i1 [[TOBOOL6]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[A_SINK2]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> %c, i32 3
+; CHECK-NEXT: [[TOBOOL11:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT: [[A_SINK3:%.*]] = select i1 [[TOBOOL11]], <4 x float> %b, <4 x float> %a
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[A_SINK3]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x float> [[TMP6]]
+;
+entry:
+ %0 = extractelement <4 x i32> %c, i32 0
+ %tobool = icmp ne i32 %0, 0
+ %a.sink = select i1 %tobool, <4 x float> %a, <4 x float> %b
+ %1 = extractelement <4 x float> %a.sink, i32 0
+ %2 = insertelement <4 x float> undef, float %1, i32 0
+ %3 = extractelement <4 x i32> %c, i32 1
+ %tobool1 = icmp ne i32 %3, 0
+ %a.sink1 = select i1 %tobool1, <4 x float> %a, <4 x float> %b
+ %4 = extractelement <4 x float> %a.sink1, i32 1
+ %5 = insertelement <4 x float> %2, float %4, i32 1
+ %6 = extractelement <4 x i32> %c, i32 2
+ %tobool6 = icmp ne i32 %6, 0
+ %a.sink2 = select i1 %tobool6, <4 x float> %a, <4 x float> %b
+ %7 = extractelement <4 x float> %a.sink2, i32 2
+ %8 = insertelement <4 x float> %5, float %7, i32 2
+ %9 = extractelement <4 x i32> %c, i32 3
+ %tobool11 = icmp ne i32 %9, 0
+ %a.sink3 = select i1 %tobool11, <4 x float> %a, <4 x float> %b
+ %10 = extractelement <4 x float> %a.sink3, i32 3
+ %11 = insertelement <4 x float> %8, float %10, i32 3
+ ret <4 x float> %11
+}
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
Added: llvm/trunk/test/Transforms/InstCombine/select-gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-gep.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-gep.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-gep.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,152 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32* @test1a(i32* %p, i32* %q) {
+; CHECK-LABEL: @test1a(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32* [[P:%.*]], [[Q:%.*]]
+; CHECK-NEXT: [[SELECT_V:%.*]] = select i1 [[CMP]], i32* [[P]], i32* [[Q]]
+; CHECK-NEXT: [[SELECT:%.*]] = getelementptr i32, i32* [[SELECT_V]], i64 4
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr i32, i32* %p, i64 4
+ %gep2 = getelementptr i32, i32* %q, i64 4
+ %cmp = icmp ugt i32* %p, %q
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+define i32* @test1b(i32* %p, i32* %q) {
+; CHECK-LABEL: @test1b(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32* [[P:%.*]], [[Q:%.*]]
+; CHECK-NEXT: [[SELECT_V:%.*]] = select i1 [[CMP]], i32* [[P]], i32* [[Q]]
+; CHECK-NEXT: [[SELECT:%.*]] = getelementptr i32, i32* [[SELECT_V]], i64 4
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr inbounds i32, i32* %p, i64 4
+ %gep2 = getelementptr i32, i32* %q, i64 4
+ %cmp = icmp ugt i32* %p, %q
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+define i32* @test1c(i32* %p, i32* %q) {
+; CHECK-LABEL: @test1c(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32* [[P:%.*]], [[Q:%.*]]
+; CHECK-NEXT: [[SELECT_V:%.*]] = select i1 [[CMP]], i32* [[P]], i32* [[Q]]
+; CHECK-NEXT: [[SELECT:%.*]] = getelementptr i32, i32* [[SELECT_V]], i64 4
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr i32, i32* %p, i64 4
+ %gep2 = getelementptr inbounds i32, i32* %q, i64 4
+ %cmp = icmp ugt i32* %p, %q
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+define i32* @test1d(i32* %p, i32* %q) {
+; CHECK-LABEL: @test1d(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32* [[P:%.*]], [[Q:%.*]]
+; CHECK-NEXT: [[SELECT_V:%.*]] = select i1 [[CMP]], i32* [[P]], i32* [[Q]]
+; CHECK-NEXT: [[SELECT:%.*]] = getelementptr inbounds i32, i32* [[SELECT_V]], i64 4
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr inbounds i32, i32* %p, i64 4
+ %gep2 = getelementptr inbounds i32, i32* %q, i64 4
+ %cmp = icmp ugt i32* %p, %q
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+define i32* @test2(i32* %p, i64 %x, i64 %y) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT_V:%.*]] = select i1 [[CMP]], i64 [[X]], i64 [[Y]]
+; CHECK-NEXT: [[SELECT:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 [[SELECT_V]]
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr inbounds i32, i32* %p, i64 %x
+ %gep2 = getelementptr inbounds i32, i32* %p, i64 %y
+ %cmp = icmp ugt i64 %x, %y
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+; Three (or more) operand GEPs are currently expected to not be optimised,
+; though they could be in principle.
+
+define i32* @test3a([4 x i32]* %p, i64 %x, i64 %y) {
+; CHECK-LABEL: @test3a(
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[P:%.*]], i64 2, i64 [[X:%.*]]
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[P]], i64 2, i64 [[Y:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[X]], [[Y]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32* [[GEP1]], i32* [[GEP2]]
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr inbounds [4 x i32], [4 x i32]* %p, i64 2, i64 %x
+ %gep2 = getelementptr inbounds [4 x i32], [4 x i32]* %p, i64 2, i64 %y
+ %cmp = icmp ugt i64 %x, %y
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+define i32* @test3b([4 x i32]* %p, i32* %q, i64 %x, i64 %y) {
+; CHECK-LABEL: @test3b(
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[P:%.*]], i64 [[X:%.*]], i64 2
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, i32* [[Q:%.*]], i64 [[X]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32* [[GEP1]], i32* [[GEP2]]
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr inbounds [4 x i32], [4 x i32]* %p, i64 %x, i64 2
+ %gep2 = getelementptr inbounds i32, i32* %q, i64 %x
+ %cmp = icmp ugt i64 %x, %y
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+define i32* @test3c(i32* %p, [4 x i32]* %q, i64 %x, i64 %y) {
+; CHECK-LABEL: @test3c(
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 [[X:%.*]]
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[Q:%.*]], i64 [[X]], i64 2
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[X]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32* [[GEP1]], i32* [[GEP2]]
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr inbounds i32, i32* %p, i64 %x
+ %gep2 = getelementptr inbounds [4 x i32], [4 x i32]* %q, i64 %x, i64 2
+ %cmp = icmp ugt i64 %x, %y
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+; Shouldn't be optimised as it would mean introducing an extra select
+
+define i32* @test4(i32* %p, i32* %q, i64 %x, i64 %y) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 [[X:%.*]]
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, i32* [[Q:%.*]], i64 [[Y:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[X]], [[Y]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32* [[GEP1]], i32* [[GEP2]]
+; CHECK-NEXT: ret i32* [[SELECT]]
+;
+ %gep1 = getelementptr inbounds i32, i32* %p, i64 %x
+ %gep2 = getelementptr inbounds i32, i32* %q, i64 %y
+ %cmp = icmp ugt i64 %x, %y
+ %select = select i1 %cmp, i32* %gep1, i32* %gep2
+ ret i32* %select
+}
+
+; We cannot create a select with a vector condition but scalar operands.
+
+define <2 x i64*> @test5(i64* %p1, i64* %p2, <2 x i64> %idx, <2 x i1> %cc) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i64, i64* %p1, <2 x i64> %idx
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i64, i64* %p2, <2 x i64> %idx
+; CHECK-NEXT: [[SELECT:%.*]] = select <2 x i1> %cc, <2 x i64*> [[GEP1]], <2 x i64*> [[GEP2]]
+; CHECK-NEXT: ret <2 x i64*> [[SELECT]]
+;
+ %gep1 = getelementptr i64, i64* %p1, <2 x i64> %idx
+ %gep2 = getelementptr i64, i64* %p2, <2 x i64> %idx
+ %select = select <2 x i1> %cc, <2 x i64*> %gep1, <2 x i64*> %gep2
+ ret <2 x i64*> %select
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-icmp-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-icmp-and.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-icmp-and.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-icmp-and.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,620 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+;; ((X & 27) ? 27 : 0)
+
+define i41 @test5(i41 %X) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[Y:%.*]] = and i41 [[X:%.*]], 32
+; CHECK-NEXT: ret i41 [[Y]]
+;
+ %Y = and i41 %X, 32
+ %t = icmp ne i41 %Y, 0
+ %V = select i1 %t, i41 32, i41 0
+ ret i41 %V
+}
+
+;; ((X & 27) ? 27 : 0)
+
+define i1023 @test6(i1023 %X) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[Y:%.*]] = and i1023 [[X:%.*]], 64
+; CHECK-NEXT: ret i1023 [[Y]]
+;
+ %Y = and i1023 %X, 64
+ %t = icmp ne i1023 %Y, 0
+ %V = select i1 %t, i1023 64, i1023 0
+ ret i1023 %V
+}
+
+define i32 @test35(i32 %x) {
+; CHECK-LABEL: @test35(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 60, i32 100
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp sge i32 %x, 0
+ %cond = select i1 %cmp, i32 60, i32 100
+ ret i32 %cond
+}
+
+define <2 x i32> @test35vec(<2 x i32> %x) {
+; CHECK-LABEL: @test35vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
+; CHECK-NEXT: ret <2 x i32> [[COND]]
+;
+ %cmp = icmp sge <2 x i32> %x, <i32 0, i32 0>
+ %cond = select <2 x i1> %cmp, <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
+ ret <2 x i32> %cond
+}
+
+; Make sure we can still perform this optimization with a truncate present
+define i32 @test35_with_trunc(i64 %x) {
+; CHECK-LABEL: @test35_with_trunc(
+; CHECK-NEXT: [[X1:%.*]] = trunc i64 [[X:%.*]] to i32
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X1]], -1
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 60, i32 100
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %x1 = trunc i64 %x to i32
+ %cmp = icmp sge i32 %x1, 0
+ %cond = select i1 %cmp, i32 60, i32 100
+ ret i32 %cond
+}
+
+define i32 @test36(i32 %x) {
+; CHECK-LABEL: @test36(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 60, i32 100
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp slt i32 %x, 0
+ %cond = select i1 %cmp, i32 60, i32 100
+ ret i32 %cond
+}
+
+define <2 x i32> @test36vec(<2 x i32> %x) {
+; CHECK-LABEL: @test36vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
+; CHECK-NEXT: ret <2 x i32> [[COND]]
+;
+ %cmp = icmp slt <2 x i32> %x, <i32 0, i32 0>
+ %cond = select <2 x i1> %cmp, <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
+ ret <2 x i32> %cond
+}
+
+define i32 @test37(i32 %x) {
+; CHECK-LABEL: @test37(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 1, i32 -1
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp sgt i32 %x, -1
+ %cond = select i1 %cmp, i32 1, i32 -1
+ ret i32 %cond
+}
+
+define <2 x i32> @test37vec(<2 x i32> %x) {
+; CHECK-LABEL: @test37vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 -1, i32 -1>
+; CHECK-NEXT: ret <2 x i32> [[COND]]
+;
+ %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
+ %cond = select <2 x i1> %cmp, <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 -1, i32 -1>
+ ret <2 x i32> %cond
+}
+
+define i32 @test65(i64 %x) {
+; CHECK-LABEL: @test65(
+; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 16
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i64 %x, 16
+ %2 = icmp ne i64 %1, 0
+ %3 = select i1 %2, i32 40, i32 42
+ ret i32 %3
+}
+
+define <2 x i32> @test65vec(<2 x i64> %x) {
+; CHECK-LABEL: @test65vec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 16, i64 16>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = and <2 x i64> %x, <i64 16, i64 16>
+ %2 = icmp ne <2 x i64> %1, zeroinitializer
+ %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %3
+}
+
+define i32 @test66(i64 %x) {
+; CHECK-LABEL: @test66(
+; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 4294967296
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i64 %x, 4294967296
+ %2 = icmp ne i64 %1, 0
+ %3 = select i1 %2, i32 40, i32 42
+ ret i32 %3
+}
+
+define <2 x i32> @test66vec(<2 x i64> %x) {
+; CHECK-LABEL: @test66vec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 4294967296, i64 4294967296>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = and <2 x i64> %x, <i64 4294967296, i64 4294967296>
+ %2 = icmp ne <2 x i64> %1, zeroinitializer
+ %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %3
+}
+
+; Make sure we don't try to optimize a scalar 'and' with a vector select.
+define <2 x i32> @test66vec_scalar_and(i64 %x) {
+; CHECK-LABEL: @test66vec_scalar_and(
+; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 4294967296
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = and i64 %x, 4294967296
+ %2 = icmp ne i64 %1, 0
+ %3 = select i1 %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %3
+}
+
+define i32 @test67(i16 %x) {
+; CHECK-LABEL: @test67(
+; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[X:%.*]], 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i16 %x, 4
+ %2 = icmp ne i16 %1, 0
+ %3 = select i1 %2, i32 40, i32 42
+ ret i32 %3
+}
+
+define <2 x i32> @test67vec(<2 x i16> %x) {
+; CHECK-LABEL: @test67vec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i16> [[X:%.*]], <i16 4, i16 4>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i16> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = and <2 x i16> %x, <i16 4, i16 4>
+ %2 = icmp ne <2 x i16> %1, zeroinitializer
+ %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %3
+}
+
+define i32 @test71(i32 %x) {
+; CHECK-LABEL: @test71(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 128
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 128
+ %2 = icmp ne i32 %1, 0
+ %3 = select i1 %2, i32 40, i32 42
+ ret i32 %3
+}
+
+define <2 x i32> @test71vec(<2 x i32> %x) {
+; CHECK-LABEL: @test71vec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 128, i32 128>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = and <2 x i32> %x, <i32 128, i32 128>
+ %2 = icmp ne <2 x i32> %1, <i32 0, i32 0>
+ %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %3
+}
+
+define i32 @test72(i32 %x) {
+; CHECK-LABEL: @test72(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 128
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 40, i32 42
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 128
+ %2 = icmp eq i32 %1, 0
+ %3 = select i1 %2, i32 40, i32 42
+ ret i32 %3
+}
+
+define <2 x i32> @test72vec(<2 x i32> %x) {
+; CHECK-LABEL: @test72vec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 128, i32 128>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = and <2 x i32> %x, <i32 128, i32 128>
+ %2 = icmp eq <2 x i32> %1, <i32 0, i32 0>
+ %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %3
+}
+
+define i32 @test73(i32 %x) {
+; CHECK-LABEL: @test73(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i8 [[TMP1]], -1
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 40, i32 42
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = trunc i32 %x to i8
+ %2 = icmp sgt i8 %1, -1
+ %3 = select i1 %2, i32 40, i32 42
+ ret i32 %3
+}
+
+define <2 x i32> @test73vec(<2 x i32> %x) {
+; CHECK-LABEL: @test73vec(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i8>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <2 x i8> [[TMP1]], <i8 -1, i8 -1>
+; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = trunc <2 x i32> %x to <2 x i8>
+ %2 = icmp sgt <2 x i8> %1, <i8 -1, i8 -1>
+ %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %3
+}
+
+define i32 @test74(i32 %x) {
+; CHECK-LABEL: @test74(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 40, i32 42
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %1 = icmp sgt i32 %x, -1
+ %2 = select i1 %1, i32 40, i32 42
+ ret i32 %2
+}
+
+define <2 x i32> @test74vec(<2 x i32> %x) {
+; CHECK-LABEL: @test74vec(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+;
+ %1 = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
+ %2 = select <2 x i1> %1, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+ ret <2 x i32> %2
+}
+
+;; Code sequence for (X & 16) ? 16 : 0
+define i32 @test15a(i32 %X) {
+; CHECK-LABEL: @test15a(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 16
+; CHECK-NEXT: ret i32 [[T1]]
+;
+ %t1 = and i32 %X, 16
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = select i1 %t2, i32 0, i32 16
+ ret i32 %t3
+}
+
+;; Code sequence for (X & 32) ? 0 : 24
+define i32 @test15b(i32 %X) {
+; CHECK-LABEL: @test15b(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 32
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], 32
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %X, 32
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = select i1 %t2, i32 32, i32 0
+ ret i32 %t3
+}
+
+;; Alternate code sequence for (X & 16) ? 16 : 0
+define i32 @test15c(i32 %X) {
+; CHECK-LABEL: @test15c(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 16
+; CHECK-NEXT: ret i32 [[T1]]
+;
+ %t1 = and i32 %X, 16
+ %t2 = icmp eq i32 %t1, 16
+ %t3 = select i1 %t2, i32 16, i32 0
+ ret i32 %t3
+}
+
+;; Alternate code sequence for (X & 16) ? 16 : 0
+define i32 @test15d(i32 %X) {
+; CHECK-LABEL: @test15d(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 16
+; CHECK-NEXT: ret i32 [[T1]]
+;
+ %t1 = and i32 %X, 16
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 16, i32 0
+ ret i32 %t3
+}
+
+;; (a & 128) ? 256 : 0
+define i32 @test15e(i32 %X) {
+; CHECK-LABEL: @test15e(
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T1]], 256
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %X, 128
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 256, i32 0
+ ret i32 %t3
+}
+
+;; (a & 128) ? 0 : 256
+define i32 @test15f(i32 %X) {
+; CHECK-LABEL: @test15f(
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T1]], 256
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 256
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %t1 = and i32 %X, 128
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 0, i32 256
+ ret i32 %t3
+}
+
+;; (a & 8) ? -1 : -9
+define i32 @test15g(i32 %X) {
+; CHECK-LABEL: @test15g(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -9
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %X, 8
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 -1, i32 -9
+ ret i32 %t3
+}
+
+;; (a & 8) ? -9 : -1
+define i32 @test15h(i32 %X) {
+; CHECK-LABEL: @test15h(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], -1
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %X, 8
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 -9, i32 -1
+ ret i32 %t3
+}
+
+;; (a & 2) ? 577 : 1089
+define i32 @test15i(i32 %X) {
+; CHECK-LABEL: @test15i(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 2
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T2]], i32 1089, i32 577
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t1 = and i32 %X, 2
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 577, i32 1089
+ ret i32 %t3
+}
+
+;; (a & 2) ? 1089 : 577
+define i32 @test15j(i32 %X) {
+; CHECK-LABEL: @test15j(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 2
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T2]], i32 577, i32 1089
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t1 = and i32 %X, 2
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 1089, i32 577
+ ret i32 %t3
+}
+
+declare void @use1(i1)
+
+; (X & 8) == 0 ? -3 : -11 --> (X & 8) ^ -3
+; Extra cmp use ensures that cmp predicate canonicalization is thwarted.
+
+define i32 @clear_to_set(i32 %x) {
+; CHECK-LABEL: @clear_to_set(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], -3
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %x, 8
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = select i1 %t2, i32 -3, i32 -11
+ call void @use1(i1 %t2)
+ ret i32 %t3
+}
+
+; (X & 8) == 0 ? -11 : -3 --> (X & 8) | -11
+; Extra cmp use ensures that cmp predicate canonicalization is thwarted.
+
+define i32 @clear_to_clear(i32 %x) {
+; CHECK-LABEL: @clear_to_clear(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T1]], -11
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %x, 8
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = select i1 %t2, i32 -11, i32 -3
+ call void @use1(i1 %t2)
+ ret i32 %t3
+}
+
+; (X & 8) != 0 ? -3 : -11 --> (X & 8) | -11
+; Extra cmp use ensures that cmp predicate canonicalization is thwarted.
+
+define i32 @set_to_set(i32 %x) {
+; CHECK-LABEL: @set_to_set(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T1]], -11
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %x, 8
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 -3, i32 -11
+ call void @use1(i1 %t2)
+ ret i32 %t3
+}
+
+; (X & 8) != 0 ? -3 : -11 --> (X & 8) ^ -3
+; Extra cmp use ensures that cmp predicate canonicalization is thwarted.
+
+define i32 @set_to_clear(i32 %x) {
+; CHECK-LABEL: @set_to_clear(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], -3
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %t1 = and i32 %x, 8
+ %t2 = icmp ne i32 %t1, 0
+ %t3 = select i1 %t2, i32 -11, i32 -3
+ call void @use1(i1 %t2)
+ ret i32 %t3
+}
+
+; (X & 128) == 0 ? 131 : 3 --> (X & 128) ^ 131
+
+define i8 @clear_to_set_decomposebittest(i8 %x) {
+; CHECK-LABEL: @clear_to_set_decomposebittest(
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
+; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[TMP1]], -125
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+ %t2 = icmp sgt i8 %x, -1
+ %t3 = select i1 %t2, i8 131, i8 3
+ ret i8 %t3
+}
+
+; (X & 128) == 0 ? 3 : 131 --> (X & 128) | 3
+
+define i8 @clear_to_clear_decomposebittest(i8 %x) {
+; CHECK-LABEL: @clear_to_clear_decomposebittest(
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
+; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 3
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+ %t2 = icmp sgt i8 %x, -1
+ %t3 = select i1 %t2, i8 3, i8 131
+ ret i8 %t3
+}
+
+; (X & 128) != 0 ? 131 : 3 --> (X & 128) | 3
+
+define i8 @set_to_set_decomposebittest(i8 %x) {
+; CHECK-LABEL: @set_to_set_decomposebittest(
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
+; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 3
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+ %t2 = icmp slt i8 %x, 0
+ %t3 = select i1 %t2, i8 131, i8 3
+ ret i8 %t3
+}
+
+; (X & 128) != 0 ? 3 : 131 --> (X & 128) ^ 131
+
+define i8 @set_to_clear_decomposebittest(i8 %x) {
+; CHECK-LABEL: @set_to_clear_decomposebittest(
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
+; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[TMP1]], -125
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+ %t2 = icmp slt i8 %x, 0
+ %t3 = select i1 %t2, i8 3, i8 131
+ ret i8 %t3
+}
+
+; (X & 128) == 0 ? 131 : 3 --> (X & 128) ^ 131
+; Extra cmp use to verify that we are not creating extra instructions.
+
+define i8 @clear_to_set_decomposebittest_extra_use(i8 %x) {
+; CHECK-LABEL: @clear_to_set_decomposebittest_extra_use(
+; CHECK-NEXT: [[T2:%.*]] = icmp sgt i8 [[X:%.*]], -1
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T2]], i8 -125, i8 3
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i8 [[T3]]
+;
+ %t2 = icmp sgt i8 %x, -1
+ %t3 = select i1 %t2, i8 131, i8 3
+ call void @use1(i1 %t2)
+ ret i8 %t3
+}
+
+; (X & 128) == 0 ? 3 : 131 --> (X & 128) | 3
+; Extra cmp use to verify that we are not creating extra instructions.
+
+define i8 @clear_to_clear_decomposebittest_extra_use(i8 %x) {
+; CHECK-LABEL: @clear_to_clear_decomposebittest_extra_use(
+; CHECK-NEXT: [[T2:%.*]] = icmp sgt i8 [[X:%.*]], -1
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T2]], i8 3, i8 -125
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i8 [[T3]]
+;
+ %t2 = icmp sgt i8 %x, -1
+ %t3 = select i1 %t2, i8 3, i8 131
+ call void @use1(i1 %t2)
+ ret i8 %t3
+}
+
+; (X & 128) != 0 ? 131 : 3 --> (X & 128) | 3
+; Extra cmp use to verify that we are not creating extra instructions.
+
+define i8 @set_to_set_decomposebittest_extra_use(i8 %x) {
+; CHECK-LABEL: @set_to_set_decomposebittest_extra_use(
+; CHECK-NEXT: [[T2:%.*]] = icmp slt i8 [[X:%.*]], 0
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T2]], i8 -125, i8 3
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i8 [[T3]]
+;
+ %t2 = icmp slt i8 %x, 0
+ %t3 = select i1 %t2, i8 131, i8 3
+ call void @use1(i1 %t2)
+ ret i8 %t3
+}
+
+; (X & 128) != 0 ? 3 : 131 --> (X & 128) ^ 131
+; Extra cmp use to verify that we are not creating extra instructions.
+
+define i8 @set_to_clear_decomposebittest_extra_use(i8 %x) {
+; CHECK-LABEL: @set_to_clear_decomposebittest_extra_use(
+; CHECK-NEXT: [[T2:%.*]] = icmp slt i8 [[X:%.*]], 0
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T2]], i8 3, i8 -125
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: ret i8 [[T3]]
+;
+ %t2 = icmp slt i8 %x, 0
+ %t3 = select i1 %t2, i8 3, i8 131
+ call void @use1(i1 %t2)
+ ret i8 %t3
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/select-load-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-load-call.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-load-call.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-load-call.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,15 @@
+; RUN: opt < %s -instcombine -S | grep "ret i32 1"
+
+declare void @test2()
+
+define i32 @test(i1 %cond, i32 *%P) {
+ %A = alloca i32
+ store i32 1, i32* %P
+ store i32 1, i32* %A
+
+ call void @test2() readonly
+
+ %P2 = select i1 %cond, i32 *%P, i32* %A
+ %V = load i32, i32* %P2
+ ret i32 %V
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-obo-peo-ops.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1143 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define i64 @test_shl_nuw_nsw__all_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl nuw nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl_nuw__all_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nuw__all_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl nuw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl_nsw__all_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nsw__all_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl__all_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl__all_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 1073741822
+ %2 = shl nuw nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 1073741822
+ %2 = shl nuw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 1073741822
+ %2 = shl nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl__nuw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 1073741822
+ %2 = shl i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_shl_nuw_nsw__nsw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %1 = or i32 %x, -83886080
+ %2 = icmp eq i32 %1, -83886079
+ %3 = shl nuw nsw i32 %1, 2
+ %4 = select i1 %2, i32 -335544316, i32 %3
+ %5 = mul i32 %4, %1
+ %6 = mul i32 %5, %3
+ ret i32 %6
+}
+
+define i32 @test_shl_nuw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_shl_nuw__nsw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %1 = or i32 %x, -83886080
+ %2 = icmp eq i32 %1, -83886079
+ %3 = shl nuw i32 %1, 2
+ %4 = select i1 %2, i32 -335544316, i32 %3
+ %5 = mul i32 %4, %1
+ %6 = mul i32 %5, %3
+ ret i32 %6
+}
+
+define i32 @test_shl_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_shl_nsw__nsw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
+; CHECK-NEXT: [[TMP3:%.*]] = shl nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %1 = or i32 %x, -83886080
+ %2 = icmp eq i32 %1, -83886079
+ %3 = shl nsw i32 %1, 2
+ %4 = select i1 %2, i32 -335544316, i32 %3
+ %5 = mul i32 %4, %1
+ %6 = mul i32 %5, %3
+ ret i32 %6
+}
+
+define i32 @test_shl__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_shl__nsw_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
+; CHECK-NEXT: [[TMP3:%.*]] = shl nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %1 = or i32 %x, -83886080
+ %2 = icmp eq i32 %1, -83886079
+ %3 = shl i32 %1, 2
+ %4 = select i1 %2, i32 -335544316, i32 %3
+ %5 = mul i32 %4, %1
+ %6 = mul i32 %5, %3
+ ret i32 %6
+}
+
+
+define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 4294967294
+ %2 = shl nuw nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nuw__none_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 4294967294
+ %2 = shl nuw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl_nsw__none_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
+; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 4294967294
+ %2 = shl nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_shl__none_are_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_shl__none_are_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, 4294967294
+ %2 = shl i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_lshr_exact__exact_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_lshr_exact__exact_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
+; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 60
+ %2 = lshr exact i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_lshr__exact_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_lshr__exact_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
+; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 60
+ %2 = lshr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 63
+; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, 63
+ %2 = lshr exact i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_lshr__exact_is_unsafe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_lshr__exact_is_unsafe(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, 63
+ %2 = lshr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_ashr_exact__exact_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
+; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, -2147483588
+ %2 = ashr exact i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_ashr__exact_is_safe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
+; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, -2147483588
+ %2 = ashr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
+; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %1 = and i32 %x, -2147483585
+ %2 = ashr exact i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) {
+; CHECK-LABEL: @test_ashr__exact_is_unsafe(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, -2147483585
+ %2 = ashr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i32 @test_add_nuw_nsw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw_nsw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 3
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 1073741823
+ %cmp = icmp eq i32 %and, 3
+ %add = add nuw nsw i32 %and, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nuw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 3
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 1073741823
+ %cmp = icmp eq i32 %and, 3
+ %add = add nuw i32 %and, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nsw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nsw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 3
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 1073741823
+ %cmp = icmp eq i32 %and, 3
+ %add = add nsw i32 %and, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 3
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 1073741823
+ %cmp = icmp eq i32 %and, 3
+ %add = add i32 %and, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nuw_nsw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw_nsw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 2147483647
+ %add = add nuw nsw i32 %and, 1
+ %sel = select i1 %cmp, i32 -2147483648, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nuw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 2147483647
+ %add = add nuw i32 %and, 1
+ %sel = select i1 %cmp, i32 -2147483648, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nsw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nsw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 2147483647
+ %add = add nsw i32 %and, 1
+ %sel = select i1 %cmp, i32 -2147483648, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 2147483647
+ %add = add i32 %and, 1
+ %sel = select i1 %cmp, i32 -2147483648, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nuw_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw_nsw__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -1
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[OR]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -1
+ %add = add nuw nsw i32 %or, 1
+ %sel = select i1 %cmp, i32 0, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nuw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -1
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[OR]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -1
+ %add = add nuw i32 %or, 1
+ %sel = select i1 %cmp, i32 0, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nsw__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -1
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -1
+ %add = add nsw i32 %or, 1
+ %sel = select i1 %cmp, i32 0, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_add__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -1
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -1
+ %add = add i32 %or, 1
+ %sel = select i1 %cmp, i32 0, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nuw_nsw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw_nsw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[X]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 3
+ %add = add nuw nsw i32 %x, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nuw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nuw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[X]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 3
+ %add = add nuw i32 %x, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add_nsw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add_nsw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 3
+ %add = add nsw i32 %x, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_add__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_add__none_are_safe(
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT: ret i32 [[ADD]]
+;
+ %cmp = icmp eq i32 %x, 3
+ %add = add i32 %x, 1
+ %sel = select i1 %cmp, i32 4, i32 %add
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw_nsw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw_nsw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 6
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 6
+ %sub = sub nuw nsw i32 -254, %and
+ %sel = select i1 %cmp, i32 -260, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 6
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 6
+ %sub = sub nuw i32 -254, %and
+ %sel = select i1 %cmp, i32 -260, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nsw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nsw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 6
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 6
+ %sub = sub nsw i32 -254, %and
+ %sel = select i1 %cmp, i32 -260, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 6
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 6
+ %sub = sub i32 -254, %and
+ %sel = select i1 %cmp, i32 -260, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw_nsw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw_nsw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 1073741824
+ %sub = sub nuw nsw i32 -2147483648, %and
+ %sel = select i1 %cmp, i32 1073741824, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 1073741824
+ %sub = sub nuw i32 -2147483648, %and
+ %sel = select i1 %cmp, i32 1073741824, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nsw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nsw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 1073741824
+ %sub = sub nsw i32 -2147483648, %and
+ %sel = select i1 %cmp, i32 1073741824, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2147483647
+ %cmp = icmp eq i32 %and, 1073741824
+ %sub = sub i32 -2147483648, %and
+ %sel = select i1 %cmp, i32 1073741824, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw_nsw__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[OR]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -2147483647
+ %sub = sub nuw nsw i32 -2147483648, %or
+ %sel = select i1 %cmp, i32 -1, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[OR]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -2147483647
+ %sub = sub nuw i32 -2147483648, %or
+ %sel = select i1 %cmp, i32 -1, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nsw__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -2147483647
+ %sub = sub nsw i32 -2147483648, %or
+ %sel = select i1 %cmp, i32 -1, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_sub__nsw_is_safe(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %or = or i32 %x, -2147483648
+ %cmp = icmp eq i32 %or, -2147483647
+ %sub = sub i32 -2147483648, %or
+ %sel = select i1 %cmp, i32 -1, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw_nsw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw_nsw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[X]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 2147483647, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 1
+ %sub = sub nuw nsw i32 -2147483648, %x
+ %sel = select i1 %cmp, i32 2147483647, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nuw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nuw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[X]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 2147483647, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 1
+ %sub = sub nuw i32 -2147483648, %x
+ %sel = select i1 %cmp, i32 2147483647, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub_nsw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub_nsw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 1
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[X]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 2147483647, i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 1
+ %sub = sub nsw i32 -2147483648, %x
+ %sel = select i1 %cmp, i32 2147483647, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_sub__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_sub__none_are_safe(
+; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]
+; CHECK-NEXT: ret i32 [[SUB]]
+;
+ %cmp = icmp eq i32 %x, 1
+ %sub = sub i32 -2147483648, %x
+ %sel = select i1 %cmp, i32 2147483647, i32 %sub
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw_nsw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw_nsw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 17
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 17
+ %mul = mul nuw nsw i32 %and, 9
+ %sel = select i1 %cmp, i32 153, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 17
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 17
+ %mul = mul nuw i32 %and, 9
+ %sel = select i1 %cmp, i32 153, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nsw__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nsw__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 17
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 17
+ %mul = mul nsw i32 %and, 9
+ %sel = select i1 %cmp, i32 153, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul__all_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul__all_are_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 17
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 255
+ %cmp = icmp eq i32 %and, 17
+ %mul = mul i32 %and, 9
+ %sel = select i1 %cmp, i32 153, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw_nsw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw_nsw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 268435457
+ %cmp = icmp eq i32 %and, 268435456
+ %mul = mul nuw nsw i32 %and, 9
+ %sel = select i1 %cmp, i32 -1879048192, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 268435457
+ %cmp = icmp eq i32 %and, 268435456
+ %mul = mul nuw i32 %and, 9
+ %sel = select i1 %cmp, i32 -1879048192, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nsw__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nsw__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 268435457
+ %cmp = icmp eq i32 %and, 268435456
+ %mul = mul nsw i32 %and, 9
+ %sel = select i1 %cmp, i32 -1879048192, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul__nuw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul__nuw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 268435457
+ %cmp = icmp eq i32 %and, 268435456
+ %mul = mul i32 %and, 9
+ %sel = select i1 %cmp, i32 -1879048192, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw_nsw__nsw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = or i32 %x, -83886080
+ %cmp = icmp eq i32 %and, -83886079
+ %mul = mul nuw nsw i32 %and, 9
+ %sel = select i1 %cmp, i32 -754974711, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw__nsw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = or i32 %x, -83886080
+ %cmp = icmp eq i32 %and, -83886079
+ %mul = mul nuw i32 %and, 9
+ %sel = select i1 %cmp, i32 -754974711, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nsw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nsw__nsw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
+; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = or i32 %x, -83886080
+ %cmp = icmp eq i32 %and, -83886079
+ %mul = mul nsw i32 %and, 9
+ %sel = select i1 %cmp, i32 -754974711, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: @test_mul__nsw_is_safe(
+; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
+; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = or i32 %x, -83886080
+ %cmp = icmp eq i32 %and, -83886079
+ %mul = mul i32 %and, 9
+ %sel = select i1 %cmp, i32 -754974711, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw_nsw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw_nsw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 805306368
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[X]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1342177280, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 805306368
+ %mul = mul nuw nsw i32 %x, 9
+ %sel = select i1 %cmp, i32 -1342177280, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nuw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nuw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 805306368
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1342177280, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 805306368
+ %mul = mul nuw i32 %x, 9
+ %sel = select i1 %cmp, i32 -1342177280, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul_nsw__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul_nsw__none_are_safe(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 805306368
+; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X]], 9
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -1342177280, i32 [[MUL]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 805306368
+ %mul = mul nsw i32 %x, 9
+ %sel = select i1 %cmp, i32 -1342177280, i32 %mul
+ ret i32 %sel
+}
+
+define i32 @test_mul__none_are_safe(i32 %x) {
+; CHECK-LABEL: @test_mul__none_are_safe(
+; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9
+; CHECK-NEXT: ret i32 [[MUL]]
+;
+ %cmp = icmp eq i32 %x, 805306368
+ %mul = mul i32 %x, 9
+ %sel = select i1 %cmp, i32 -1342177280, i32 %mul
+ ret i32 %sel
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-of-bittest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-of-bittest.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-of-bittest.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-of-bittest.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,654 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; https://bugs.llvm.org/show_bug.cgi?id=36950
+
+; These all should be just and+icmp, there should be no select.
+
+define i32 @and_lshr_and(i32 %arg) {
+; CHECK-LABEL: @and_lshr_and(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 3
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, 1
+ %tmp1 = icmp eq i32 %tmp, 0
+ %tmp2 = lshr i32 %arg, 1
+ %tmp3 = and i32 %tmp2, 1
+ %tmp4 = select i1 %tmp1, i32 %tmp3, i32 1
+ ret i32 %tmp4
+}
+
+define <2 x i32> @and_lshr_and_splatvec(<2 x i32> %arg) {
+; CHECK-LABEL: @and_lshr_and_splatvec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 3, i32 3>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP4]]
+;
+ %tmp = and <2 x i32> %arg, <i32 1, i32 1>
+ %tmp1 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp2 = lshr <2 x i32> %arg, <i32 1, i32 1>
+ %tmp3 = and <2 x i32> %tmp2, <i32 1, i32 1>
+ %tmp4 = select <2 x i1> %tmp1, <2 x i32> %tmp3, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp4
+}
+
+define <2 x i32> @and_lshr_and_vec_v0(<2 x i32> %arg) {
+; CHECK-LABEL: @and_lshr_and_vec_v0(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 3, i32 6>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP4]]
+;
+ %tmp = and <2 x i32> %arg, <i32 1, i32 4> ; mask is not splat
+ %tmp1 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp2 = lshr <2 x i32> %arg, <i32 1, i32 1>
+ %tmp3 = and <2 x i32> %tmp2, <i32 1, i32 1>
+ %tmp4 = select <2 x i1> %tmp1, <2 x i32> %tmp3, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp4
+}
+
+define <2 x i32> @and_lshr_and_vec_v1(<2 x i32> %arg) {
+; CHECK-LABEL: @and_lshr_and_vec_v1(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 3, i32 5>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP4]]
+;
+ %tmp = and <2 x i32> %arg, <i32 1, i32 1>
+ %tmp1 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp2 = lshr <2 x i32> %arg, <i32 1, i32 2> ; shift is not splat
+ %tmp3 = and <2 x i32> %tmp2, <i32 1, i32 1>
+ %tmp4 = select <2 x i1> %tmp1, <2 x i32> %tmp3, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp4
+}
+
+define <2 x i32> @and_lshr_and_vec_v2(<2 x i32> %arg) {
+; CHECK-LABEL: @and_lshr_and_vec_v2(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 12, i32 3>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP4]]
+;
+ %tmp = and <2 x i32> %arg, <i32 8, i32 1> ; mask is not splat
+ %tmp1 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp2 = lshr <2 x i32> %arg, <i32 2, i32 1> ; shift is not splat
+ %tmp3 = and <2 x i32> %tmp2, <i32 1, i32 1>
+ %tmp4 = select <2 x i1> %tmp1, <2 x i32> %tmp3, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp4
+}
+
+define <3 x i32> @and_lshr_and_vec_undef(<3 x i32> %arg) {
+; CHECK-LABEL: @and_lshr_and_vec_undef(
+; CHECK-NEXT: [[TMP1:%.*]] = and <3 x i32> [[ARG:%.*]], <i32 3, i32 undef, i32 3>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <3 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = zext <3 x i1> [[TMP2]] to <3 x i32>
+; CHECK-NEXT: ret <3 x i32> [[TMP4]]
+;
+ %tmp = and <3 x i32> %arg, <i32 1, i32 undef, i32 1>
+ %tmp1 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
+ %tmp2 = lshr <3 x i32> %arg, <i32 1, i32 undef, i32 1>
+ %tmp3 = and <3 x i32> %tmp2, <i32 1, i32 undef, i32 1>
+ %tmp4 = select <3 x i1> %tmp1, <3 x i32> %tmp3, <3 x i32> <i32 1, i32 undef, i32 1>
+ ret <3 x i32> %tmp4
+}
+
+define i32 @and_and(i32 %arg) {
+; CHECK-LABEL: @and_and(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 3
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %tmp = and i32 %arg, 2
+ %tmp1 = icmp eq i32 %tmp, 0
+ %tmp2 = and i32 %arg, 1
+ %tmp3 = select i1 %tmp1, i32 %tmp2, i32 1
+ ret i32 %tmp3
+}
+
+define <2 x i32> @and_and_splatvec(<2 x i32> %arg) {
+; CHECK-LABEL: @and_and_splatvec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 3, i32 3>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %tmp = and <2 x i32> %arg, <i32 2, i32 2>
+ %tmp1 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp2 = and <2 x i32> %arg, <i32 1, i32 1>
+ %tmp3 = select <2 x i1> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp3
+}
+
+define <2 x i32> @and_and_vec(<2 x i32> %arg) {
+; CHECK-LABEL: @and_and_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 7, i32 3>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %tmp = and <2 x i32> %arg, <i32 6, i32 2> ; mask is not splat
+ %tmp1 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp2 = and <2 x i32> %arg, <i32 1, i32 1>
+ %tmp3 = select <2 x i1> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp3
+}
+
+define <3 x i32> @and_and_vec_undef(<3 x i32> %arg) {
+; CHECK-LABEL: @and_and_vec_undef(
+; CHECK-NEXT: [[TMP1:%.*]] = and <3 x i32> [[ARG:%.*]], <i32 3, i32 -1, i32 3>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <3 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = zext <3 x i1> [[TMP2]] to <3 x i32>
+; CHECK-NEXT: ret <3 x i32> [[TMP3]]
+;
+ %tmp = and <3 x i32> %arg, <i32 2, i32 undef, i32 2>
+ %tmp1 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
+ %tmp2 = and <3 x i32> %arg, <i32 1, i32 undef, i32 1>
+ %tmp3 = select <3 x i1> %tmp1, <3 x i32> %tmp2, <3 x i32> <i32 1, i32 undef, i32 1>
+ ret <3 x i32> %tmp3
+}
+
+; ============================================================================ ;
+; Mask can be a variable, too.
+; ============================================================================ ;
+
+define i32 @f_var0(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @f_var0(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARG1:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp = and i32 %arg, %arg1
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = lshr i32 %arg, 1
+ %tmp4 = and i32 %tmp3, 1
+ %tmp5 = select i1 %tmp2, i32 %tmp4, i32 1
+ ret i32 %tmp5
+}
+
+; Should be exactly as the previous one
+define i32 @f_var0_commutative_and(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @f_var0_commutative_and(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARG1:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp = and i32 %arg1, %arg ; in different order
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = lshr i32 %arg, 1
+ %tmp4 = and i32 %tmp3, 1
+ %tmp5 = select i1 %tmp2, i32 %tmp4, i32 1
+ ret i32 %tmp5
+}
+
+define <2 x i32> @f_var0_splatvec(<2 x i32> %arg, <2 x i32> %arg1) {
+; CHECK-LABEL: @f_var0_splatvec(
+; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[ARG1:%.*]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i1> [[TMP3]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP5]]
+;
+ %tmp = and <2 x i32> %arg, %arg1
+ %tmp2 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp3 = lshr <2 x i32> %arg, <i32 1, i32 1>
+ %tmp4 = and <2 x i32> %tmp3, <i32 1, i32 1>
+ %tmp5 = select <2 x i1> %tmp2, <2 x i32> %tmp4, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp5
+}
+
+define <2 x i32> @f_var0_vec(<2 x i32> %arg, <2 x i32> %arg1) {
+; CHECK-LABEL: @f_var0_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[ARG1:%.*]], <i32 2, i32 4>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i1> [[TMP3]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP5]]
+;
+ %tmp = and <2 x i32> %arg, %arg1
+ %tmp2 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp3 = lshr <2 x i32> %arg, <i32 1, i32 2> ; shift is not splat
+ %tmp4 = and <2 x i32> %tmp3, <i32 1, i32 1>
+ %tmp5 = select <2 x i1> %tmp2, <2 x i32> %tmp4, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp5
+}
+
+define <3 x i32> @f_var0_vec_undef(<3 x i32> %arg, <3 x i32> %arg1) {
+; CHECK-LABEL: @f_var0_vec_undef(
+; CHECK-NEXT: [[TMP1:%.*]] = or <3 x i32> [[ARG1:%.*]], <i32 2, i32 undef, i32 2>
+; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = zext <3 x i1> [[TMP3]] to <3 x i32>
+; CHECK-NEXT: ret <3 x i32> [[TMP5]]
+;
+ %tmp = and <3 x i32> %arg, %arg1
+ %tmp2 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
+ %tmp3 = lshr <3 x i32> %arg, <i32 1, i32 undef, i32 1>
+ %tmp4 = and <3 x i32> %tmp3, <i32 1, i32 undef, i32 1>
+ %tmp5 = select <3 x i1> %tmp2, <3 x i32> %tmp4, <3 x i32> <i32 1, i32 undef, i32 1>
+ ret <3 x i32> %tmp5
+}
+
+define i32 @f_var1(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @f_var1(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARG1:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, %arg1
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = and i32 %arg, 1
+ %tmp4 = select i1 %tmp2, i32 %tmp3, i32 1
+ ret i32 %tmp4
+}
+
+; Should be exactly as the previous one
+define i32 @f_var1_commutative_and(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @f_var1_commutative_and(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARG1:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg1, %arg ; in different order
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = and i32 %arg, 1
+ %tmp4 = select i1 %tmp2, i32 %tmp3, i32 1
+ ret i32 %tmp4
+}
+
+define <2 x i32> @f_var1_vec(<2 x i32> %arg, <2 x i32> %arg1) {
+; CHECK-LABEL: @f_var1_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[ARG1:%.*]], <i32 1, i32 1>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i1> [[TMP3]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP4]]
+;
+ %tmp = and <2 x i32> %arg, %arg1
+ %tmp2 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp3 = and <2 x i32> %arg, <i32 1, i32 1>
+ %tmp4 = select <2 x i1> %tmp2, <2 x i32> %tmp3, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp4
+}
+
+define <3 x i32> @f_var1_vec_undef(<3 x i32> %arg, <3 x i32> %arg1) {
+; CHECK-LABEL: @f_var1_vec_undef(
+; CHECK-NEXT: [[TMP1:%.*]] = or <3 x i32> [[ARG1:%.*]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = zext <3 x i1> [[TMP3]] to <3 x i32>
+; CHECK-NEXT: ret <3 x i32> [[TMP4]]
+;
+ %tmp = and <3 x i32> %arg, %arg1
+ %tmp2 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
+ %tmp3 = and <3 x i32> %arg, <i32 1, i32 undef, i32 1>
+ %tmp4 = select <3 x i1> %tmp2, <3 x i32> %tmp3, <3 x i32> <i32 1, i32 undef, i32 1>
+ ret <3 x i32> %tmp4
+}
+
+; ============================================================================ ;
+; Shift can be a variable, too.
+; ============================================================================ ;
+
+define i32 @f_var2(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @f_var2(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 1, [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp = and i32 %arg, 1
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = lshr i32 %arg, %arg1
+ %tmp4 = and i32 %tmp3, 1
+ %tmp5 = select i1 %tmp2, i32 %tmp4, i32 1
+ ret i32 %tmp5
+}
+
+define <2 x i32> @f_var2_splatvec(<2 x i32> %arg, <2 x i32> %arg1) {
+; CHECK-LABEL: @f_var2_splatvec(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP5]]
+;
+ %tmp = and <2 x i32> %arg, <i32 1, i32 1>
+ %tmp2 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp3 = lshr <2 x i32> %arg, %arg1
+ %tmp4 = and <2 x i32> %tmp3, <i32 1, i32 1>
+ %tmp5 = select <2 x i1> %tmp2, <2 x i32> %tmp4, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp5
+}
+
+define <2 x i32> @f_var2_vec(<2 x i32> %arg, <2 x i32> %arg1) {
+; CHECK-LABEL: @f_var2_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], <i32 2, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP5]]
+;
+ %tmp = and <2 x i32> %arg, <i32 2, i32 1>; mask is not splat
+ %tmp2 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp3 = lshr <2 x i32> %arg, %arg1
+ %tmp4 = and <2 x i32> %tmp3, <i32 1, i32 1>
+ %tmp5 = select <2 x i1> %tmp2, <2 x i32> %tmp4, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp5
+}
+
+define <3 x i32> @f_var2_vec_undef(<3 x i32> %arg, <3 x i32> %arg1) {
+; CHECK-LABEL: @f_var2_vec_undef(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or <3 x i32> [[TMP1]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = and <3 x i32> [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <3 x i32> [[TMP3]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = zext <3 x i1> [[TMP4]] to <3 x i32>
+; CHECK-NEXT: ret <3 x i32> [[TMP5]]
+;
+ %tmp = and <3 x i32> %arg, <i32 1, i32 undef, i32 1>
+ %tmp2 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
+ %tmp3 = lshr <3 x i32> %arg, %arg1
+ %tmp4 = and <3 x i32> %tmp3, <i32 1, i32 undef, i32 1>
+ %tmp5 = select <3 x i1> %tmp2, <3 x i32> %tmp4, <3 x i32> <i32 1, i32 undef, i32 1>
+ ret <3 x i32> %tmp5
+}
+
+; ============================================================================ ;
+; The worst case: both Mask and Shift are variables
+; ============================================================================ ;
+
+define i32 @f_var3(i32 %arg, i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: @f_var3(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 1, [[ARG2:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
+; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP4]] to i32
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %tmp = and i32 %arg, %arg1
+ %tmp3 = icmp eq i32 %tmp, 0
+ %tmp4 = lshr i32 %arg, %arg2
+ %tmp5 = and i32 %tmp4, 1
+ %tmp6 = select i1 %tmp3, i32 %tmp5, i32 1
+ ret i32 %tmp6
+}
+
+; Should be exactly as the previous one
+define i32 @f_var3_commutative_and(i32 %arg, i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: @f_var3_commutative_and(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 1, [[ARG2:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
+; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP4]] to i32
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %tmp = and i32 %arg1, %arg ; in different order
+ %tmp3 = icmp eq i32 %tmp, 0
+ %tmp4 = lshr i32 %arg, %arg2
+ %tmp5 = and i32 %tmp4, 1
+ %tmp6 = select i1 %tmp3, i32 %tmp5, i32 1
+ ret i32 %tmp6
+}
+
+define <2 x i32> @f_var3_splatvec(<2 x i32> %arg, <2 x i32> %arg1, <2 x i32> %arg2) {
+; CHECK-LABEL: @f_var3_splatvec(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[ARG2:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[TMP6]]
+;
+ %tmp = and <2 x i32> %arg, %arg1
+ %tmp3 = icmp eq <2 x i32> %tmp, zeroinitializer
+ %tmp4 = lshr <2 x i32> %arg, %arg2
+ %tmp5 = and <2 x i32> %tmp4, <i32 1, i32 1>
+ %tmp6 = select <2 x i1> %tmp3, <2 x i32> %tmp5, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %tmp6
+}
+
+define <3 x i32> @f_var3_vec_undef(<3 x i32> %arg, <3 x i32> %arg1, <3 x i32> %arg2) {
+; CHECK-LABEL: @f_var3_vec_undef(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[ARG2:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = or <3 x i32> [[TMP1]], [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = and <3 x i32> [[TMP2]], [[ARG:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <3 x i32> [[TMP3]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = zext <3 x i1> [[TMP4]] to <3 x i32>
+; CHECK-NEXT: ret <3 x i32> [[TMP6]]
+;
+ %tmp = and <3 x i32> %arg, %arg1
+ %tmp3 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
+ %tmp4 = lshr <3 x i32> %arg, %arg2
+ %tmp5 = and <3 x i32> %tmp4, <i32 1, i32 undef, i32 1>
+ %tmp6 = select <3 x i1> %tmp3, <3 x i32> %tmp5, <3 x i32> <i32 1, i32 undef, i32 1>
+ ret <3 x i32> %tmp6
+}
+
+; ============================================================================ ;
+; Negative tests. Should not be folded.
+; ============================================================================ ;
+
+; One use only.
+
+declare void @use32(i32)
+
+declare void @use1(i1)
+
+define i32 @n_var0_oneuse(i32 %arg, i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: @n_var0_oneuse(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[ARG]], [[ARG2:%.*]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
+; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP5]], i32 1
+; CHECK-NEXT: call void @use32(i32 [[TMP]])
+; CHECK-NEXT: call void @use1(i1 [[TMP3]])
+; CHECK-NEXT: call void @use32(i32 [[TMP4]])
+; CHECK-NEXT: call void @use32(i32 [[TMP5]])
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %tmp = and i32 %arg, %arg1
+ %tmp3 = icmp eq i32 %tmp, 0
+ %tmp4 = lshr i32 %arg, %arg2
+ %tmp5 = and i32 %tmp4, 1
+ %tmp6 = select i1 %tmp3, i32 %tmp5, i32 1
+ call void @use32(i32 %tmp)
+ call void @use1(i1 %tmp3)
+ call void @use32(i32 %tmp4)
+ call void @use32(i32 %tmp5)
+ ret i32 %tmp6
+}
+
+define i32 @n_var1_oneuse(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @n_var1_oneuse(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[ARG]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 1
+; CHECK-NEXT: call void @use32(i32 [[TMP]])
+; CHECK-NEXT: call void @use1(i1 [[TMP2]])
+; CHECK-NEXT: call void @use32(i32 [[TMP3]])
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, %arg1
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = and i32 %arg, 1
+ %tmp4 = select i1 %tmp2, i32 %tmp3, i32 1
+ call void @use32(i32 %tmp)
+ call void @use1(i1 %tmp2)
+ call void @use32(i32 %tmp3)
+ ret i32 %tmp4
+}
+
+; Different variables are used
+
+define i32 @n0(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @n0(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[ARG1:%.*]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 1
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i32 [[TMP4]], i32 1
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp = and i32 %arg, 1
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = lshr i32 %arg1, 1 ; works on %arg1 instead of %arg
+ %tmp4 = and i32 %tmp3, 1
+ %tmp5 = select i1 %tmp2, i32 %tmp4, i32 1
+ ret i32 %tmp5
+}
+
+define i32 @n1(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: @n1(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[ARG1:%.*]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 1
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, 2
+ %tmp2 = icmp eq i32 %tmp, 0
+ %tmp3 = and i32 %arg1, 1 ; works on %arg1 instead of %arg
+ %tmp4 = select i1 %tmp2, i32 %tmp3, i32 1
+ ret i32 %tmp4
+}
+
+; False-value is not 1
+
+define i32 @n2(i32 %arg) {
+; CHECK-LABEL: @n2(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[ARG]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], i32 [[TMP3]], i32 0
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, 1
+ %tmp1 = icmp eq i32 %tmp, 0
+ %tmp2 = lshr i32 %arg, 2
+ %tmp3 = and i32 %tmp2, 1
+ %tmp4 = select i1 %tmp1, i32 %tmp3, i32 0 ; 0 instead of 1
+ ret i32 %tmp4
+}
+
+define i32 @n3(i32 %arg) {
+; CHECK-LABEL: @n3(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 0
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %tmp = and i32 %arg, 2
+ %tmp1 = icmp eq i32 %tmp, 0
+ %tmp2 = and i32 %arg, 1
+ %tmp3 = select i1 %tmp1, i32 %tmp2, i32 0 ; 0 instead of 1
+ ret i32 %tmp3
+}
+
+; Mask of second and is not one
+
+define i32 @n4(i32 %arg) {
+; CHECK-LABEL: @n4(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[ARG]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], i32 [[TMP3]], i32 1
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, 1
+ %tmp1 = icmp eq i32 %tmp, 0
+ %tmp2 = lshr i32 %arg, 2
+ %tmp3 = and i32 %tmp2, 2 ; 2 instead of 1
+ %tmp4 = select i1 %tmp1, i32 %tmp3, i32 1
+ ret i32 %tmp4
+}
+
+define i32 @n5(i32 %arg) {
+; CHECK-LABEL: @n5(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 1
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %tmp = and i32 %arg, 2
+ %tmp1 = icmp eq i32 %tmp, 0
+ %tmp2 = and i32 %arg, 2 ; 2 instead of 1
+ %tmp3 = select i1 %tmp1, i32 %tmp2, i32 1
+ ret i32 %tmp3
+}
+
+; Wrong icmp pred
+
+define i32 @n6(i32 %arg) {
+; CHECK-LABEL: @n6(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[ARG]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], i32 1, i32 [[TMP3]]
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, 1
+ %tmp1 = icmp ne i32 %tmp, 0 ; ne, not eq
+ %tmp2 = lshr i32 %arg, 2
+ %tmp3 = and i32 %tmp2, 1
+ %tmp4 = select i1 %tmp1, i32 %tmp3, i32 1
+ ret i32 %tmp4
+}
+
+define i32 @n7(i32 %arg) {
+; CHECK-LABEL: @n7(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i32 1, i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %tmp = and i32 %arg, 2
+ %tmp1 = icmp ne i32 %tmp, 0 ; ne, not eq
+ %tmp2 = and i32 %arg, 1
+ %tmp3 = select i1 %tmp1, i32 %tmp2, i32 1
+ ret i32 %tmp3
+}
+
+; icmp second operand is not zero
+
+define i32 @n8(i32 %arg) {
+; CHECK-LABEL: @n8(
+; CHECK-NEXT: [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[ARG]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], i32 1, i32 [[TMP3]]
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %tmp = and i32 %arg, 1
+ %tmp1 = icmp eq i32 %tmp, 1
+ %tmp2 = lshr i32 %arg, 2
+ %tmp3 = and i32 %tmp2, 1
+ %tmp4 = select i1 %tmp1, i32 %tmp3, i32 1
+ ret i32 %tmp4
+}
Added: llvm/trunk/test/Transforms/InstCombine/select-pr39595.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-pr39595.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-pr39595.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-pr39595.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,18 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @foo(i32 %x, i32 %y) {
+; CHECK-LABEL: foo
+; CHECK: [[TMP1:%.*]] = icmp ult i32 %y, %x
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 %x, i32 %y, !prof ![[$MD0:[0-9]+]]
+; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[TMP3:%.*]]
+; CHECK-DAG: !0 = !{!"branch_weights", i32 6, i32 1}
+
+ %1 = xor i32 %x, -1
+ %2 = xor i32 %y, -1
+ %3 = icmp ugt i32 %1, %2
+ %4 = select i1 %3, i32 %2, i32 %1, !prof !1
+ ret i32 %4
+}
+
+!1 = !{!"branch_weights", i32 1, i32 6}
Added: llvm/trunk/test/Transforms/InstCombine/select-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-select.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-select.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-select.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,34 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+; CHECK: @foo1
+define float @foo1(float %a) #0 {
+; CHECK-NOT: xor
+ %b = fcmp ogt float %a, 0.000000e+00
+ %c = select i1 %b, float %a, float 0.000000e+00
+ %d = fcmp olt float %c, 1.000000e+00
+ %f = select i1 %d, float %c, float 1.000000e+00
+ ret float %f
+}
+
+; CHECK: @foo2
+define float @foo2(float %a) #0 {
+; CHECK-NOT: xor
+ %b = fcmp ogt float %a, 0.000000e+00
+ %c = select i1 %b, float %a, float 0.000000e+00
+ %d = fcmp olt float %c, 1.000000e+00
+ %e = select i1 %b, float %a, float 0.000000e+00
+ %f = select i1 %d, float %e, float 1.000000e+00
+ ret float %f
+}
+
+; CHECK-LABEL: @foo3
+define <2 x i32> @foo3(<2 x i1> %vec_bool, i1 %bool, <2 x i32> %V) {
+; CHECK: %[[sel0:.*]] = select <2 x i1> %vec_bool, <2 x i32> zeroinitializer, <2 x i32> %V
+; CHECK: %[[sel1:.*]] = select i1 %bool, <2 x i32> %[[sel0]], <2 x i32> %V
+; CHECK: ret <2 x i32> %[[sel1]]
+ %sel0 = select <2 x i1> %vec_bool, <2 x i32> zeroinitializer, <2 x i32> %V
+ %sel1 = select i1 %bool, <2 x i32> %sel0, <2 x i32> %V
+ ret <2 x i32> %sel1
+}
+
+attributes #0 = { nounwind readnone ssp uwtable }
Added: llvm/trunk/test/Transforms/InstCombine/select-with-bitwise-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-with-bitwise-ops.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-with-bitwise-ops.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-with-bitwise-ops.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1451 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "n8:16:32:64"
+
+define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2(
+; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @select_icmp_eq_and_1_0_or_2_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2_vec(
+; CHECK-NEXT: [[AND:%.*]] = shl <2 x i32> [[X:%.*]], <i32 1, i32 1>
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+;
+ %and = and <2 x i32> %x, <i32 1, i32 1>
+ %cmp = icmp eq <2 x i32> %and, zeroinitializer
+ %or = or <2 x i32> %y, <i32 2, i32 2>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @select_icmp_eq_and_1_0_xor_2(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_1_0_xor_2(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_eq_and_1_0_and_not_2(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_1_0_and_not_2(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -3
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_32_0_or_8(
+; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 8
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %and = and i32 %x, 32
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 8
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @select_icmp_eq_and_32_0_or_8_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_icmp_eq_and_32_0_or_8_vec(
+; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 8, i32 8>
+; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+;
+ %and = and <2 x i32> %x, <i32 32, i32 32>
+ %cmp = icmp eq <2 x i32> %and, zeroinitializer
+ %or = or <2 x i32> %y, <i32 8, i32 8>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @select_icmp_eq_and_32_0_xor_8(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_32_0_xor_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 8
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 32
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 8
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_eq_and_32_0_and_not_8(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_32_0_and_not_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -9
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 32
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -9
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @select_icmp_ne_0_and_4096_or_4096_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_4096_vec(
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 4096, i32 4096>
+; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[AND]], <i32 4096, i32 4096>
+; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+;
+ %and = and <2 x i32> %x, <i32 4096, i32 4096>
+ %cmp = icmp ne <2 x i32> zeroinitializer, %and
+ %or = or <2 x i32> %y, <i32 4096, i32 4096>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @select_icmp_ne_0_and_4096_xor_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_xor_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_4096_and_not_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_and_not_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_4096_0_or_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @select_icmp_eq_and_4096_0_or_4096_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_icmp_eq_and_4096_0_or_4096_vec(
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 4096, i32 4096>
+; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[AND]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %and = and <2 x i32> %x, <i32 4096, i32 4096>
+ %cmp = icmp eq <2 x i32> %and, zeroinitializer
+ %or = or <2 x i32> %y, <i32 4096, i32 4096>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @select_icmp_eq_and_4096_0_xor_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_4096_0_xor_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_eq_and_4096_0_and_not_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_and_4096_0_and_not_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i32 @select_icmp_eq_0_and_1_or_1(i64 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_0_and_1_or_1(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %and = and i64 %x, 1
+ %cmp = icmp eq i64 %and, 0
+ %or = or i32 %y, 1
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @select_icmp_eq_0_and_1_or_1_vec(<2 x i64> %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_icmp_eq_0_and_1_or_1_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 1, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %and = and <2 x i64> %x, <i64 1, i64 1>
+ %cmp = icmp eq <2 x i64> %and, zeroinitializer
+ %or = or <2 x i32> %y, <i32 1, i32 1>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @select_icmp_eq_0_and_1_xor_1(i64 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_0_and_1_xor_1(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1
+; CHECK-NEXT: [[SELECT:%.*]] = xor i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i64 %x, 1
+ %cmp = icmp eq i64 %and, 0
+ %xor = xor i32 %y, 1
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_eq_0_and_1_and_not_1(i64 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_eq_0_and_1_and_not_1(
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i64 %x, 1
+ %cmp = icmp eq i64 %and, 0
+ %and2 = and i32 %y, -2
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_32(
+; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 7
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 32
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 32
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 32
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_4096_xor_32(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_xor_32(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 32
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 32
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_4096_and_not_32(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_and_not_32(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -33
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -33
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_32_or_4096(
+; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 7
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 4096
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 4096
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %and = and i32 %x, 32
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @select_icmp_ne_0_and_32_or_4096_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_32_or_4096_vec(
+; CHECK-NEXT: [[AND:%.*]] = shl <2 x i32> [[X:%.*]], <i32 7, i32 7>
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 4096, i32 4096>
+; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], <i32 4096, i32 4096>
+; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %and = and <2 x i32> %x, <i32 32, i32 32>
+ %cmp = icmp ne <2 x i32> zeroinitializer, %and
+ %or = or <2 x i32> %y, <i32 4096, i32 4096>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @select_icmp_ne_0_and_32_xor_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_32_xor_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 32
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_32_and_not_4096(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_32_and_not_4096(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 32
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i8 @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_or_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], 8
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[OR]], i8 [[Y]]
+; CHECK-NEXT: ret i8 [[SELECT]]
+;
+ %and = and i32 %x, 1073741824
+ %cmp = icmp ne i32 0, %and
+ %or = or i8 %y, 8
+ %select = select i1 %cmp, i8 %y, i8 %or
+ ret i8 %select
+}
+
+define i8 @select_icmp_ne_0_and_1073741824_xor_8(i32 %x, i8 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_xor_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[Y:%.*]], 8
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[XOR]], i8 [[Y]]
+; CHECK-NEXT: ret i8 [[SELECT]]
+;
+ %and = and i32 %x, 1073741824
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i8 %y, 8
+ %select = select i1 %cmp, i8 %y, i8 %xor
+ ret i8 %select
+}
+
+define i8 @select_icmp_ne_0_and_1073741824_and_not_8(i32 %x, i8 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_and_not_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i8 [[Y:%.*]], -9
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[AND2]], i8 [[Y]]
+; CHECK-NEXT: ret i8 [[SELECT]]
+;
+ %and = and i32 %x, 1073741824
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i8 %y, -9
+ %select = select i1 %cmp, i8 %y, i8 %and2
+ ret i8 %select
+}
+
+define i32 @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_8_or_1073741824(
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 1073741824
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i8 %x, 8
+ %cmp = icmp ne i8 0, %and
+ %or = or i32 %y, 1073741824
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_8_xor_1073741824(i8 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_8_xor_1073741824(
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 1073741824
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i8 %x, 8
+ %cmp = icmp ne i8 0, %and
+ %xor = xor i32 %y, 1073741824
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @select_icmp_ne_0_and_8_and_not_1073741824(i8 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_ne_0_and_8_and_not_1073741824(
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -1073741825
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i8 %x, 8
+ %cmp = icmp ne i8 0, %and
+ %and2 = and i32 %y, -1073741825
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+; We can't combine here, because the cmp is scalar and the or vector.
+; Just make sure we don't assert.
+define <2 x i32> @select_icmp_eq_and_1_0_or_vector_of_2s(i32 %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_icmp_eq_and_1_0_or_vector_of_2s(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[Y:%.*]], <i32 2, i32 2>
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], <2 x i32> [[Y]], <2 x i32> [[OR]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or <2 x i32> %y, <i32 2, i32 2>
+ %select = select i1 %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @select_icmp_and_8_ne_0_xor_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_ne_0_xor_8(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -9
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %and = and i32 %x, 8
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %x, 8
+ %x.xor = select i1 %cmp, i32 %x, i32 %xor
+ ret i32 %x.xor
+}
+
+define i32 @select_icmp_and_8_eq_0_xor_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_eq_0_xor_8(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], 8
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %and = and i32 %x, 8
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %x, 8
+ %xor.x = select i1 %cmp, i32 %xor, i32 %x
+ ret i32 %xor.x
+}
+
+define i64 @select_icmp_x_and_8_eq_0_y_xor_8(i32 %x, i64 %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_eq_0_y_xor_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i64 [[Y:%.*]], 8
+; CHECK-NEXT: [[Y_XOR:%.*]] = select i1 [[CMP]], i64 [[Y]], i64 [[XOR]]
+; CHECK-NEXT: ret i64 [[Y_XOR]]
+;
+ %and = and i32 %x, 8
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i64 %y, 8
+ %y.xor = select i1 %cmp, i64 %y, i64 %xor
+ ret i64 %y.xor
+}
+
+define i64 @select_icmp_x_and_8_ne_0_y_xor_8(i32 %x, i64 %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_xor_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i64 [[Y:%.*]], 8
+; CHECK-NEXT: [[XOR_Y:%.*]] = select i1 [[CMP]], i64 [[XOR]], i64 [[Y]]
+; CHECK-NEXT: ret i64 [[XOR_Y]]
+;
+ %and = and i32 %x, 8
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i64 %y, 8
+ %xor.y = select i1 %cmp, i64 %xor, i64 %y
+ ret i64 %xor.y
+}
+
+define i64 @select_icmp_x_and_8_ne_0_y_or_8(i32 %x, i64 %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_or_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 8
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i64 [[TMP3]]
+;
+ %and = and i32 %x, 8
+ %cmp = icmp eq i32 %and, 0
+ %or = or i64 %y, 8
+ %or.y = select i1 %cmp, i64 %or, i64 %y
+ ret i64 %or.y
+}
+
+define <2 x i64> @select_icmp_x_and_8_ne_0_y_or_8_vec(<2 x i32> %x, <2 x i64> %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_or_8_vec(
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 8, i32 8>
+; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[AND]], <i32 8, i32 8>
+; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i64> [[TMP3]]
+;
+ %and = and <2 x i32> %x, <i32 8, i32 8>
+ %cmp = icmp eq <2 x i32> %and, zeroinitializer
+ %or = or <2 x i64> %y, <i64 8, i64 8>
+ %or.y = select <2 x i1> %cmp, <2 x i64> %or, <2 x i64> %y
+ ret <2 x i64> %or.y
+}
+
+define i64 @select_icmp_x_and_8_ne_0_y_and_not_8(i32 %x, i64 %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_and_not_8(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], -9
+; CHECK-NEXT: [[AND_Y:%.*]] = select i1 [[CMP]], i64 [[AND2]], i64 [[Y]]
+; CHECK-NEXT: ret i64 [[AND_Y]]
+;
+ %and = and i32 %x, 8
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i64 %y, -9
+ %and.y = select i1 %cmp, i64 %and2, i64 %y
+ ret i64 %and.y
+}
+
+define i32 @select_icmp_and_2147483648_ne_0_xor_2147483648(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_2147483648_ne_0_xor_2147483648(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %and = and i32 %x, 2147483648
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %x, 2147483648
+ %x.xor = select i1 %cmp, i32 %x, i32 %xor
+ ret i32 %x.xor
+}
+
+define i32 @select_icmp_and_2147483648_eq_0_xor_2147483648(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_2147483648_eq_0_xor_2147483648(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %and = and i32 %x, 2147483648
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %x, 2147483648
+ %xor.x = select i1 %cmp, i32 %xor, i32 %x
+ ret i32 %xor.x
+}
+
+define i32 @select_icmp_x_and_2147483648_ne_0_or_2147483648(i32 %x) {
+; CHECK-LABEL: @select_icmp_x_and_2147483648_ne_0_or_2147483648(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %and = and i32 %x, 2147483648
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %x, 2147483648
+ %or.x = select i1 %cmp, i32 %or, i32 %x
+ ret i32 %or.x
+}
+
+define i32 @test68(i32 %x, i32 %y) {
+; CHECK-LABEL: @test68(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @test68vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @test68vec(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 6, i32 6>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %and = and <2 x i32> %x, <i32 128, i32 128>
+ %cmp = icmp eq <2 x i32> %and, zeroinitializer
+ %or = or <2 x i32> %y, <i32 2, i32 2>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @test68_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @test68_xor(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[TMP1]], -1
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @test68_and(i32 %x, i32 %y) {
+; CHECK-LABEL: @test68_and(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[TMP1]], -1
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -3
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i32 @test69(i32 %x, i32 %y) {
+; CHECK-LABEL: @test69(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[TMP4]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp ne i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define <2 x i32> @test69vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @test69vec(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 6, i32 6>
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[TMP2]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP3]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[TMP4]]
+;
+ %and = and <2 x i32> %x, <i32 128, i32 128>
+ %cmp = icmp ne <2 x i32> %and, zeroinitializer
+ %or = or <2 x i32> %y, <i32 2, i32 2>
+ %select = select <2 x i1> %cmp, <2 x i32> %y, <2 x i32> %or
+ ret <2 x i32> %select
+}
+
+define i32 @test69_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @test69_xor(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp ne i32 %and, 0
+ %xor = xor i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ ret i32 %select
+}
+
+define i32 @test69_and(i32 %x, i32 %y) {
+; CHECK-LABEL: @test69_and(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp ne i32 %and, 0
+ %and2 = and i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ ret i32 %select
+}
+
+define i8 @test70(i8 %x, i8 %y) {
+; CHECK-LABEL: @test70(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[OR]], i8 [[Y]]
+; CHECK-NEXT: ret i8 [[SELECT]]
+;
+ %cmp = icmp slt i8 %x, 0
+ %or = or i8 %y, 2
+ %select = select i1 %cmp, i8 %or, i8 %y
+ ret i8 %select
+}
+
+define i32 @shift_no_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_no_xor_multiuse_or(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+define i32 @shift_no_xor_multiuse_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_no_xor_multiuse_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %res = mul i32 %select, %xor ; to bump up use count of the Xor
+ ret i32 %res
+}
+
+define i32 @shift_no_xor_multiuse_and(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_no_xor_multiuse_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -3
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %res = mul i32 %select, %and2 ; to bump up use count of the And
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %res = mul i32 %select, %xor ; to bump up use count of the Xor
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_and(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = add i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %and2 = add i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %res = mul i32 %select, %and2 ; to bump up use count of the And
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_xor_multiuse_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_xor_multiuse_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %res = mul i32 %select, %xor ; to bump up use count of the Xor
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_and(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_xor_multiuse_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %res = mul i32 %select, %and2 ; to bump up use count of the And
+ ret i32 %res
+}
+
+define i32 @shift_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_xor_multiuse_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+define i32 @shift_xor_multiuse_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_xor_multiuse_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %res = mul i32 %select, %xor ; to bump up use count of the Xor
+ ret i32 %res
+}
+
+define i32 @shift_xor_multiuse_and(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_xor_multiuse_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2049
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]], i32 [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -2049
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %res = mul i32 %select, %and2 ; to bump up use count of the and
+ ret i32 %res
+}
+
+define i32 @shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @shift_no_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp_with_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @shift_no_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp_with_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -3
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp_with_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp_with_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[W:%.*]], i32 [[Z:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp_with_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp_with_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp_with_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp_with_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2049
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -2049
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
+
+define i32 @shift_no_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %xor ; to bump up the use count of the xor
+ ret i32 %res2
+}
+
+define i32 @shift_no_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -3
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -3
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %and2 ; to bump up the use count of the and
+ ret i32 %res2
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %xor ; to bump up the use count of the xor
+ ret i32 %res2
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %and2 ; to bump up the use count of the and
+ ret i32 %res2
+}
+
+define i32 @no_shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
+
+define i32 @no_shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %xor ; to bump up the use count of the xor
+ ret i32 %res2
+}
+
+define i32 @no_shift_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, -4097
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %and2 ; to bump up the use count of the and
+ ret i32 %res2
+}
+
+define i32 @shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
+
+define i32 @shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp_xor(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %xor = xor i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %xor
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %xor ; to bump up the use count of the xor
+ ret i32 %res2
+}
+
+define i32 @shift_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp_and(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND2]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %and2 = and i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %and2
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %and2 ; to bump up the use count of the and
+ ret i32 %res2
+}
Added: llvm/trunk/test/Transforms/InstCombine/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1506 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; PR1822
+
+target datalayout = "e-p:64:64-p1:16:16-p2:32:32:32-p3:64:64:64"
+
+define i32 @test1(i32 %A, i32 %B) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: ret i32 [[B:%.*]]
+;
+ %C = select i1 false, i32 %A, i32 %B
+ ret i32 %C
+}
+
+define i32 @test2(i32 %A, i32 %B) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: ret i32 [[A:%.*]]
+;
+ %C = select i1 true, i32 %A, i32 %B
+ ret i32 %C
+}
+
+
+define i32 @test3(i1 %C, i32 %I) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: ret i32 [[I:%.*]]
+;
+ %V = select i1 %C, i32 %I, i32 %I
+ ret i32 %V
+}
+
+define i1 @test4(i1 %C) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: ret i1 [[C:%.*]]
+;
+ %V = select i1 %C, i1 true, i1 false
+ ret i1 %V
+}
+
+define i1 @test5(i1 %C) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT: ret i1 [[NOT_C]]
+;
+ %V = select i1 %C, i1 false, i1 true
+ ret i1 %V
+}
+
+define i32 @test6(i1 %C) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[V:%.*]] = zext i1 [[C:%.*]] to i32
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %V = select i1 %C, i32 1, i32 0
+ ret i32 %V
+}
+
+define i1 @trueval_is_true(i1 %C, i1 %X) {
+; CHECK-LABEL: @trueval_is_true(
+; CHECK-NEXT: [[R:%.*]] = or i1 [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %R = select i1 %C, i1 true, i1 %X
+ ret i1 %R
+}
+
+define <2 x i1> @trueval_is_true_vec(<2 x i1> %C, <2 x i1> %X) {
+; CHECK-LABEL: @trueval_is_true_vec(
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %R = select <2 x i1> %C, <2 x i1> <i1 true, i1 true>, <2 x i1> %X
+ ret <2 x i1> %R
+}
+
+define <2 x i1> @trueval_is_true_vec_undef_elt(<2 x i1> %C, <2 x i1> %X) {
+; CHECK-LABEL: @trueval_is_true_vec_undef_elt(
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %R = select <2 x i1> %C, <2 x i1> <i1 undef, i1 true>, <2 x i1> %X
+ ret <2 x i1> %R
+}
+
+define i1 @test8(i1 %C, i1 %X) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %R = select i1 %C, i1 %X, i1 false
+ ret i1 %R
+}
+
+define <2 x i1> @test8vec(<2 x i1> %C, <2 x i1> %X) {
+; CHECK-LABEL: @test8vec(
+; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[C:%.*]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %R = select <2 x i1> %C, <2 x i1> %X, <2 x i1> <i1 false, i1 false>
+ ret <2 x i1> %R
+}
+
+define i1 @test9(i1 %C, i1 %X) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT: [[R:%.*]] = and i1 [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %R = select i1 %C, i1 false, i1 %X
+ ret i1 %R
+}
+
+define <2 x i1> @test9vec(<2 x i1> %C, <2 x i1> %X) {
+; CHECK-LABEL: @test9vec(
+; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true>
+; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %R = select <2 x i1> %C, <2 x i1> <i1 false, i1 false>, <2 x i1> %X
+ ret <2 x i1> %R
+}
+
+define i1 @test10(i1 %C, i1 %X) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT: [[R:%.*]] = or i1 [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %R = select i1 %C, i1 %X, i1 true
+ ret i1 %R
+}
+
+define <2 x i1> @test10vec(<2 x i1> %C, <2 x i1> %X) {
+; CHECK-LABEL: @test10vec(
+; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[NOT_C]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %R = select <2 x i1> %C, <2 x i1> %X, <2 x i1> <i1 true, i1 true>
+ ret <2 x i1> %R
+}
+
+define i1 @test23(i1 %a, i1 %b) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT: [[C:%.*]] = and i1 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %c = select i1 %a, i1 %b, i1 %a
+ ret i1 %c
+}
+
+define <2 x i1> @test23vec(<2 x i1> %a, <2 x i1> %b) {
+; CHECK-LABEL: @test23vec(
+; CHECK-NEXT: [[C:%.*]] = and <2 x i1> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %c = select <2 x i1> %a, <2 x i1> %b, <2 x i1> %a
+ ret <2 x i1> %c
+}
+
+define i1 @test24(i1 %a, i1 %b) {
+; CHECK-LABEL: @test24(
+; CHECK-NEXT: [[C:%.*]] = or i1 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %c = select i1 %a, i1 %a, i1 %b
+ ret i1 %c
+}
+
+define <2 x i1> @test24vec(<2 x i1> %a, <2 x i1> %b) {
+; CHECK-LABEL: @test24vec(
+; CHECK-NEXT: [[C:%.*]] = or <2 x i1> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %c = select <2 x i1> %a, <2 x i1> %a, <2 x i1> %b
+ ret <2 x i1> %c
+}
+
+define i1 @test62(i1 %A, i1 %B) {
+; CHECK-LABEL: @test62(
+; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[A:%.*]], true
+; CHECK-NEXT: [[C:%.*]] = and i1 [[NOT]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %not = xor i1 %A, true
+ %C = select i1 %A, i1 %not, i1 %B
+ ret i1 %C
+}
+
+define <2 x i1> @test62vec(<2 x i1> %A, <2 x i1> %B) {
+; CHECK-LABEL: @test62vec(
+; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i1> [[A:%.*]], <i1 true, i1 true>
+; CHECK-NEXT: [[C:%.*]] = and <2 x i1> [[NOT]], [[B:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %not = xor <2 x i1> %A, <i1 true, i1 true>
+ %C = select <2 x i1> %A, <2 x i1> %not, <2 x i1> %B
+ ret <2 x i1> %C
+}
+
+define i1 @test63(i1 %A, i1 %B) {
+; CHECK-LABEL: @test63(
+; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[A:%.*]], true
+; CHECK-NEXT: [[C:%.*]] = or i1 [[NOT]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %not = xor i1 %A, true
+ %C = select i1 %A, i1 %B, i1 %not
+ ret i1 %C
+}
+
+define <2 x i1> @test63vec(<2 x i1> %A, <2 x i1> %B) {
+; CHECK-LABEL: @test63vec(
+; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i1> [[A:%.*]], <i1 true, i1 true>
+; CHECK-NEXT: [[C:%.*]] = or <2 x i1> [[NOT]], [[B:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %not = xor <2 x i1> %A, <i1 true, i1 true>
+ %C = select <2 x i1> %A, <2 x i1> %B, <2 x i1> %not
+ ret <2 x i1> %C
+}
+
+define i32 @test11(i32 %a) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A:%.*]], 0
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[C]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %C = icmp eq i32 %a, 0
+ %R = select i1 %C, i32 0, i32 1
+ ret i32 %R
+}
+
+define i32 @test12(i1 %cond, i32 %a) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: [[B:%.*]] = zext i1 [[COND:%.*]] to i32
+; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], [[A:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %b = or i32 %a, 1
+ %c = select i1 %cond, i32 %b, i32 %a
+ ret i32 %c
+}
+
+define <2 x i32> @test12vec(<2 x i1> %cond, <2 x i32> %a) {
+; CHECK-LABEL: @test12vec(
+; CHECK-NEXT: [[B:%.*]] = zext <2 x i1> [[COND:%.*]] to <2 x i32>
+; CHECK-NEXT: [[C:%.*]] = or <2 x i32> [[B]], [[A:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[C]]
+;
+ %b = or <2 x i32> %a, <i32 1, i32 1>
+ %c = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> %a
+ ret <2 x i32> %c
+}
+
+define i32 @test12a(i1 %cond, i32 %a) {
+; CHECK-LABEL: @test12a(
+; CHECK-NEXT: [[B:%.*]] = zext i1 [[COND:%.*]] to i32
+; CHECK-NEXT: [[C:%.*]] = ashr i32 [[A:%.*]], [[B]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %b = ashr i32 %a, 1
+ %c = select i1 %cond, i32 %b, i32 %a
+ ret i32 %c
+}
+
+define <2 x i32> @test12avec(<2 x i1> %cond, <2 x i32> %a) {
+; CHECK-LABEL: @test12avec(
+; CHECK-NEXT: [[B:%.*]] = zext <2 x i1> [[COND:%.*]] to <2 x i32>
+; CHECK-NEXT: [[C:%.*]] = ashr <2 x i32> [[A:%.*]], [[B]]
+; CHECK-NEXT: ret <2 x i32> [[C]]
+;
+ %b = ashr <2 x i32> %a, <i32 1, i32 1>
+ %c = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> %a
+ ret <2 x i32> %c
+}
+
+define i32 @test12b(i1 %cond, i32 %a) {
+; CHECK-LABEL: @test12b(
+; CHECK-NEXT: [[NOT_COND:%.*]] = xor i1 [[COND:%.*]], true
+; CHECK-NEXT: [[B:%.*]] = zext i1 [[NOT_COND]] to i32
+; CHECK-NEXT: [[D:%.*]] = ashr i32 [[A:%.*]], [[B]]
+; CHECK-NEXT: ret i32 [[D]]
+;
+ %b = ashr i32 %a, 1
+ %d = select i1 %cond, i32 %a, i32 %b
+ ret i32 %d
+}
+
+define <2 x i32> @test12bvec(<2 x i1> %cond, <2 x i32> %a) {
+; CHECK-LABEL: @test12bvec(
+; CHECK-NEXT: [[NOT_COND:%.*]] = xor <2 x i1> [[COND:%.*]], <i1 true, i1 true>
+; CHECK-NEXT: [[B:%.*]] = zext <2 x i1> [[NOT_COND]] to <2 x i32>
+; CHECK-NEXT: [[D:%.*]] = ashr <2 x i32> [[A:%.*]], [[B]]
+; CHECK-NEXT: ret <2 x i32> [[D]]
+;
+ %b = ashr <2 x i32> %a, <i32 1, i32 1>
+ %d = select <2 x i1> %cond, <2 x i32> %a, <2 x i32> %b
+ ret <2 x i32> %d
+}
+
+define i32 @test13(i32 %a, i32 %b) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: ret i32 [[B:%.*]]
+;
+ %C = icmp eq i32 %a, %b
+ %V = select i1 %C, i32 %a, i32 %b
+ ret i32 %V
+}
+
+define i32 @test13a(i32 %a, i32 %b) {
+; CHECK-LABEL: @test13a(
+; CHECK-NEXT: ret i32 [[A:%.*]]
+;
+ %C = icmp ne i32 %a, %b
+ %V = select i1 %C, i32 %a, i32 %b
+ ret i32 %V
+}
+
+define i32 @test13b(i32 %a, i32 %b) {
+; CHECK-LABEL: @test13b(
+; CHECK-NEXT: ret i32 [[A:%.*]]
+;
+ %C = icmp eq i32 %a, %b
+ %V = select i1 %C, i32 %b, i32 %a
+ ret i32 %V
+}
+
+define i1 @test14a(i1 %C, i32 %X) {
+; CHECK-LABEL: @test14a(
+; CHECK-NEXT: [[R1:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT: [[R:%.*]] = or i1 [[R1]], [[NOT_C]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %V = select i1 %C, i32 %X, i32 0
+ ; (X < 1) | !C
+ %R = icmp slt i32 %V, 1
+ ret i1 %R
+}
+
+define i1 @test14b(i1 %C, i32 %X) {
+; CHECK-LABEL: @test14b(
+; CHECK-NEXT: [[R1:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT: [[R:%.*]] = or i1 [[R1]], [[C:%.*]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %V = select i1 %C, i32 0, i32 %X
+ ; (X < 1) | C
+ %R = icmp slt i32 %V, 1
+ ret i1 %R
+}
+
+define i32 @test16(i1 %C, i32* %P) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %P2 = select i1 %C, i32* %P, i32* null
+ %V = load i32, i32* %P2
+ ret i32 %V
+}
+
+;; It may be legal to load from a null address in a non-zero address space
+define i32 @test16_neg(i1 %C, i32 addrspace(1)* %P) {
+; CHECK-LABEL: @test16_neg(
+; CHECK-NEXT: [[P2:%.*]] = select i1 [[C:%.*]], i32 addrspace(1)* [[P:%.*]], i32 addrspace(1)* null
+; CHECK-NEXT: [[V:%.*]] = load i32, i32 addrspace(1)* [[P2]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %P2 = select i1 %C, i32 addrspace(1)* %P, i32 addrspace(1)* null
+ %V = load i32, i32 addrspace(1)* %P2
+ ret i32 %V
+}
+
+define i32 @test16_neg2(i1 %C, i32 addrspace(1)* %P) {
+; CHECK-LABEL: @test16_neg2(
+; CHECK-NEXT: [[P2:%.*]] = select i1 [[C:%.*]], i32 addrspace(1)* null, i32 addrspace(1)* [[P:%.*]]
+; CHECK-NEXT: [[V:%.*]] = load i32, i32 addrspace(1)* [[P2]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %P2 = select i1 %C, i32 addrspace(1)* null, i32 addrspace(1)* %P
+ %V = load i32, i32 addrspace(1)* %P2
+ ret i32 %V
+}
+
+;; It may be legal to load from a null address with null pointer valid attribute.
+define i32 @test16_no_null_opt(i1 %C, i32* %P) #0 {
+; CHECK-LABEL: @test16_no_null_opt(
+; CHECK-NEXT: [[P2:%.*]] = select i1 [[C:%.*]], i32* [[P:%.*]], i32* null
+; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P2]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %P2 = select i1 %C, i32* %P, i32* null
+ %V = load i32, i32* %P2
+ ret i32 %V
+}
+
+define i32 @test16_no_null_opt_2(i1 %C, i32* %P) #0 {
+; CHECK-LABEL: @test16_no_null_opt_2(
+; CHECK-NEXT: [[P2:%.*]] = select i1 [[C:%.*]], i32* null, i32* [[P:%.*]]
+; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P2]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %P2 = select i1 %C, i32* null, i32* %P
+ %V = load i32, i32* %P2
+ ret i32 %V
+}
+
+attributes #0 = { "null-pointer-is-valid"="true" }
+
+define i1 @test17(i32* %X, i1 %C) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[RV1:%.*]] = icmp eq i32* [[X:%.*]], null
+; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT: [[RV:%.*]] = or i1 [[RV1]], [[NOT_C]]
+; CHECK-NEXT: ret i1 [[RV]]
+;
+ %R = select i1 %C, i32* %X, i32* null
+ %RV = icmp eq i32* %R, null
+ ret i1 %RV
+}
+
+define i32 @test18(i32 %X, i32 %Y, i1 %C) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: [[V:%.*]] = sdiv i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %R = select i1 %C, i32 %X, i32 0
+ %V = sdiv i32 %Y, %R
+ ret i32 %V
+}
+
+define i32 @test19(i32 %x) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X:%.*]], 31
+; CHECK-NEXT: ret i32 [[X_LOBIT]]
+;
+ %tmp = icmp ugt i32 %x, 2147483647
+ %retval = select i1 %tmp, i32 -1, i32 0
+ ret i32 %retval
+}
+
+define i32 @test20(i32 %x) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X:%.*]], 31
+; CHECK-NEXT: ret i32 [[X_LOBIT]]
+;
+ %tmp = icmp slt i32 %x, 0
+ %retval = select i1 %tmp, i32 -1, i32 0
+ ret i32 %retval
+}
+
+define i64 @test21(i32 %x) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X:%.*]], 31
+; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[X_LOBIT]] to i64
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %tmp = icmp slt i32 %x, 0
+ %retval = select i1 %tmp, i64 -1, i64 0
+ ret i64 %retval
+}
+
+define i16 @test22(i32 %x) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X:%.*]], 31
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X_LOBIT]] to i16
+; CHECK-NEXT: ret i16 [[TMP1]]
+;
+ %tmp = icmp slt i32 %x, 0
+ %retval = select i1 %tmp, i16 -1, i16 0
+ ret i16 %retval
+}
+
+define i32 @test25(i1 %c) {
+; CHECK-LABEL: @test25(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[JUMP:%.*]], label [[RET:%.*]]
+; CHECK: jump:
+; CHECK-NEXT: br label [[RET]]
+; CHECK: ret:
+; CHECK-NEXT: [[A:%.*]] = phi i32 [ 10, [[JUMP]] ], [ 20, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[A]]
+;
+entry:
+ br i1 %c, label %jump, label %ret
+jump:
+ br label %ret
+ret:
+ %a = phi i1 [true, %jump], [false, %entry]
+ %b = select i1 %a, i32 10, i32 20
+ ret i32 %b
+}
+
+define i32 @test26(i1 %cond) {
+; CHECK-LABEL: @test26(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[JUMP:%.*]], label [[RET:%.*]]
+; CHECK: jump:
+; CHECK-NEXT: br label [[RET]]
+; CHECK: ret:
+; CHECK-NEXT: [[A:%.*]] = phi i32 [ 20, [[ENTRY:%.*]] ], [ 10, [[JUMP]] ]
+; CHECK-NEXT: ret i32 [[A]]
+;
+entry:
+ br i1 %cond, label %jump, label %ret
+jump:
+ %c = or i1 false, false
+ br label %ret
+ret:
+ %a = phi i1 [true, %entry], [%c, %jump]
+ %b = select i1 %a, i32 20, i32 10
+ ret i32 %b
+}
+
+define i32 @test27(i1 %c, i32 %A, i32 %B) {
+; CHECK-LABEL: @test27(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[JUMP:%.*]], label [[RET:%.*]]
+; CHECK: jump:
+; CHECK-NEXT: br label [[RET]]
+; CHECK: ret:
+; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[A:%.*]], [[JUMP]] ], [ [[B:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[P]]
+;
+entry:
+ br i1 %c, label %jump, label %ret
+jump:
+ br label %ret
+ret:
+ %p = phi i1 [true, %jump], [false, %entry]
+ %s = select i1 %p, i32 %A, i32 %B
+ ret i32 %s
+}
+
+define i32 @test28(i1 %cond, i32 %A, i32 %B) {
+; CHECK-LABEL: @test28(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[JUMP:%.*]], label [[RET:%.*]]
+; CHECK: jump:
+; CHECK-NEXT: br label [[RET]]
+; CHECK: ret:
+; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[A:%.*]], [[JUMP]] ], [ [[B:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[P]]
+;
+entry:
+ br i1 %cond, label %jump, label %ret
+jump:
+ br label %ret
+ret:
+ %c = phi i32 [%A, %jump], [%B, %entry]
+ %p = phi i1 [true, %jump], [false, %entry]
+ %s = select i1 %p, i32 %A, i32 %c
+ ret i32 %s
+}
+
+define i32 @test29(i1 %cond, i32 %A, i32 %B) {
+; CHECK-LABEL: @test29(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[JUMP:%.*]], label [[RET:%.*]]
+; CHECK: jump:
+; CHECK-NEXT: br label [[RET]]
+; CHECK: ret:
+; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[A:%.*]], [[JUMP]] ], [ [[B:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: br label [[NEXT:%.*]]
+; CHECK: next:
+; CHECK-NEXT: ret i32 [[P]]
+;
+entry:
+ br i1 %cond, label %jump, label %ret
+jump:
+ br label %ret
+ret:
+ %c = phi i32 [%A, %jump], [%B, %entry]
+ %p = phi i1 [true, %jump], [false, %entry]
+ br label %next
+
+next:
+ %s = select i1 %p, i32 %A, i32 %c
+ ret i32 %s
+}
+
+; SMAX(SMAX(x, y), x) -> SMAX(x, y)
+define i32 @test30(i32 %x, i32 %y) {
+; CHECK-LABEL: @test30(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp sgt i32 %x, %y
+ %cond = select i1 %cmp, i32 %x, i32 %y
+ %cmp5 = icmp sgt i32 %cond, %x
+ %retval = select i1 %cmp5, i32 %cond, i32 %x
+ ret i32 %retval
+}
+
+; UMAX(UMAX(x, y), x) -> UMAX(x, y)
+define i32 @test31(i32 %x, i32 %y) {
+; CHECK-LABEL: @test31(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp ugt i32 %x, %y
+ %cond = select i1 %cmp, i32 %x, i32 %y
+ %cmp5 = icmp ugt i32 %cond, %x
+ %retval = select i1 %cmp5, i32 %cond, i32 %x
+ ret i32 %retval
+}
+
+; SMIN(SMIN(x, y), x) -> SMIN(x, y)
+define i32 @test32(i32 %x, i32 %y) {
+; CHECK-LABEL: @test32(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[X]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp sgt i32 %x, %y
+ %cond = select i1 %cmp, i32 %y, i32 %x
+ %cmp5 = icmp sgt i32 %cond, %x
+ %retval = select i1 %cmp5, i32 %x, i32 %cond
+ ret i32 %retval
+}
+
+; MAX(MIN(x, y), x) -> x
+define i32 @test33(i32 %x, i32 %y) {
+; CHECK-LABEL: @test33(
+; CHECK-NEXT: ret i32 [[X:%.*]]
+;
+ %cmp = icmp sgt i32 %x, %y
+ %cond = select i1 %cmp, i32 %y, i32 %x
+ %cmp5 = icmp sgt i32 %cond, %x
+ %retval = select i1 %cmp5, i32 %cond, i32 %x
+ ret i32 %retval
+}
+
+; MIN(MAX(x, y), x) -> x
+define i32 @test34(i32 %x, i32 %y) {
+; CHECK-LABEL: @test34(
+; CHECK-NEXT: ret i32 [[X:%.*]]
+;
+ %cmp = icmp sgt i32 %x, %y
+ %cond = select i1 %cmp, i32 %x, i32 %y
+ %cmp5 = icmp sgt i32 %cond, %x
+ %retval = select i1 %cmp5, i32 %x, i32 %cond
+ ret i32 %retval
+}
+
+define i1 @test38(i1 %cond) {
+; CHECK-LABEL: @test38(
+; CHECK-NEXT: ret i1 false
+;
+ %zero = alloca i32
+ %one = alloca i32
+ %ptr = select i1 %cond, i32* %zero, i32* %one
+ %isnull = icmp eq i32* %ptr, null
+ ret i1 %isnull
+}
+
+define i1 @test39(i1 %cond, double %x) {
+; CHECK-LABEL: @test39(
+; CHECK-NEXT: ret i1 true
+;
+ %s = select i1 %cond, double %x, double 0x7FF0000000000000 ; RHS = +infty
+ %cmp = fcmp ule double %x, %s
+ ret i1 %cmp
+}
+
+define i1 @test40(i1 %cond) {
+; CHECK-LABEL: @test40(
+; CHECK-NEXT: ret i1 false
+;
+ %a = alloca i32
+ %b = alloca i32
+ %c = alloca i32
+ %s = select i1 %cond, i32* %a, i32* %b
+ %r = icmp eq i32* %s, %c
+ ret i1 %r
+}
+
+define i32 @test41(i1 %cond, i32 %x, i32 %y) {
+; CHECK-LABEL: @test41(
+; CHECK-NEXT: [[R:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %z = and i32 %x, %y
+ %s = select i1 %cond, i32 %y, i32 %z
+ %r = and i32 %x, %s
+ ret i32 %r
+}
+
+define i32 @test42(i32 %x, i32 %y) {
+; CHECK-LABEL: @test42(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[COND]] to i32
+; CHECK-NEXT: [[C:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %b = add i32 %y, -1
+ %cond = icmp eq i32 %x, 0
+ %c = select i1 %cond, i32 %b, i32 %y
+ ret i32 %c
+}
+
+define <2 x i32> @test42vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @test42vec(
+; CHECK-NEXT: [[COND:%.*]] = icmp eq <2 x i32> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[COND]] to <2 x i32>
+; CHECK-NEXT: [[C:%.*]] = sub <2 x i32> [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i32> [[C]]
+;
+ %b = add <2 x i32> %y, <i32 -1, i32 -1>
+ %cond = icmp eq <2 x i32> %x, zeroinitializer
+ %c = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> %y
+ ret <2 x i32> %c
+}
+
+; PR8994
+
+; This select instruction can't be eliminated because trying to do so would
+; change the number of vector elements. This used to assert.
+define i48 @test51(<3 x i1> %icmp, <3 x i16> %tmp) {
+; CHECK-LABEL: @test51(
+; CHECK-NEXT: [[SELECT:%.*]] = select <3 x i1> [[ICMP:%.*]], <3 x i16> zeroinitializer, <3 x i16> [[TMP:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast <3 x i16> [[SELECT]] to i48
+; CHECK-NEXT: ret i48 [[TMP2]]
+;
+ %select = select <3 x i1> %icmp, <3 x i16> zeroinitializer, <3 x i16> %tmp
+ %tmp2 = bitcast <3 x i16> %select to i48
+ ret i48 %tmp2
+}
+
+; Allow select promotion even if there are multiple uses of bitcasted ops.
+; Hoisting the selects allows later pattern matching to see that these are min/max ops.
+
+define void @min_max_bitcast(<4 x float> %a, <4 x float> %b, <4 x i32>* %ptr1, <4 x i32>* %ptr2) {
+; CHECK-LABEL: @min_max_bitcast(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[A]], <4 x float> [[B]]
+; CHECK-NEXT: [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[B]], <4 x float> [[A]]
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32>* [[PTR1:%.*]] to <4 x float>*
+; CHECK-NEXT: store <4 x float> [[SEL1_V]], <4 x float>* [[TMP1]], align 16
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32>* [[PTR2:%.*]] to <4 x float>*
+; CHECK-NEXT: store <4 x float> [[SEL2_V]], <4 x float>* [[TMP2]], align 16
+; CHECK-NEXT: ret void
+;
+ %cmp = fcmp olt <4 x float> %a, %b
+ %bc1 = bitcast <4 x float> %a to <4 x i32>
+ %bc2 = bitcast <4 x float> %b to <4 x i32>
+ %sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2
+ %sel2 = select <4 x i1> %cmp, <4 x i32> %bc2, <4 x i32> %bc1
+ store <4 x i32> %sel1, <4 x i32>* %ptr1
+ store <4 x i32> %sel2, <4 x i32>* %ptr2
+ ret void
+}
+
+; To avoid potential backend problems, we don't do the same transform for other casts.
+
+define void @truncs_before_selects(<4 x float> %f1, <4 x float> %f2, <4 x i64> %a, <4 x i64> %b, <4 x i32>* %ptr1, <4 x i32>* %ptr2) {
+; CHECK-LABEL: @truncs_before_selects(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x float> [[F1:%.*]], [[F2:%.*]]
+; CHECK-NEXT: [[BC1:%.*]] = trunc <4 x i64> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT: [[BC2:%.*]] = trunc <4 x i64> [[B:%.*]] to <4 x i32>
+; CHECK-NEXT: [[SEL1:%.*]] = select <4 x i1> [[CMP]], <4 x i32> [[BC1]], <4 x i32> [[BC2]]
+; CHECK-NEXT: [[SEL2:%.*]] = select <4 x i1> [[CMP]], <4 x i32> [[BC2]], <4 x i32> [[BC1]]
+; CHECK-NEXT: store <4 x i32> [[SEL1]], <4 x i32>* [[PTR1:%.*]], align 16
+; CHECK-NEXT: store <4 x i32> [[SEL2]], <4 x i32>* [[PTR2:%.*]], align 16
+; CHECK-NEXT: ret void
+;
+ %cmp = fcmp olt <4 x float> %f1, %f2
+ %bc1 = trunc <4 x i64> %a to <4 x i32>
+ %bc2 = trunc <4 x i64> %b to <4 x i32>
+ %sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2
+ %sel2 = select <4 x i1> %cmp, <4 x i32> %bc2, <4 x i32> %bc1
+ store <4 x i32> %sel1, <4 x i32>* %ptr1, align 16
+ store <4 x i32> %sel2, <4 x i32>* %ptr2, align 16
+ ret void
+}
+
+; PR8575
+
+define i32 @test52(i32 %n, i32 %m) {
+; CHECK-LABEL: @test52(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], [[M:%.*]]
+; CHECK-NEXT: [[STOREMERGE:%.*]] = select i1 [[CMP]], i32 1, i32 6
+; CHECK-NEXT: ret i32 [[STOREMERGE]]
+;
+ %cmp = icmp sgt i32 %n, %m
+ %. = select i1 %cmp, i32 1, i32 3
+ %add = add nsw i32 %., 3
+ %storemerge = select i1 %cmp, i32 %., i32 %add
+ ret i32 %storemerge
+}
+
+; PR9454
+
+define i32 @test53(i32 %x) {
+; CHECK-LABEL: @test53(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], [[X]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 2, i32 1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %and = and i32 %x, 2
+ %cmp = icmp eq i32 %and, %x
+ %sel = select i1 %cmp, i32 2, i32 1
+ ret i32 %sel
+}
+
+define i32 @test54(i32 %X, i32 %Y) {
+; CHECK-LABEL: @test54(
+; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: [[C:%.*]] = zext i1 [[B]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = ashr exact i32 %X, %Y
+ %B = icmp eq i32 %A, 0
+ %C = select i1 %B, i32 %A, i32 1
+ ret i32 %C
+}
+
+define i1 @test55(i1 %X, i32 %Y, i32 %Z) {
+; CHECK-LABEL: @test55(
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[Y:%.*]], 0
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %A = ashr exact i32 %Y, %Z
+ %B = select i1 %X, i32 %Y, i32 %A
+ %C = icmp eq i32 %B, 0
+ ret i1 %C
+}
+
+define i32 @test56(i16 %x) {
+; CHECK-LABEL: @test56(
+; CHECK-NEXT: [[CONV:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: ret i32 [[CONV]]
+;
+ %tobool = icmp eq i16 %x, 0
+ %conv = zext i16 %x to i32
+ %cond = select i1 %tobool, i32 0, i32 %conv
+ ret i32 %cond
+}
+
+define i32 @test57(i32 %x, i32 %y) {
+; CHECK-LABEL: @test57(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[AND]]
+;
+ %and = and i32 %x, %y
+ %tobool = icmp eq i32 %x, 0
+ %.and = select i1 %tobool, i32 0, i32 %and
+ ret i32 %.and
+}
+
+define i32 @test58(i16 %x) {
+; CHECK-LABEL: @test58(
+; CHECK-NEXT: [[CONV:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: ret i32 [[CONV]]
+;
+ %tobool = icmp ne i16 %x, 1
+ %conv = zext i16 %x to i32
+ %cond = select i1 %tobool, i32 %conv, i32 1
+ ret i32 %cond
+}
+
+define i32 @test59(i32 %x, i32 %y) {
+; CHECK-LABEL: @test59(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[AND]]
+;
+ %and = and i32 %x, %y
+ %tobool = icmp ne i32 %x, %y
+ %.and = select i1 %tobool, i32 %and, i32 %y
+ ret i32 %.and
+}
+
+define i1 @test60(i32 %x, i1* %y) {
+; CHECK-LABEL: @test60(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT: [[LOAD:%.*]] = load i1, i1* [[Y:%.*]], align 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i1 [[LOAD]], i1 [[CMP1]]
+; CHECK-NEXT: ret i1 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 0
+ %load = load i1, i1* %y, align 1
+ %cmp1 = icmp slt i32 %x, 1
+ %sel = select i1 %cmp, i1 %load, i1 %cmp1
+ ret i1 %sel
+}
+
+ at glbl = constant i32 10
+define i32 @test61(i32* %ptr) {
+; CHECK-LABEL: @test61(
+; CHECK-NEXT: ret i32 10
+;
+ %A = load i32, i32* %ptr
+ %B = icmp eq i32* %ptr, @glbl
+ %C = select i1 %B, i32 %A, i32 10
+ ret i32 %C
+}
+
+; PR14131
+define void @test64(i32 %p, i16 %b) noreturn {
+; CHECK-LABEL: @test64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 undef, label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
+; CHECK: lor.rhs:
+; CHECK-NEXT: br label [[LOR_END]]
+; CHECK: lor.end:
+; CHECK-NEXT: br i1 true, label [[COND_END17:%.*]], label [[COND_FALSE16:%.*]]
+; CHECK: cond.false16:
+; CHECK-NEXT: br label [[COND_END17]]
+; CHECK: cond.end17:
+; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
+; CHECK: while.body:
+; CHECK-NEXT: br label [[WHILE_BODY]]
+;
+entry:
+ %p.addr.0.insert.mask = and i32 %p, -65536
+ %conv2 = and i32 %p, 65535
+ br i1 undef, label %lor.rhs, label %lor.end
+
+lor.rhs:
+ %p.addr.0.extract.trunc = trunc i32 %p.addr.0.insert.mask to i16
+ %phitmp = zext i16 %p.addr.0.extract.trunc to i32
+ br label %lor.end
+
+lor.end:
+ %t.1 = phi i32 [ 0, %entry ], [ %phitmp, %lor.rhs ]
+ %conv6 = zext i16 %b to i32
+ %div = udiv i32 %conv6, %t.1
+ %tobool8 = icmp eq i32 %div, 0
+ %cmp = icmp eq i32 %t.1, 0
+ %cmp12 = icmp ult i32 %conv2, 2
+ %cmp.sink = select i1 %tobool8, i1 %cmp12, i1 %cmp
+ br i1 %cmp.sink, label %cond.end17, label %cond.false16
+
+cond.false16:
+ br label %cond.end17
+
+cond.end17:
+ br label %while.body
+
+while.body:
+ br label %while.body
+}
+
+ at under_aligned = external global i32, align 1
+
+; The load here must not be speculated around the select. One side of the
+; select is trivially dereferenceable but may have a lower alignment than the
+; load does.
+define i32 @test76(i1 %flag, i32* %x) {
+; CHECK-LABEL: @test76(
+; CHECK-NEXT: store i32 0, i32* [[X:%.*]], align 4
+; CHECK-NEXT: [[P:%.*]] = select i1 [[FLAG:%.*]], i32* @under_aligned, i32* [[X]]
+; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ store i32 0, i32* %x
+ %p = select i1 %flag, i32* @under_aligned, i32* %x
+ %v = load i32, i32* %p
+ ret i32 %v
+}
+
+declare void @scribble_on_i32(i32*)
+
+; The load here must not be speculated around the select. One side of the
+; select is trivially dereferenceable but may have a lower alignment than the
+; load does.
+
+define i32 @test77(i1 %flag, i32* %x) {
+; CHECK-LABEL: @test77(
+; CHECK-NEXT: [[UNDER_ALIGNED:%.*]] = alloca i32, align 1
+; CHECK-NEXT: call void @scribble_on_i32(i32* nonnull [[UNDER_ALIGNED]])
+; CHECK-NEXT: store i32 0, i32* [[X:%.*]], align 4
+; CHECK-NEXT: [[P:%.*]] = select i1 [[FLAG:%.*]], i32* [[UNDER_ALIGNED]], i32* [[X]]
+; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %under_aligned = alloca i32, align 1
+ call void @scribble_on_i32(i32* %under_aligned)
+ store i32 0, i32* %x
+ %p = select i1 %flag, i32* %under_aligned, i32* %x
+ %v = load i32, i32* %p
+ ret i32 %v
+}
+
+define i32 @test78(i1 %flag, i32* %x, i32* %y, i32* %z) {
+; Test that we can speculate the loads around the select even when we can't
+; fold the load completely away.
+; CHECK-LABEL: @test78(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: store i32 0, i32* [[X:%.*]], align 4
+; CHECK-NEXT: store i32 0, i32* [[Y:%.*]], align 4
+; CHECK-NEXT: store i32 42, i32* [[Z:%.*]], align 4
+; CHECK-NEXT: [[X_VAL:%.*]] = load i32, i32* [[X]], align 4
+; CHECK-NEXT: [[Y_VAL:%.*]] = load i32, i32* [[Y]], align 4
+; CHECK-NEXT: [[V:%.*]] = select i1 [[FLAG:%.*]], i32 [[X_VAL]], i32 [[Y_VAL]]
+; CHECK-NEXT: ret i32 [[V]]
+;
+entry:
+ store i32 0, i32* %x
+ store i32 0, i32* %y
+ ; Block forwarding by storing to %z which could alias either %x or %y.
+ store i32 42, i32* %z
+ %p = select i1 %flag, i32* %x, i32* %y
+ %v = load i32, i32* %p
+ ret i32 %v
+}
+
+; Test that we can speculate the loads around the select even when we can't
+; fold the load completely away.
+define i32 @test78_deref(i1 %flag, i32* dereferenceable(4) %x, i32* dereferenceable(4) %y, i32* %z) {
+; CHECK-LABEL: @test78_deref(
+; CHECK-NEXT: [[X_VAL:%.*]] = load i32, i32* [[X:%.*]], align 4
+; CHECK-NEXT: [[Y_VAL:%.*]] = load i32, i32* [[Y:%.*]], align 4
+; CHECK-NEXT: [[V:%.*]] = select i1 [[FLAG:%.*]], i32 [[X_VAL]], i32 [[Y_VAL]]
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %p = select i1 %flag, i32* %x, i32* %y
+ %v = load i32, i32* %p
+ ret i32 %v
+}
+
+; The same as @test78 but we can't speculate the load because it can trap
+; if under-aligned.
+define i32 @test78_neg(i1 %flag, i32* %x, i32* %y, i32* %z) {
+; CHECK-LABEL: @test78_neg(
+; CHECK-NEXT: store i32 0, i32* [[X:%.*]], align 4
+; CHECK-NEXT: store i32 0, i32* [[Y:%.*]], align 4
+; CHECK-NEXT: store i32 42, i32* [[Z:%.*]], align 4
+; CHECK-NEXT: [[P:%.*]] = select i1 [[FLAG:%.*]], i32* [[X]], i32* [[Y]]
+; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 16
+; CHECK-NEXT: ret i32 [[V]]
+;
+ store i32 0, i32* %x
+ store i32 0, i32* %y
+ ; Block forwarding by storing to %z which could alias either %x or %y.
+ store i32 42, i32* %z
+ %p = select i1 %flag, i32* %x, i32* %y
+ %v = load i32, i32* %p, align 16
+ ret i32 %v
+}
+
+; The same as @test78_deref but we can't speculate the load because
+; one of the arguments is not sufficiently dereferenceable.
+define i32 @test78_deref_neg(i1 %flag, i32* dereferenceable(2) %x, i32* dereferenceable(4) %y, i32* %z) {
+; CHECK-LABEL: @test78_deref_neg(
+; CHECK-NEXT: [[P:%.*]] = select i1 [[FLAG:%.*]], i32* [[X:%.*]], i32* [[Y:%.*]]
+; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 4
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %p = select i1 %flag, i32* %x, i32* %y
+ %v = load i32, i32* %p
+ ret i32 %v
+}
+
+; Test that we can speculate the loads around the select even when we can't
+; fold the load completely away.
+define float @test79(i1 %flag, float* %x, i32* %y, i32* %z) {
+; CHECK-LABEL: @test79(
+; CHECK-NEXT: [[X1:%.*]] = bitcast float* [[X:%.*]] to i32*
+; CHECK-NEXT: [[Y1:%.*]] = bitcast i32* [[Y:%.*]] to float*
+; CHECK-NEXT: store i32 0, i32* [[X1]], align 4
+; CHECK-NEXT: store i32 0, i32* [[Y]], align 4
+; CHECK-NEXT: store i32 42, i32* [[Z:%.*]], align 4
+; CHECK-NEXT: [[X_VAL:%.*]] = load float, float* [[X]], align 4
+; CHECK-NEXT: [[Y1_VAL:%.*]] = load float, float* [[Y1]], align 4
+; CHECK-NEXT: [[V:%.*]] = select i1 [[FLAG:%.*]], float [[X_VAL]], float [[Y1_VAL]]
+; CHECK-NEXT: ret float [[V]]
+;
+ %x1 = bitcast float* %x to i32*
+ %y1 = bitcast i32* %y to float*
+ store i32 0, i32* %x1
+ store i32 0, i32* %y
+ ; Block forwarding by storing to %z which could alias either %x or %y.
+ store i32 42, i32* %z
+ %p = select i1 %flag, float* %x, float* %y1
+ %v = load float, float* %p
+ ret float %v
+}
+
+; Test that when we speculate the loads around the select they fold throug
+; load->load folding and load->store folding.
+define i32 @test80(i1 %flag) {
+; CHECK-LABEL: @test80(
+; CHECK-NEXT: [[X:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[Y:%.*]] = alloca i32, align 4
+; CHECK-NEXT: call void @scribble_on_i32(i32* nonnull [[X]])
+; CHECK-NEXT: call void @scribble_on_i32(i32* nonnull [[Y]])
+; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[X]], align 4
+; CHECK-NEXT: store i32 [[TMP]], i32* [[Y]], align 4
+; CHECK-NEXT: ret i32 [[TMP]]
+;
+ %x = alloca i32
+ %y = alloca i32
+ call void @scribble_on_i32(i32* %x)
+ call void @scribble_on_i32(i32* %y)
+ %tmp = load i32, i32* %x
+ store i32 %tmp, i32* %y
+ %p = select i1 %flag, i32* %x, i32* %y
+ %v = load i32, i32* %p
+ ret i32 %v
+}
+
+; Test that we can speculate the load around the select even though they use
+; differently typed pointers.
+define float @test81(i1 %flag) {
+; CHECK-LABEL: @test81(
+; CHECK-NEXT: [[X:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[Y:%.*]] = alloca i32, align 4
+; CHECK-NEXT: call void @scribble_on_i32(i32* nonnull [[X]])
+; CHECK-NEXT: call void @scribble_on_i32(i32* nonnull [[Y]])
+; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[X]], align 4
+; CHECK-NEXT: store i32 [[TMP]], i32* [[Y]], align 4
+; CHECK-NEXT: [[V:%.*]] = bitcast i32 [[TMP]] to float
+; CHECK-NEXT: ret float [[V]]
+;
+ %x = alloca float
+ %y = alloca i32
+ %x1 = bitcast float* %x to i32*
+ %y1 = bitcast i32* %y to float*
+ call void @scribble_on_i32(i32* %x1)
+ call void @scribble_on_i32(i32* %y)
+ %tmp = load i32, i32* %x1
+ store i32 %tmp, i32* %y
+ %p = select i1 %flag, float* %x, float* %y1
+ %v = load float, float* %p
+ ret float %v
+}
+
+; Test that we can speculate the load around the select even though they use
+; differently typed pointers.
+define i32 @test82(i1 %flag) {
+; CHECK-LABEL: @test82(
+; CHECK-NEXT: [[X:%.*]] = alloca float, align 4
+; CHECK-NEXT: [[Y:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[X1:%.*]] = bitcast float* [[X]] to i32*
+; CHECK-NEXT: [[Y1:%.*]] = bitcast i32* [[Y]] to float*
+; CHECK-NEXT: call void @scribble_on_i32(i32* nonnull [[X1]])
+; CHECK-NEXT: call void @scribble_on_i32(i32* nonnull [[Y]])
+; CHECK-NEXT: [[TMP:%.*]] = load float, float* [[X]], align 4
+; CHECK-NEXT: store float [[TMP]], float* [[Y1]], align 4
+; CHECK-NEXT: [[V:%.*]] = bitcast float [[TMP]] to i32
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %x = alloca float
+ %y = alloca i32
+ %x1 = bitcast float* %x to i32*
+ %y1 = bitcast i32* %y to float*
+ call void @scribble_on_i32(i32* %x1)
+ call void @scribble_on_i32(i32* %y)
+ %tmp = load float, float* %x
+ store float %tmp, float* %y1
+ %p = select i1 %flag, i32* %x1, i32* %y
+ %v = load i32, i32* %p
+ ret i32 %v
+}
+
+declare void @scribble_on_i64(i64*)
+declare void @scribble_on_i128(i128*)
+
+; Test that we can speculate the load around the select even though they use
+; differently typed pointers and requires inttoptr casts.
+define i8* @test83(i1 %flag) {
+; CHECK-LABEL: @test83(
+; CHECK-NEXT: [[X:%.*]] = alloca i8*, align 8
+; CHECK-NEXT: [[Y:%.*]] = alloca i8*, align 8
+; CHECK-NEXT: [[TMPCAST:%.*]] = bitcast i8** [[Y]] to i64*
+; CHECK-NEXT: [[X1:%.*]] = bitcast i8** [[X]] to i64*
+; CHECK-NEXT: call void @scribble_on_i64(i64* nonnull [[X1]])
+; CHECK-NEXT: call void @scribble_on_i64(i64* nonnull [[TMPCAST]])
+; CHECK-NEXT: [[TMP:%.*]] = load i64, i64* [[X1]], align 8
+; CHECK-NEXT: store i64 [[TMP]], i64* [[TMPCAST]], align 8
+; CHECK-NEXT: [[V:%.*]] = inttoptr i64 [[TMP]] to i8*
+; CHECK-NEXT: ret i8* [[V]]
+;
+ %x = alloca i8*
+ %y = alloca i64
+ %x1 = bitcast i8** %x to i64*
+ %y1 = bitcast i64* %y to i8**
+ call void @scribble_on_i64(i64* %x1)
+ call void @scribble_on_i64(i64* %y)
+ %tmp = load i64, i64* %x1
+ store i64 %tmp, i64* %y
+ %p = select i1 %flag, i8** %x, i8** %y1
+ %v = load i8*, i8** %p
+ ret i8* %v
+}
+
+; Test that we can speculate the load around the select even though they use
+; differently typed pointers and requires a ptrtoint cast.
+define i64 @test84(i1 %flag) {
+; CHECK-LABEL: @test84(
+; CHECK-NEXT: [[X:%.*]] = alloca i8*, align 8
+; CHECK-NEXT: [[Y:%.*]] = alloca i8*, align 8
+; CHECK-NEXT: [[TMPCAST:%.*]] = bitcast i8** [[Y]] to i64*
+; CHECK-NEXT: [[X1:%.*]] = bitcast i8** [[X]] to i64*
+; CHECK-NEXT: call void @scribble_on_i64(i64* nonnull [[X1]])
+; CHECK-NEXT: call void @scribble_on_i64(i64* nonnull [[TMPCAST]])
+; CHECK-NEXT: [[TMP:%.*]] = load i8*, i8** [[X]], align 8
+; CHECK-NEXT: store i8* [[TMP]], i8** [[Y]], align 8
+; CHECK-NEXT: [[V:%.*]] = ptrtoint i8* [[TMP]] to i64
+; CHECK-NEXT: ret i64 [[V]]
+;
+ %x = alloca i8*
+ %y = alloca i64
+ %x1 = bitcast i8** %x to i64*
+ %y1 = bitcast i64* %y to i8**
+ call void @scribble_on_i64(i64* %x1)
+ call void @scribble_on_i64(i64* %y)
+ %tmp = load i8*, i8** %x
+ store i8* %tmp, i8** %y1
+ %p = select i1 %flag, i64* %x1, i64* %y
+ %v = load i64, i64* %p
+ ret i64 %v
+}
+
+; Test that we can't speculate the load around the select. The load of the
+; pointer doesn't load all of the stored integer bits. We could fix this, but it
+; would require endianness checks and other nastiness.
+define i8* @test85(i1 %flag) {
+; CHECK-LABEL: @test85(
+; CHECK-NEXT: [[X1:%.*]] = alloca [2 x i8*], align 8
+; CHECK-NEXT: [[Y:%.*]] = alloca i128, align 8
+; CHECK-NEXT: [[X1_SUB:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[X1]], i64 0, i64 0
+; CHECK-NEXT: [[X2:%.*]] = bitcast [2 x i8*]* [[X1]] to i128*
+; CHECK-NEXT: [[Y1:%.*]] = bitcast i128* [[Y]] to i8**
+; CHECK-NEXT: call void @scribble_on_i128(i128* nonnull [[X2]])
+; CHECK-NEXT: call void @scribble_on_i128(i128* nonnull [[Y]])
+; CHECK-NEXT: [[TMP:%.*]] = load i128, i128* [[X2]], align 8
+; CHECK-NEXT: store i128 [[TMP]], i128* [[Y]], align 8
+; CHECK-NEXT: [[X1_SUB_VAL:%.*]] = load i8*, i8** [[X1_SUB]], align 8
+; CHECK-NEXT: [[Y1_VAL:%.*]] = load i8*, i8** [[Y1]], align 8
+; CHECK-NEXT: [[V:%.*]] = select i1 [[FLAG:%.*]], i8* [[X1_SUB_VAL]], i8* [[Y1_VAL]]
+; CHECK-NEXT: ret i8* [[V]]
+;
+ %x = alloca [2 x i8*]
+ %y = alloca i128
+ %x1 = bitcast [2 x i8*]* %x to i8**
+ %x2 = bitcast i8** %x1 to i128*
+ %y1 = bitcast i128* %y to i8**
+ call void @scribble_on_i128(i128* %x2)
+ call void @scribble_on_i128(i128* %y)
+ %tmp = load i128, i128* %x2
+ store i128 %tmp, i128* %y
+ %p = select i1 %flag, i8** %x1, i8** %y1
+ %v = load i8*, i8** %p
+ ret i8* %v
+}
+
+; Test that we can't speculate the load around the select when the integer size
+; is larger than the pointer size. The store of the pointer doesn't store to all
+; the bits of the integer.
+define i128 @test86(i1 %flag) {
+; CHECK-LABEL: @test86(
+; CHECK-NEXT: [[X1:%.*]] = alloca [2 x i8*], align 8
+; CHECK-NEXT: [[Y:%.*]] = alloca i128, align 8
+; CHECK-NEXT: [[X1_SUB:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[X1]], i64 0, i64 0
+; CHECK-NEXT: [[X2:%.*]] = bitcast [2 x i8*]* [[X1]] to i128*
+; CHECK-NEXT: [[Y1:%.*]] = bitcast i128* [[Y]] to i8**
+; CHECK-NEXT: call void @scribble_on_i128(i128* nonnull [[X2]])
+; CHECK-NEXT: call void @scribble_on_i128(i128* nonnull [[Y]])
+; CHECK-NEXT: [[TMP:%.*]] = load i8*, i8** [[X1_SUB]], align 8
+; CHECK-NEXT: store i8* [[TMP]], i8** [[Y1]], align 8
+; CHECK-NEXT: [[X2_VAL:%.*]] = load i128, i128* [[X2]], align 8
+; CHECK-NEXT: [[Y_VAL:%.*]] = load i128, i128* [[Y]], align 8
+; CHECK-NEXT: [[V:%.*]] = select i1 [[FLAG:%.*]], i128 [[X2_VAL]], i128 [[Y_VAL]]
+; CHECK-NEXT: ret i128 [[V]]
+;
+ %x = alloca [2 x i8*]
+ %y = alloca i128
+ %x1 = bitcast [2 x i8*]* %x to i8**
+ %x2 = bitcast i8** %x1 to i128*
+ %y1 = bitcast i128* %y to i8**
+ call void @scribble_on_i128(i128* %x2)
+ call void @scribble_on_i128(i128* %y)
+ %tmp = load i8*, i8** %x1
+ store i8* %tmp, i8** %y1
+ %p = select i1 %flag, i128* %x2, i128* %y
+ %v = load i128, i128* %p
+ ret i128 %v
+}
+
+define i32 @test_select_select0(i32 %a, i32 %r0, i32 %r1, i32 %v1, i32 %v2) {
+; CHECK-LABEL: @test_select_select0(
+; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[A:%.*]], [[V1:%.*]]
+; CHECK-NEXT: [[S0:%.*]] = select i1 [[C0]], i32 [[R1:%.*]], i32 [[R0:%.*]]
+; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[A]], [[V2:%.*]]
+; CHECK-NEXT: [[S1:%.*]] = select i1 [[C1]], i32 [[S0]], i32 [[R1]]
+; CHECK-NEXT: ret i32 [[S1]]
+;
+ %c0 = icmp sge i32 %a, %v1
+ %s0 = select i1 %c0, i32 %r0, i32 %r1
+ %c1 = icmp slt i32 %a, %v2
+ %s1 = select i1 %c1, i32 %s0, i32 %r1
+ ret i32 %s1
+}
+
+define i32 @test_select_select1(i32 %a, i32 %r0, i32 %r1, i32 %v1, i32 %v2) {
+; CHECK-LABEL: @test_select_select1(
+; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[A:%.*]], [[V1:%.*]]
+; CHECK-NEXT: [[S0:%.*]] = select i1 [[C0]], i32 [[R1:%.*]], i32 [[R0:%.*]]
+; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[A]], [[V2:%.*]]
+; CHECK-NEXT: [[S1:%.*]] = select i1 [[C1]], i32 [[R0]], i32 [[S0]]
+; CHECK-NEXT: ret i32 [[S1]]
+;
+ %c0 = icmp sge i32 %a, %v1
+ %s0 = select i1 %c0, i32 %r0, i32 %r1
+ %c1 = icmp slt i32 %a, %v2
+ %s1 = select i1 %c1, i32 %r0, i32 %s0
+ ret i32 %s1
+}
+
+define i32 @PR23757(i32 %x) {
+; CHECK-LABEL: @PR23757(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp eq i32 %x, 2147483647
+ %add = add nsw i32 %x, 1
+ %sel = select i1 %cmp, i32 -2147483648, i32 %add
+ ret i32 %sel
+}
+
+; max(max(~a, -1), -1) --> ~min(a, 0)
+
+define i32 @PR27137(i32 %a) {
+; CHECK-LABEL: @PR27137(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 0
+; CHECK-NEXT: [[S1:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[S1]]
+;
+ %not_a = xor i32 %a, -1
+ %c0 = icmp slt i32 %a, 0
+ %s0 = select i1 %c0, i32 %not_a, i32 -1
+ %c1 = icmp sgt i32 %s0, -1
+ %s1 = select i1 %c1, i32 %s0, i32 -1
+ ret i32 %s1
+}
+
+define i32 @select_icmp_slt0_xor(i32 %x) {
+; CHECK-LABEL: @select_icmp_slt0_xor(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %cmp = icmp slt i32 %x, zeroinitializer
+ %xor = xor i32 %x, 2147483648
+ %x.xor = select i1 %cmp, i32 %x, i32 %xor
+ ret i32 %x.xor
+}
+
+define <2 x i32> @select_icmp_slt0_xor_vec(<2 x i32> %x) {
+; CHECK-LABEL: @select_icmp_slt0_xor_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[X:%.*]], <i32 -2147483648, i32 -2147483648>
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %cmp = icmp slt <2 x i32> %x, zeroinitializer
+ %xor = xor <2 x i32> %x, <i32 2147483648, i32 2147483648>
+ %x.xor = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %xor
+ ret <2 x i32> %x.xor
+}
+
+define <4 x i32> @canonicalize_to_shuffle(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @canonicalize_to_shuffle(
+; CHECK-NEXT: [[SEL:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[SEL]]
+;
+ %sel = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %sel
+}
+
+; Undef elements of the select condition may not be translated into undef elements of a shuffle mask
+; because undef in a shuffle mask means we can return anything, not just one of the selected values.
+; https://bugs.llvm.org/show_bug.cgi?id=32486
+
+define <4 x i32> @undef_elts_in_condition(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @undef_elts_in_condition(
+; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> <i1 true, i1 undef, i1 false, i1 undef>, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[SEL]]
+;
+ %sel = select <4 x i1> <i1 true, i1 undef, i1 false, i1 undef>, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %sel
+}
+
+; Don't die or try if the condition mask is a constant expression or contains a constant expression.
+
+ at g = global i32 0
+
+define <4 x i32> @cannot_canonicalize_to_shuffle1(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @cannot_canonicalize_to_shuffle1(
+; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> bitcast (i4 ptrtoint (i32* @g to i4) to <4 x i1>), <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[SEL]]
+;
+ %sel = select <4 x i1> bitcast (i4 ptrtoint (i32* @g to i4) to <4 x i1>), <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %sel
+}
+
+define <4 x i32> @cannot_canonicalize_to_shuffle2(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @cannot_canonicalize_to_shuffle2(
+; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> <i1 true, i1 undef, i1 false, i1 icmp sle (i16 ptrtoint (i32* @g to i16), i16 4)>, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[SEL]]
+;
+ %sel = select <4 x i1> <i1 true, i1 undef, i1 false, i1 icmp sle (i16 ptrtoint (i32* @g to i16), i16 4)>, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %sel
+}
+
+declare void @llvm.assume(i1)
+
+define i8 @assume_cond_true(i1 %cond, i8 %x, i8 %y) {
+; CHECK-LABEL: @assume_cond_true(
+; CHECK-NEXT: call void @llvm.assume(i1 [[COND:%.*]])
+; CHECK-NEXT: ret i8 [[X:%.*]]
+;
+ call void @llvm.assume(i1 %cond)
+ %sel = select i1 %cond, i8 %x, i8 %y
+ ret i8 %sel
+}
+
+; computeKnownBitsFromAssume() understands the 'not' of an assumed condition.
+
+define i8 @assume_cond_false(i1 %cond, i8 %x, i8 %y) {
+; CHECK-LABEL: @assume_cond_false(
+; CHECK-NEXT: [[NOTCOND:%.*]] = xor i1 [[COND:%.*]], true
+; CHECK-NEXT: call void @llvm.assume(i1 [[NOTCOND]])
+; CHECK-NEXT: ret i8 [[Y:%.*]]
+;
+ %notcond = xor i1 %cond, true
+ call void @llvm.assume(i1 %notcond)
+ %sel = select i1 %cond, i8 %x, i8 %y
+ ret i8 %sel
+}
+
+; Test case to make sure we don't consider an all ones float values for converting the select into a sext.
+define <4 x float> @PR33721(<4 x float> %w) {
+; CHECK-LABEL: @PR33721(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = fcmp ole <4 x float> [[W:%.*]], zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[TMP0]], <4 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <4 x float> zeroinitializer
+; CHECK-NEXT: ret <4 x float> [[TMP1]]
+;
+entry:
+ %0 = fcmp ole <4 x float> %w, zeroinitializer
+ %1 = select <4 x i1> %0, <4 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <4 x float> zeroinitializer
+ ret <4 x float> %1
+}
+
+; select(C, binop(select(C, X, Y), W), Z) -> select(C, binop(X, W), Z)
+define i8 @test87(i1 %cond, i8 %w, i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: @test87(
+; CHECK-NEXT: [[B:%.*]] = add i8 [[X:%.*]], [[W:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], i8 [[B]], i8 [[Z:%.*]]
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = select i1 %cond, i8 %x, i8 %y
+ %b = add i8 %a, %w
+ %c = select i1 %cond, i8 %b, i8 %z
+ ret i8 %c
+}
+
+; select(C, binop(select(C, X, Y), W), Z) -> select(C, Z, binop(Y, W))
+define i8 @test88(i1 %cond, i8 %w, i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: @test88(
+; CHECK-NEXT: [[B:%.*]] = sub i8 [[Y:%.*]], [[W:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], i8 [[Z:%.*]], i8 [[B]]
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = select i1 %cond, i8 %x, i8 %y
+ %b = sub i8 %a, %w
+ %c = select i1 %cond, i8 %z, i8 %b
+ ret i8 %c
+}
+
+; select(C, Z, binop(W, select(C, X, Y))) -> select(C, binop(X, W), Z)
+define i8 @test89(i1 %cond, i8 %w, i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: @test89(
+; CHECK-NEXT: [[B:%.*]] = and i8 [[X:%.*]], [[W:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], i8 [[B]], i8 [[Z:%.*]]
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = select i1 %cond, i8 %x, i8 %y
+ %b = and i8 %w, %a
+ %c = select i1 %cond, i8 %b, i8 %z
+ ret i8 %c
+}
+
+; select(C, Z, binop(W, select(C, X, Y))) -> select(C, Z, binop(W, Y))
+define i8 @test90(i1 %cond, i8 %w, i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: @test90(
+; CHECK-NEXT: [[B:%.*]] = or i8 [[Y:%.*]], [[W:%.*]]
+; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], i8 [[Z:%.*]], i8 [[B]]
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = select i1 %cond, i8 %x, i8 %y
+ %b = or i8 %w, %a
+ %c = select i1 %cond, i8 %z, i8 %b
+ ret i8 %c
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/select_arithmetic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select_arithmetic.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select_arithmetic.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select_arithmetic.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+; Tests folding constants from two similar selects that feed a add
+
+define float @test1a(i1 zeroext %arg) #0 {
+; CHECK-LABEL: @test1a(
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[ARG:%.*]], float 6.000000e+00, float 1.500000e+01
+; CHECK-NEXT: ret float [[TMP2]]
+;
+ %tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
+ %tmp1 = select i1 %arg, float 1.000000e+00, float 9.000000e+00
+ %tmp2 = fadd float %tmp, %tmp1
+ ret float %tmp2
+}
+
+; Tests folding multiple expression constants from similar selects that feed a adds
+
+define float @test1b(i1 zeroext %arg) #0 {
+; CHECK-LABEL: @test1b(
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[ARG:%.*]], float 7.250000e+00, float 2.800000e+01
+; CHECK-NEXT: ret float [[TMP5]]
+;
+ %tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
+ %tmp1 = select i1 %arg, float 1.000000e+00, float 9.000000e+00
+ %tmp2 = select i1 %arg, float 2.500000e-01, float 4.000000e+00
+ %tmp3 = fadd float %tmp, %tmp1
+ %tmp4 = fadd float %tmp2, %tmp1
+ %tmp5 = fadd float %tmp4, %tmp3
+ ret float %tmp5
+}
+
+; Tests folding constants from two similar selects that feed a sub
+
+define float @test2(i1 zeroext %arg) #0 {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[ARG:%.*]], float 4.000000e+00, float -3.000000e+00
+; CHECK-NEXT: ret float [[TMP2]]
+;
+ %tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
+ %tmp1 = select i1 %arg, float 1.000000e+00, float 9.000000e+00
+ %tmp2 = fsub float %tmp, %tmp1
+ ret float %tmp2
+}
+
+; Tests folding constants from two similar selects that feed a mul
+
+define float @test3(i1 zeroext %arg) #0 {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[ARG:%.*]], float 5.000000e+00, float 5.400000e+01
+; CHECK-NEXT: ret float [[TMP2]]
+;
+ %tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
+ %tmp1 = select i1 %arg, float 1.000000e+00, float 9.000000e+00
+ %tmp2 = fmul float %tmp, %tmp1
+ ret float %tmp2
+}
+
+declare void @use_float(float)
+
+; Tests folding constants if the selects have multiple uses but
+; we can fold away the binary op with a select.
+
+define float @test4(i1 zeroext %arg) #0 {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[TMP:%.*]] = select i1 [[ARG:%.*]], float 5.000000e+00, float 6.000000e+00
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[ARG]], float 5.000000e+00, float 5.400000e+01
+; CHECK-NEXT: call void @use_float(float [[TMP]])
+; CHECK-NEXT: ret float [[TMP2]]
+;
+ %tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00
+ %tmp1 = select i1 %arg, float 1.000000e+00, float 9.000000e+00
+ %tmp2 = fmul float %tmp, %tmp1
+ call void @use_float(float %tmp)
+ ret float %tmp2
+}
+
+; Tests not folding constants if we cannot fold away any of the selects.
+
+define float @test5(i1 zeroext %arg, float %div) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[TMP:%.*]] = select i1 [[ARG:%.*]], float [[DIV:%.*]], float 5.000000e+00
+; CHECK-NEXT: [[MUL:%.*]] = fmul contract float [[TMP]], [[TMP]]
+; CHECK-NEXT: call void @use_float(float [[TMP]])
+; CHECK-NEXT: ret float [[MUL]]
+;
+ %tmp = select i1 %arg, float %div, float 5.000000e+00
+ %mul = fmul contract float %tmp, %tmp
+ call void @use_float(float %tmp)
+ ret float %mul
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/select_meta.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select_meta.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select_meta.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select_meta.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,345 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; and enhanced to include metadata checking.
+
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @foo(i32) local_unnamed_addr #0 {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 %0, 2
+; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[TMP2]], i32 20, i32 -20, !prof ![[$MD1:[0-9]+]]
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[DOTV]], %0
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %2 = icmp sgt i32 %0, 2
+ %3 = add nsw i32 %0, 20
+ %4 = add i32 %0, -20
+ select i1 %2, i32 %3, i32 %4, !prof !1
+ ret i32 %5
+}
+
+define i8 @shrink_select(i1 %cond, i32 %x) {
+; CHECK-LABEL: @shrink_select(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %x to i8
+; CHECK-NEXT: [[TRUNC:%.*]] = select i1 %cond, i8 [[TMP1]], i8 42, !prof ![[$MD1]]
+; CHECK-NEXT: ret i8 [[TRUNC]]
+;
+ %sel = select i1 %cond, i32 %x, i32 42, !prof !1
+ %trunc = trunc i32 %sel to i8
+ ret i8 %trunc
+}
+
+define void @min_max_bitcast(<4 x float> %a, <4 x float> %b, <4 x i32>* %ptr1, <4 x i32>* %ptr2) {
+; CHECK-LABEL: @min_max_bitcast(
+; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x float> %a, %b
+; CHECK-NEXT: [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> %a, <4 x float> %b, !prof ![[$MD1]]
+; CHECK-NEXT: [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> %b, <4 x float> %a, !prof ![[$MD1]]
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32>* %ptr1 to <4 x float>*
+; CHECK-NEXT: store <4 x float> [[SEL1_V]], <4 x float>* [[TMP1]], align 16
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32>* %ptr2 to <4 x float>*
+; CHECK-NEXT: store <4 x float> [[SEL2_V]], <4 x float>* [[TMP2]], align 16
+; CHECK-NEXT: ret void
+;
+ %cmp = fcmp olt <4 x float> %a, %b
+ %bc1 = bitcast <4 x float> %a to <4 x i32>
+ %bc2 = bitcast <4 x float> %b to <4 x i32>
+ %sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2, !prof !1
+ %sel2 = select <4 x i1> %cmp, <4 x i32> %bc2, <4 x i32> %bc1, !prof !1
+ store <4 x i32> %sel1, <4 x i32>* %ptr1
+ store <4 x i32> %sel2, <4 x i32>* %ptr2
+ ret void
+}
+
+define i32 @foo2(i32, i32) local_unnamed_addr #0 {
+; CHECK-LABEL: @foo2(
+; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 %0, 2
+; CHECK-NEXT: [[TMP4:%.*]] = sub i32 0, %1
+; CHECK-NEXT: [[DOTP:%.*]] = select i1 [[TMP3]], i32 %1, i32 [[TMP4]], !prof ![[$MD1]]
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[DOTP]], %0
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %3 = icmp sgt i32 %0, 2
+ %4 = add nsw i32 %0, %1
+ %5 = sub nsw i32 %0, %1
+ select i1 %3, i32 %4, i32 %5, !prof !1
+ ret i32 %6
+}
+
+define i64 @test43(i32 %a) nounwind {
+; CHECK-LABEL: @test43(
+; CHECK-NEXT: [[A_EXT:%.*]] = sext i32 %a to i64
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A_EXT]], 0
+; CHECK-NEXT: [[MAX:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 0, !prof ![[$MD1]]
+; CHECK-NEXT: ret i64 [[MAX]]
+;
+ %a_ext = sext i32 %a to i64
+ %is_a_nonnegative = icmp sgt i32 %a, -1
+ %max = select i1 %is_a_nonnegative, i64 %a_ext, i64 0, !prof !1
+ ret i64 %max
+}
+
+define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {
+; CHECK-LABEL: @scalar_select_of_vectors_sext(
+; CHECK-NEXT: [[NARROW:%.*]] = select i1 %ccb, <2 x i1> %cca, <2 x i1> zeroinitializer, !prof ![[$MD1]]
+; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %ccax = sext <2 x i1> %cca to <2 x i32>
+ %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>, !prof !1
+ ret <2 x i32> %r
+}
+
+
+define i16 @t7(i32 %a) {
+; CHECK-LABEL: @t7(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 %a, -32768
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 -32768, !prof ![[$MD1]]
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[TMP3]]
+;
+ %1 = icmp slt i32 %a, -32768
+ %2 = trunc i32 %a to i16
+ %3 = select i1 %1, i16 %2, i16 -32768, !prof !1
+ ret i16 %3
+}
+
+define i32 @abs_nabs_x01(i32 %x) {
+; CHECK-LABEL: @abs_nabs_x01(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 %x, 0
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, %x
+; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 %x, !prof ![[$MD3:[0-9]+]]
+; CHECK-NEXT: ret i32 [[COND1]]
+;
+ %cmp = icmp sgt i32 %x, -1
+ %sub = sub nsw i32 0, %x
+ %cond = select i1 %cmp, i32 %sub, i32 %x, !prof !1
+ %cmp1 = icmp sgt i32 %cond, -1
+ %sub16 = sub nsw i32 0, %cond
+ %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16, !prof !2
+ ret i32 %cond18
+}
+
+; Swap predicate / metadata order
+
+define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
+; CHECK-LABEL: @abs_nabs_x01_vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> %x, zeroinitializer
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, %x
+; CHECK-NEXT: [[COND1:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> %x, !prof ![[$MD3]]
+; CHECK-NEXT: ret <2 x i32> [[COND1]]
+;
+ %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
+ %sub = sub nsw <2 x i32> zeroinitializer, %x
+ %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x, !prof !1
+ %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
+ %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
+ %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16, !prof !2
+ ret <2 x i32> %cond18
+}
+
+; SMAX(SMAX(x, y), x) -> SMAX(x, y)
+define i32 @test30(i32 %x, i32 %y) {
+; CHECK-LABEL: @test30(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 %x, %y
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 %x, i32 %y, !prof ![[$MD1]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp sgt i32 %x, %y
+ %cond = select i1 %cmp, i32 %x, i32 %y, !prof !1
+ %cmp5 = icmp sgt i32 %cond, %x
+ %retval = select i1 %cmp5, i32 %cond, i32 %x, !prof !2
+ ret i32 %retval
+}
+
+; SMAX(SMAX(75, X), 36) -> SMAX(X, 75)
+define i32 @test70(i32 %x) {
+; CHECK-LABEL: @test70(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 %x, 75
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[$MD3]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %cmp = icmp slt i32 %x, 75
+ %cond = select i1 %cmp, i32 75, i32 %x, !prof !1
+ %cmp3 = icmp slt i32 %cond, 36
+ %retval = select i1 %cmp3, i32 36, i32 %cond, !prof !2
+ ret i32 %retval
+}
+
+; Swap predicate / metadata order
+; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
+define i32 @test72(i32 %x) {
+; CHECK-LABEL: @test72(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 %x, 11
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[TMP1]], i32 %x, i32 11, !prof ![[$MD4:[0-9]+]]
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
+ %cmp = icmp sgt i32 %x, 92
+ %cond = select i1 %cmp, i32 92, i32 %x, !prof !1
+ %cmp3 = icmp sgt i32 %cond, 11
+ %retval = select i1 %cmp3, i32 11, i32 %cond, !prof !2
+ ret i32 %retval
+}
+
+; Swap predicate / metadata order
+; SMAX(SMAX(X, 36), 75) -> SMAX(X, 75)
+define i32 @test74(i32 %x) {
+; CHECK-LABEL: @test74(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 %x, 75
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[$MD4]]
+; CHECK-NEXT: ret i32 [[RETVAL]]
+;
+ %cmp = icmp slt i32 %x, 36
+ %cond = select i1 %cmp, i32 36, i32 %x, !prof !1
+ %cmp3 = icmp slt i32 %cond, 75
+ %retval = select i1 %cmp3, i32 75, i32 %cond, !prof !2
+ ret i32 %retval
+}
+
+; The xor is moved after the select. The metadata remains the same because the select operands are not swapped only inverted.
+define i32 @smin1(i32 %x) {
+; CHECK-LABEL: @smin1(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0, !prof ![[$MD1]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %not_x = xor i32 %x, -1
+ %cmp = icmp sgt i32 %x, 0
+ %sel = select i1 %cmp, i32 %not_x, i32 -1, !prof !1
+ ret i32 %sel
+}
+
+; The compare should change, and the metadata is swapped because the select operands are swapped and inverted.
+define i32 @smin2(i32 %x) {
+; CHECK-LABEL: @smin2(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0, !prof ![[$MD3]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %not_x = xor i32 %x, -1
+ %cmp = icmp slt i32 %x, 0
+ %sel = select i1 %cmp, i32 -1, i32 %not_x, !prof !1
+ ret i32 %sel
+}
+
+; The xor is moved after the select. The metadata remains the same because the select operands are not swapped only inverted.
+define i32 @smax1(i32 %x) {
+; CHECK-LABEL: @smax1(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0, !prof ![[$MD1]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %not_x = xor i32 %x, -1
+ %cmp = icmp slt i32 %x, 0
+ %sel = select i1 %cmp, i32 %not_x, i32 -1, !prof !1
+ ret i32 %sel
+}
+
+; The compare should change, and the metadata is swapped because the select operands are swapped and inverted.
+define i32 @smax2(i32 %x) {
+; CHECK-LABEL: @smax2(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0, !prof ![[$MD3]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %not_x = xor i32 %x, -1
+ %cmp = icmp sgt i32 %x, 0
+ %sel = select i1 %cmp, i32 -1, i32 %not_x, !prof !1
+ ret i32 %sel
+}
+
+; The compare should change, but the metadata remains the same because the select operands are not swapped.
+define i32 @umin1(i32 %x) {
+; CHECK-LABEL: @umin1(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %x, -2147483648
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 -2147483648, !prof ![[$MD1]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp sgt i32 %x, -1
+ %sel = select i1 %cmp, i32 %x, i32 -2147483648, !prof !1
+ ret i32 %sel
+}
+
+; The compare should change, and the metadata is swapped because the select operands are swapped.
+define i32 @umin2(i32 %x) {
+; CHECK-LABEL: @umin2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %x, 2147483647
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 2147483647, !prof ![[$MD3]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp slt i32 %x, 0
+ %sel = select i1 %cmp, i32 2147483647, i32 %x, !prof !1
+ ret i32 %sel
+}
+
+; The compare should change, but the metadata remains the same because the select operands are not swapped.
+define i32 @umax1(i32 %x) {
+; CHECK-LABEL: @umax1(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %x, 2147483647
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 2147483647, !prof ![[$MD1]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp slt i32 %x, 0
+ %sel = select i1 %cmp, i32 %x, i32 2147483647, !prof !1
+ ret i32 %sel
+}
+
+; The compare should change, and the metadata is swapped because the select operands are swapped.
+define i32 @umax2(i32 %x) {
+; CHECK-LABEL: @umax2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %x, -2147483648
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 -2147483648, !prof ![[$MD3]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp = icmp sgt i32 %x, -1
+ %sel = select i1 %cmp, i32 -2147483648, i32 %x, !prof !1
+ ret i32 %sel
+}
+
+; The condition is inverted, and the select ops are swapped. The metadata should be swapped.
+
+define i32 @not_cond(i1 %c, i32 %tv, i32 %fv) {
+; CHECK-LABEL: @not_cond(
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i32 [[FV:%.*]], i32 [[TV:%.*]], !prof ![[$MD3]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %notc = xor i1 %c, true
+ %r = select i1 %notc, i32 %tv, i32 %fv, !prof !1
+ ret i32 %r
+}
+
+; The condition is inverted, and the select ops are swapped. The metadata should be swapped.
+
+define <2 x i32> @not_cond_vec(<2 x i1> %c, <2 x i32> %tv, <2 x i32> %fv) {
+; CHECK-LABEL: @not_cond_vec(
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i32> [[FV:%.*]], <2 x i32> [[TV:%.*]], !prof ![[$MD3]]
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %notc = xor <2 x i1> %c, <i1 true, i1 true>
+ %r = select <2 x i1> %notc, <2 x i32> %tv, <2 x i32> %fv, !prof !1
+ ret <2 x i32> %r
+}
+
+; Should match vector 'not' with undef element.
+; The condition is inverted, and the select ops are swapped. The metadata should be swapped.
+
+define <2 x i32> @not_cond_vec_undef(<2 x i1> %c, <2 x i32> %tv, <2 x i32> %fv) {
+; CHECK-LABEL: @not_cond_vec_undef(
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i32> [[FV:%.*]], <2 x i32> [[TV:%.*]], !prof ![[$MD3]]
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %notc = xor <2 x i1> %c, <i1 undef, i1 true>
+ %r = select <2 x i1> %notc, <2 x i32> %tv, <2 x i32> %fv, !prof !1
+ ret <2 x i32> %r
+}
+
+
+!1 = !{!"branch_weights", i32 2, i32 10}
+!2 = !{!"branch_weights", i32 3, i32 10}
+
+; CHECK-DAG: ![[$MD1]] = !{!"branch_weights", i32 2, i32 10}
+; CHECK-DAG: ![[$MD3]] = !{!"branch_weights", i32 10, i32 2}
+; CHECK-DAG: ![[$MD4]] = !{!"branch_weights", i32 10, i32 3}
+
Added: llvm/trunk/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,300 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; https://bugs.llvm.org/show_bug.cgi?id=37603
+
+; Pattern:
+; (1 << NBits) - 1
+; Should be transformed into:
+; ~(-(1 << NBits))
+; The `not` may end up being folded into `and`
+
+; ============================================================================ ;
+; Most basic positive tests
+; ============================================================================ ;
+
+; No no-wrap tags on shl
+
+define i32 @shl_add(i32 %NBits) {
+; CHECK-LABEL: @shl_add(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl i32 1, %NBits
+ %ret = add i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_add_nsw(i32 %NBits) {
+; CHECK-LABEL: @shl_add_nsw(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl i32 1, %NBits
+ %ret = add nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_add_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_add_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl i32 1, %NBits
+ %ret = add nuw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_add_nsw_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_add_nsw_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl i32 1, %NBits
+ %ret = add nuw nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+; shl is nsw
+
+define i32 @shl_nsw_add(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_add(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl nsw i32 1, %NBits
+ %ret = add i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nsw_add_nsw(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_add_nsw(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl nsw i32 1, %NBits
+ %ret = add nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nsw_add_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_add_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl nsw i32 1, %NBits
+ %ret = add nuw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nsw_add_nsw_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_add_nsw_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl nsw i32 1, %NBits
+ %ret = add nuw nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+; shl is nuw
+
+define i32 @shl_nuw_add(i32 %NBits) {
+; CHECK-LABEL: @shl_nuw_add(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl nuw i32 1, %NBits
+ %ret = add i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nuw_add_nsw(i32 %NBits) {
+; CHECK-LABEL: @shl_nuw_add_nsw(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl nuw i32 1, %NBits
+ %ret = add nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nuw_add_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_nuw_add_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl nuw i32 1, %NBits
+ %ret = add nuw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nuw_add_nsw_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_nuw_add_nsw_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl nuw i32 1, %NBits
+ %ret = add nuw nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+; shl is nuw nsw
+
+define i32 @shl_nsw_nuw_add(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_nuw_add(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl nuw nsw i32 1, %NBits
+ %ret = add i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nsw_nuw_add_nsw(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_nuw_add_nsw(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor i32 [[NOTMASK]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl nuw nsw i32 1, %NBits
+ %ret = add nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nsw_nuw_add_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_nuw_add_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl nuw nsw i32 1, %NBits
+ %ret = add nuw i32 %setbit, -1
+ ret i32 %ret
+}
+
+define i32 @shl_nsw_nuw_add_nsw_nuw(i32 %NBits) {
+; CHECK-LABEL: @shl_nsw_nuw_add_nsw_nuw(
+; CHECK-NEXT: ret i32 -1
+;
+ %setbit = shl nuw nsw i32 1, %NBits
+ %ret = add nuw nsw i32 %setbit, -1
+ ret i32 %ret
+}
+
+; ============================================================================ ;
+; Vectors
+; ============================================================================ ;
+
+define <2 x i32> @shl_add_vec(<2 x i32> %NBits) {
+; CHECK-LABEL: @shl_add_vec(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw <2 x i32> <i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor <2 x i32> [[NOTMASK]], <i32 -1, i32 -1>
+; CHECK-NEXT: ret <2 x i32> [[RET]]
+;
+ %setbit = shl <2 x i32> <i32 1, i32 1>, %NBits
+ %ret = add <2 x i32> %setbit, <i32 -1, i32 -1>
+ ret <2 x i32> %ret
+}
+
+define <3 x i32> @shl_add_vec_undef0(<3 x i32> %NBits) {
+; CHECK-LABEL: @shl_add_vec_undef0(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor <3 x i32> [[NOTMASK]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: ret <3 x i32> [[RET]]
+;
+ %setbit = shl <3 x i32> <i32 1, i32 undef, i32 1>, %NBits
+ %ret = add <3 x i32> %setbit, <i32 -1, i32 -1, i32 -1>
+ ret <3 x i32> %ret
+}
+
+define <3 x i32> @shl_add_vec_undef1(<3 x i32> %NBits) {
+; CHECK-LABEL: @shl_add_vec_undef1(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor <3 x i32> [[NOTMASK]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: ret <3 x i32> [[RET]]
+;
+ %setbit = shl <3 x i32> <i32 1, i32 1, i32 1>, %NBits
+ %ret = add <3 x i32> %setbit, <i32 -1, i32 undef, i32 -1>
+ ret <3 x i32> %ret
+}
+
+define <3 x i32> @shl_add_vec_undef2(<3 x i32> %NBits) {
+; CHECK-LABEL: @shl_add_vec_undef2(
+; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = xor <3 x i32> [[NOTMASK]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: ret <3 x i32> [[RET]]
+;
+ %setbit = shl <3 x i32> <i32 1, i32 undef, i32 1>, %NBits
+ %ret = add <3 x i32> %setbit, <i32 -1, i32 undef, i32 -1>
+ ret <3 x i32> %ret
+}
+
+; ============================================================================ ;
+; Negative tests. Should not be folded.
+; ============================================================================ ;
+
+declare void @use32(i32)
+
+; One use only.
+define i32 @bad_oneuse0(i32 %NBits) {
+; CHECK-LABEL: @bad_oneuse0(
+; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[SETBIT]])
+; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl i32 1, %NBits
+ call void @use32(i32 %setbit)
+ %ret = add i32 %setbit, -1
+ ret i32 %ret
+}
+
+; shift base is not `1` constant
+
+define i32 @bad_shl(i32 %base, i32 %NBits) {
+; CHECK-LABEL: @bad_shl(
+; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 [[BASE:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl i32 %base, %NBits ; %base instead of 1
+ %ret = add i32 %setbit, -1
+ ret i32 %ret
+}
+
+; Second `add` operand is not `-1` constant
+
+define i32 @bad_add0(i32 %NBits, i32 %addop2) {
+; CHECK-LABEL: @bad_add0(
+; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], [[ADDOP2:%.*]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl i32 1, %NBits
+ %ret = add i32 %setbit, %addop2
+ ret i32 %ret
+}
+
+; Bad add constant
+
+define i32 @bad_add1(i32 %NBits) {
+; CHECK-LABEL: @bad_add1(
+; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], 1
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl i32 1, %NBits
+ %ret = add i32 %setbit, 1 ; not -1
+ ret i32 %ret
+}
+
+define i32 @bad_add2(i32 %NBits) {
+; CHECK-LABEL: @bad_add2(
+; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -2
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %setbit = shl i32 1, %NBits
+ %ret = add i32 %setbit, -2 ; not -1
+ ret i32 %ret
+}
Added: llvm/trunk/test/Transforms/InstCombine/set.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/set.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/set.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/set.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,392 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; This test makes sure that all icmp instructions are eliminated.
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+ at X = external global i32
+
+define i1 @test1(i32 %A) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: ret i1 false
+;
+ %B = icmp eq i32 %A, %A
+ ; Never true
+ %C = icmp eq i32* @X, null
+ %D = and i1 %B, %C
+ ret i1 %D
+}
+
+define i1 @test2(i32 %A) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: ret i1 true
+;
+ %B = icmp ne i32 %A, %A
+ ; Never false
+ %C = icmp ne i32* @X, null
+ %D = or i1 %B, %C
+ ret i1 %D
+}
+
+define i1 @test3(i32 %A) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: ret i1 false
+;
+ %B = icmp slt i32 %A, %A
+ ret i1 %B
+}
+
+
+define i1 @test4(i32 %A) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: ret i1 false
+;
+ %B = icmp sgt i32 %A, %A
+ ret i1 %B
+}
+
+define i1 @test5(i32 %A) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: ret i1 true
+;
+ %B = icmp sle i32 %A, %A
+ ret i1 %B
+}
+
+define i1 @test6(i32 %A) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: ret i1 true
+;
+ %B = icmp sge i32 %A, %A
+ ret i1 %B
+}
+
+define i1 @test7(i32 %A) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: ret i1 true
+;
+ %B = icmp uge i32 %A, 0
+ ret i1 %B
+}
+
+define i1 @test8(i32 %A) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: ret i1 false
+;
+ %B = icmp ult i32 %A, 0
+ ret i1 %B
+}
+
+;; test operations on boolean values these should all be eliminated$a
+define i1 @test9(i1 %A) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: ret i1 false
+;
+ %B = icmp ult i1 %A, false
+ ret i1 %B
+}
+
+define i1 @test10(i1 %A) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: ret i1 false
+;
+ %B = icmp ugt i1 %A, true
+ ret i1 %B
+}
+
+define i1 @test11(i1 %A) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: ret i1 true
+;
+ %B = icmp ule i1 %A, true
+ ret i1 %B
+}
+
+define i1 @test12(i1 %A) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: ret i1 true
+;
+ %B = icmp uge i1 %A, false
+ ret i1 %B
+}
+
+define i1 @test13(i1 %A, i1 %B) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT: [[C:%.*]] = or i1 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %C = icmp uge i1 %A, %B
+ ret i1 %C
+}
+
+define <2 x i1> @test13vec(<2 x i1> %A, <2 x i1> %B) {
+; CHECK-LABEL: @test13vec(
+; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i1> [[B:%.*]], <i1 true, i1 true>
+; CHECK-NEXT: [[C:%.*]] = or <2 x i1> [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %C = icmp uge <2 x i1> %A, %B
+ ret <2 x i1> %C
+}
+
+define i1 @test14(i1 %A, i1 %B) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[C:%.*]] = xor i1 [[TMP1]], true
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %C = icmp eq i1 %A, %B
+ ret i1 %C
+}
+
+define <3 x i1> @test14vec(<3 x i1> %A, <3 x i1> %B) {
+; CHECK-LABEL: @test14vec(
+; CHECK-NEXT: [[TMP1:%.*]] = xor <3 x i1> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[C:%.*]] = xor <3 x i1> [[TMP1]], <i1 true, i1 true, i1 true>
+; CHECK-NEXT: ret <3 x i1> [[C]]
+;
+ %C = icmp eq <3 x i1> %A, %B
+ ret <3 x i1> %C
+}
+
+define i1 @bool_eq0(i64 %a) {
+; CHECK-LABEL: @bool_eq0(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], 1
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %b = icmp sgt i64 %a, 0
+ %c = icmp eq i64 %a, 1
+ %notc = icmp eq i1 %c, false
+ %and = and i1 %b, %notc
+ ret i1 %and
+}
+
+; This is equivalent to the previous test.
+
+define i1 @xor_of_icmps(i64 %a) {
+; CHECK-LABEL: @xor_of_icmps(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], 1
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %b = icmp sgt i64 %a, 0
+ %c = icmp eq i64 %a, 1
+ %xor = xor i1 %c, %b
+ ret i1 %xor
+}
+
+; This is also equivalent to the previous test.
+
+define i1 @xor_of_icmps_commute(i64 %a) {
+; CHECK-LABEL: @xor_of_icmps_commute(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], 1
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %b = icmp sgt i64 %a, 0
+ %c = icmp eq i64 %a, 1
+ %xor = xor i1 %b, %c
+ ret i1 %xor
+}
+
+; FIXME: This is (a != 5).
+
+define i1 @xor_of_icmps_folds_more(i64 %a) {
+; CHECK-LABEL: @xor_of_icmps_folds_more(
+; CHECK-NEXT: [[B:%.*]] = icmp sgt i64 [[A:%.*]], 4
+; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[A]], 6
+; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[B]], [[C]]
+; CHECK-NEXT: ret i1 [[XOR]]
+;
+ %b = icmp sgt i64 %a, 4
+ %c = icmp slt i64 %a, 6
+ %xor = xor i1 %b, %c
+ ret i1 %xor
+}
+
+; https://bugs.llvm.org/show_bug.cgi?id=2844
+
+define i32 @PR2844(i32 %x) {
+; CHECK-LABEL: @PR2844(
+; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -638208502
+; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %A = icmp eq i32 %x, 0
+ %B = icmp slt i32 %x, -638208501
+ %or = or i1 %A, %B
+ %sel = select i1 %or, i32 0, i32 1
+ ret i32 %sel
+}
+
+define i1 @test16(i32 %A) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: ret i1 false
+;
+ %B = and i32 %A, 5
+ ; Is never true
+ %C = icmp eq i32 %B, 8
+ ret i1 %C
+}
+
+define i1 @test17(i8 %A) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: ret i1 false
+;
+ %B = or i8 %A, 1
+ ; Always false
+ %C = icmp eq i8 %B, 2
+ ret i1 %C
+}
+
+define i1 @test18(i1 %C, i32 %a) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[ENDIF:%.*]], label [[ELSE:%.*]]
+; CHECK: else:
+; CHECK-NEXT: br label [[ENDIF]]
+; CHECK: endif:
+; CHECK-NEXT: ret i1 true
+;
+entry:
+ br i1 %C, label %endif, label %else
+
+else:
+ br label %endif
+
+endif:
+ %b.0 = phi i32 [ 0, %entry ], [ 1, %else ]
+ %tmp.4 = icmp slt i32 %b.0, 123
+ ret i1 %tmp.4
+}
+
+define i1 @test19(i1 %A, i1 %B) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[C:%.*]] = xor i1 [[TMP1]], true
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %a = zext i1 %A to i32
+ %b = zext i1 %B to i32
+ %C = icmp eq i32 %a, %b
+ ret i1 %C
+}
+
+define i32 @test20(i32 %A) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], 1
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %B = and i32 %A, 1
+ %C = icmp ne i32 %B, 0
+ %D = zext i1 %C to i32
+ ret i32 %D
+}
+
+define <2 x i32> @test20vec(<2 x i32> %A) {
+; CHECK-LABEL: @test20vec(
+; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[A:%.*]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %B = and <2 x i32> %A, <i32 1, i32 1>
+ %C = icmp ne <2 x i32> %B, zeroinitializer
+ %D = zext <2 x i1> %C to <2 x i32>
+ ret <2 x i32> %D
+}
+
+define i32 @test21(i32 %a) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT: [[TMP_6:%.*]] = lshr i32 [[A:%.*]], 2
+; CHECK-NEXT: [[TMP_6_LOBIT:%.*]] = and i32 [[TMP_6]], 1
+; CHECK-NEXT: ret i32 [[TMP_6_LOBIT]]
+;
+ %tmp.6 = and i32 %a, 4
+ %not.tmp.7 = icmp ne i32 %tmp.6, 0
+ %retval = zext i1 %not.tmp.7 to i32
+ ret i32 %retval
+}
+
+define <2 x i32> @test21vec(<2 x i32> %a) {
+; CHECK-LABEL: @test21vec(
+; CHECK-NEXT: [[TMP_6:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP_6_LOBIT:%.*]] = and <2 x i32> [[TMP_6]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[TMP_6_LOBIT]]
+;
+ %tmp.6 = and <2 x i32> %a, <i32 4, i32 4>
+ %not.tmp.7 = icmp ne <2 x i32> %tmp.6, zeroinitializer
+ %retval = zext <2 x i1> %not.tmp.7 to <2 x i32>
+ ret <2 x i32> %retval
+}
+
+define i1 @test22(i32 %A, i32 %X) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT: ret i1 true
+;
+ %B = and i32 %A, 100663295
+ %C = icmp ult i32 %B, 268435456
+ %Y = and i32 %X, 7
+ %Z = icmp sgt i32 %Y, -1
+ %R = or i1 %C, %Z
+ ret i1 %R
+}
+
+define i32 @test23(i32 %a) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT: [[TMP_1:%.*]] = and i32 [[A:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[TMP_1]], 1
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %tmp.1 = and i32 %a, 1
+ %tmp.2 = icmp eq i32 %tmp.1, 0
+ %tmp.3 = zext i1 %tmp.2 to i32
+ ret i32 %tmp.3
+}
+
+define <2 x i32> @test23vec(<2 x i32> %a) {
+; CHECK-LABEL: @test23vec(
+; CHECK-NEXT: [[TMP_1:%.*]] = and <2 x i32> [[A:%.*]], <i32 1, i32 1>
+; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[TMP_1]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %tmp.1 = and <2 x i32> %a, <i32 1, i32 1>
+ %tmp.2 = icmp eq <2 x i32> %tmp.1, zeroinitializer
+ %tmp.3 = zext <2 x i1> %tmp.2 to <2 x i32>
+ ret <2 x i32> %tmp.3
+}
+
+define i32 @test24(i32 %a) {
+; CHECK-LABEL: @test24(
+; CHECK-NEXT: [[TMP_1:%.*]] = lshr i32 [[A:%.*]], 2
+; CHECK-NEXT: [[TMP_1_LOBIT:%.*]] = and i32 [[TMP_1]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[TMP_1_LOBIT]], 1
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %tmp1 = and i32 %a, 4
+ %tmp.1 = lshr i32 %tmp1, 2
+ %tmp.2 = icmp eq i32 %tmp.1, 0
+ %tmp.3 = zext i1 %tmp.2 to i32
+ ret i32 %tmp.3
+}
+
+define <2 x i32> @test24vec(<2 x i32> %a) {
+; CHECK-LABEL: @test24vec(
+; CHECK-NEXT: [[TMP_1:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP_1_LOBIT:%.*]] = and <2 x i32> [[TMP_1]], <i32 1, i32 1>
+; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[TMP_1_LOBIT]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+;
+ %tmp1 = and <2 x i32> %a, <i32 4, i32 4>
+ %tmp.1 = lshr <2 x i32> %tmp1, <i32 2, i32 2>
+ %tmp.2 = icmp eq <2 x i32> %tmp.1, zeroinitializer
+ %tmp.3 = zext <2 x i1> %tmp.2 to <2 x i32>
+ ret <2 x i32> %tmp.3
+}
+
+define i1 @test25(i32 %A) {
+; CHECK-LABEL: @test25(
+; CHECK-NEXT: ret i1 false
+;
+ %B = and i32 %A, 2
+ %C = icmp ugt i32 %B, 2
+ ret i1 %C
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/setcc-strength-reduce.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/setcc-strength-reduce.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/setcc-strength-reduce.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/setcc-strength-reduce.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,37 @@
+; This test ensures that "strength reduction" of conditional expressions are
+; working. Basically this boils down to converting setlt,gt,le,ge instructions
+; into equivalent setne,eq instructions.
+;
+; RUN: opt < %s -instcombine -S | \
+; RUN: grep -v "icmp eq" | grep -v "icmp ne" | not grep icmp
+; END.
+
+define i1 @test1(i32 %A) {
+ ; setne %A, 0
+ %B = icmp uge i32 %A, 1 ; <i1> [#uses=1]
+ ret i1 %B
+}
+
+define i1 @test2(i32 %A) {
+ ; setne %A, 0
+ %B = icmp ugt i32 %A, 0 ; <i1> [#uses=1]
+ ret i1 %B
+}
+
+define i1 @test3(i8 %A) {
+ ; setne %A, -128
+ %B = icmp sge i8 %A, -127 ; <i1> [#uses=1]
+ ret i1 %B
+}
+
+define i1 @test4(i8 %A) {
+ ; setne %A, 127
+ %B = icmp sle i8 %A, 126 ; <i1> [#uses=1]
+ ret i1 %B
+}
+
+define i1 @test5(i8 %A) {
+ ; setne %A, 127
+ %B = icmp slt i8 %A, 127 ; <i1> [#uses=1]
+ ret i1 %B
+}
Added: llvm/trunk/test/Transforms/InstCombine/sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sext.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sext.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sext.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,242 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+
+declare i32 @llvm.ctpop.i32(i32)
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define i64 @test1(i32 %x) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 %x)
+; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S1]]
+;
+ %t = call i32 @llvm.ctpop.i32(i32 %x)
+ %s = sext i32 %t to i64
+ ret i64 %s
+}
+
+define i64 @test2(i32 %x) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S1]]
+;
+ %t = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+ %s = sext i32 %t to i64
+ ret i64 %s
+}
+
+define i64 @test3(i32 %x) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S1]]
+;
+ %t = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ %s = sext i32 %t to i64
+ ret i64 %s
+}
+
+define i64 @test4(i32 %x) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[T:%.*]] = udiv i32 %x, 3
+; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S1]]
+;
+ %t = udiv i32 %x, 3
+ %s = sext i32 %t to i64
+ ret i64 %s
+}
+
+define i64 @test5(i32 %x) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[T:%.*]] = urem i32 %x, 30000
+; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S1]]
+;
+ %t = urem i32 %x, 30000
+ %s = sext i32 %t to i64
+ ret i64 %s
+}
+
+define i64 @test6(i32 %x) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[U:%.*]] = lshr i32 %x, 3
+; CHECK-NEXT: [[T:%.*]] = mul nuw nsw i32 [[U]], 3
+; CHECK-NEXT: [[S1:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT: ret i64 [[S1]]
+;
+ %u = lshr i32 %x, 3
+ %t = mul i32 %u, 3
+ %s = sext i32 %t to i64
+ ret i64 %s
+}
+
+define i64 @test7(i32 %x) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: [[T:%.*]] = and i32 %x, 511
+; CHECK-NEXT: [[U:%.*]] = sub nuw nsw i32 20000, [[T]]
+; CHECK-NEXT: [[S1:%.*]] = zext i32 [[U]] to i64
+; CHECK-NEXT: ret i64 [[S1]]
+;
+ %t = and i32 %x, 511
+ %u = sub i32 20000, %t
+ %s = sext i32 %u to i64
+ ret i64 %s
+}
+
+define i32 @test8(i8 %a, i32 %f, i1 %p, i32* %z) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: [[D:%.*]] = lshr i32 %f, 24
+; CHECK-NEXT: [[N:%.*]] = select i1 %p, i32 [[D]], i32 0
+; CHECK-NEXT: ret i32 [[N]]
+;
+ %d = lshr i32 %f, 24
+ %e = select i1 %p, i32 %d, i32 0
+ %s = trunc i32 %e to i16
+ %n = sext i16 %s to i32
+ ret i32 %n
+}
+
+; rdar://6013816
+define i16 @test9(i16 %t, i1 %cond) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 %cond, label %T, label %F
+; CHECK: T:
+; CHECK-NEXT: br label %F
+; CHECK: F:
+; CHECK-NEXT: [[V_OFF0:%.*]] = phi i16 [ %t, %T ], [ 42, %entry ]
+; CHECK-NEXT: ret i16 [[V_OFF0]]
+;
+entry:
+ br i1 %cond, label %T, label %F
+T:
+ %t2 = sext i16 %t to i32
+ br label %F
+
+F:
+ %V = phi i32 [%t2, %T], [42, %entry]
+ %W = trunc i32 %V to i16
+ ret i16 %W
+}
+
+; PR2638
+define i32 @test10(i32 %i) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: [[B1:%.*]] = shl i32 %i, 30
+; CHECK-NEXT: [[B:%.*]] = ashr exact i32 [[B1]], 30
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %tmp12 = trunc i32 %i to i8
+ %tmp16 = shl i8 %tmp12, 6
+ %a = ashr i8 %tmp16, 6
+ %b = sext i8 %a to i32
+ ret i32 %b
+}
+
+define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i16> %srcB, %srcA
+; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i16>
+; CHECK-NEXT: store <2 x i16> [[SEXT]], <2 x i16>* %dst, align 4
+; CHECK-NEXT: ret void
+;
+ %cmp = icmp eq <2 x i16> %srcB, %srcA
+ %sext = sext <2 x i1> %cmp to <2 x i16>
+ %tmask = ashr <2 x i16> %sext, <i16 15, i16 15>
+ store <2 x i16> %tmask, <2 x i16>* %dst
+ ret void
+}
+
+define i64 @test12(i32 %x) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[SHR]]
+; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[SUB]] to i64
+; CHECK-NEXT: ret i64 [[CONV]]
+;
+ %shr = lshr i32 %x, 1
+ %sub = sub nsw i32 0, %shr
+ %conv = sext i32 %sub to i64
+ ret i64 %conv
+}
+
+define i32 @test13(i32 %x) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: [[AND:%.*]] = lshr i32 %x, 3
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 1
+; CHECK-NEXT: [[SEXT:%.*]] = add nsw i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[SEXT]]
+;
+ %and = and i32 %x, 8
+ %cmp = icmp eq i32 %and, 0
+ %ext = sext i1 %cmp to i32
+ ret i32 %ext
+}
+
+define i32 @test14(i16 %x) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT: [[AND:%.*]] = lshr i16 %x, 4
+; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[AND]], 1
+; CHECK-NEXT: [[SEXT:%.*]] = add nsw i16 [[TMP1]], -1
+; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
+; CHECK-NEXT: ret i32 [[EXT]]
+;
+ %and = and i16 %x, 16
+ %cmp = icmp ne i16 %and, 16
+ %ext = sext i1 %cmp to i32
+ ret i32 %ext
+}
+
+define i32 @test15(i32 %x) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 27
+; CHECK-NEXT: [[SEXT:%.*]] = ashr i32 [[TMP1]], 31
+; CHECK-NEXT: ret i32 [[SEXT]]
+;
+ %and = and i32 %x, 16
+ %cmp = icmp ne i32 %and, 0
+ %ext = sext i1 %cmp to i32
+ ret i32 %ext
+}
+
+define i32 @test16(i16 %x) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i16 %x, 12
+; CHECK-NEXT: [[SEXT:%.*]] = ashr i16 [[TMP1]], 15
+; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
+; CHECK-NEXT: ret i32 [[EXT]]
+;
+ %and = and i16 %x, 8
+ %cmp = icmp eq i16 %and, 8
+ %ext = sext i1 %cmp to i32
+ ret i32 %ext
+}
+
+define i32 @test17(i1 %x) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[C2:%.*]] = zext i1 %x to i32
+; CHECK-NEXT: ret i32 [[C2]]
+;
+ %c1 = sext i1 %x to i32
+ %c2 = sub i32 0, %c1
+ ret i32 %c2
+}
+
+define i32 @test18(i16 %x) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 %x, 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TMP1]], i16 %x, i16 0
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[SEL]] to i32
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %cmp = icmp slt i16 %x, 0
+ %sel = select i1 %cmp, i16 0, i16 %x
+ %ext = sext i16 %sel to i32
+ ret i32 %ext
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/shift-add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift-add.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift-add.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shift-add.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; This test makes sure that these instructions are properly eliminated.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @shl_C1_add_A_C2_i32(i16 %A) {
+; CHECK-LABEL: @shl_C1_add_A_C2_i32(
+; CHECK-NEXT: [[B:%.*]] = zext i16 %A to i32
+; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
+; CHECK-NEXT: ret i32 [[D]]
+;
+ %B = zext i16 %A to i32
+ %C = add i32 %B, 5
+ %D = shl i32 6, %C
+ ret i32 %D
+}
+
+define i32 @ashr_C1_add_A_C2_i32(i32 %A) {
+; CHECK-LABEL: @ashr_C1_add_A_C2_i32(
+; CHECK-NEXT: ret i32 0
+;
+ %B = and i32 %A, 65535
+ %C = add i32 %B, 5
+ %D = ashr i32 6, %C
+ ret i32 %D
+}
+
+define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
+; CHECK-LABEL: @lshr_C1_add_A_C2_i32(
+; CHECK-NEXT: [[B:%.*]] = and i32 %A, 65535
+; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
+; CHECK-NEXT: ret i32 [[D]]
+;
+ %B = and i32 %A, 65535
+ %C = add i32 %B, 5
+ %D = shl i32 6, %C
+ ret i32 %D
+}
+
+define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
+; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
+; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> %A to <4 x i32>
+; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 undef, i32 -458752>, [[B]]
+; CHECK-NEXT: ret <4 x i32> [[D]]
+;
+ %B = zext <4 x i16> %A to <4 x i32>
+ %C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
+ %D = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
+ ret <4 x i32> %D
+}
+
+define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) {
+; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32(
+; CHECK-NEXT: [[B:%.*]] = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+; CHECK-NEXT: [[D:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 undef, i32 -1>, [[B]]
+; CHECK-NEXT: ret <4 x i32> [[D]]
+;
+ %B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+ %C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
+ %D = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
+ ret <4 x i32> %D
+}
+
+define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) {
+; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32(
+; CHECK-NEXT: [[B:%.*]] = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+; CHECK-NEXT: [[D:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 undef, i32 65535>, [[B]]
+; CHECK-NEXT: ret <4 x i32> [[D]]
+;
+ %B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+ %C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
+ %D = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
+ ret <4 x i32> %D
+}
Added: llvm/trunk/test/Transforms/InstCombine/shift-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift-shift.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift-shift.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shift-shift.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; These would crash if we didn't check for a negative shift.
+
+; https://llvm.org/bugs/show_bug.cgi?id=12967
+
+define void @pr12967() {
+; CHECK-LABEL: @pr12967(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label %loop
+; CHECK: loop:
+; CHECK-NEXT: br label %loop
+;
+entry:
+ br label %loop
+
+loop:
+ %c = phi i32 [ %shl, %loop ], [ undef, %entry ]
+ %shr = shl i32 %c, 7
+ %shl = lshr i32 %shr, -2
+ br label %loop
+}
+
+; https://llvm.org/bugs/show_bug.cgi?id=26760
+
+define void @pr26760() {
+; CHECK-LABEL: @pr26760(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label %loop
+; CHECK: loop:
+; CHECK-NEXT: br label %loop
+;
+entry:
+ br label %loop
+
+loop:
+ %c = phi i32 [ %shl, %loop ], [ undef, %entry ]
+ %shr = lshr i32 %c, 7
+ %shl = shl i32 %shr, -2
+ br label %loop
+}
+
+; Converting the 2 shifts to SHL 6 without the AND is wrong.
+; https://llvm.org/bugs/show_bug.cgi?id=8547
+
+define i32 @pr8547(i32* %g) {
+; CHECK-LABEL: @pr8547(
+; CHECK-NEXT: codeRepl:
+; CHECK-NEXT: br label %for.cond
+; CHECK: for.cond:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
+; CHECK-NEXT: store i32 [[STOREMERGE]], i32* %g, align 4
+; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i32 [[STOREMERGE]], 6
+; CHECK-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 64
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[CONV2]], 0
+; CHECK-NEXT: br i1 [[TOBOOL]], label %for.cond, label %codeRepl2
+; CHECK: codeRepl2:
+; CHECK-NEXT: ret i32 [[CONV2]]
+;
+codeRepl:
+ br label %for.cond
+
+for.cond:
+ %storemerge = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
+ store i32 %storemerge, i32* %g, align 4
+ %shl = shl i32 %storemerge, 30
+ %conv2 = lshr i32 %shl, 24
+ %tobool = icmp eq i32 %conv2, 0
+ br i1 %tobool, label %for.cond, label %codeRepl2
+
+codeRepl2:
+ ret i32 %conv2
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/shift-sra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift-sra.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift-sra.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shift-sra.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,217 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+
+define i32 @test1(i32 %X, i8 %A) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 %A to i32
+; CHECK-NEXT: [[Y1:%.*]] = lshr i32 %X, [[SHIFT_UPGRD_1]]
+; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y1]], 1
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %shift.upgrd.1 = zext i8 %A to i32
+ ; can be logical shift.
+ %Y = ashr i32 %X, %shift.upgrd.1
+ %Z = and i32 %Y, 1
+ ret i32 %Z
+}
+
+define i32 @test2(i8 %tmp) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[TMP3:%.*]] = zext i8 %tmp to i32
+; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 7
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP4]], 3
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %tmp3 = zext i8 %tmp to i32
+ %tmp4 = add i32 %tmp3, 7
+ %tmp5 = ashr i32 %tmp4, 3
+ ret i32 %tmp5
+}
+
+define i64 @test3(i1 %X, i64 %Y, i1 %Cond) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: br i1 %Cond, label %T, label %F
+; CHECK: T:
+; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
+; CHECK-NEXT: br label %C
+; CHECK: F:
+; CHECK-NEXT: [[Y2:%.*]] = ashr i64 %Y, 63
+; CHECK-NEXT: br label %C
+; CHECK: C:
+; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
+; CHECK-NEXT: ret i64 [[P]]
+;
+ br i1 %Cond, label %T, label %F
+T:
+ %X2 = sext i1 %X to i64
+ br label %C
+F:
+ %Y2 = ashr i64 %Y, 63
+ br label %C
+C:
+ %P = phi i64 [%X2, %T], [%Y2, %F]
+ %S = ashr i64 %P, 12
+ ret i64 %S
+}
+
+define i64 @test4(i1 %X, i64 %Y, i1 %Cond) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: br i1 %Cond, label %T, label %F
+; CHECK: T:
+; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
+; CHECK-NEXT: br label %C
+; CHECK: F:
+; CHECK-NEXT: [[Y2:%.*]] = ashr i64 %Y, 63
+; CHECK-NEXT: br label %C
+; CHECK: C:
+; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
+; CHECK-NEXT: ret i64 [[P]]
+;
+ br i1 %Cond, label %T, label %F
+T:
+ %X2 = sext i1 %X to i64
+ br label %C
+F:
+ %Y2 = ashr i64 %Y, 63
+ br label %C
+C:
+ %P = phi i64 [%X2, %T], [%Y2, %F]
+ %R = shl i64 %P, 12
+ %S = ashr i64 %R, 12
+ ret i64 %S
+}
+
+; rdar://7732987
+define i32 @test5(i32 %Y) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: br i1 undef, label %A, label %C
+; CHECK: A:
+; CHECK-NEXT: br i1 undef, label %B, label %D
+; CHECK: B:
+; CHECK-NEXT: br label %D
+; CHECK: C:
+; CHECK-NEXT: br i1 undef, label %D, label %E
+; CHECK: D:
+; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, %A ], [ 0, %B ], [ %Y, %C ]
+; CHECK-NEXT: [[S:%.*]] = ashr i32 [[P]], 16
+; CHECK-NEXT: ret i32 [[S]]
+; CHECK: E:
+; CHECK-NEXT: ret i32 0
+;
+ br i1 undef, label %A, label %C
+A:
+ br i1 undef, label %B, label %D
+B:
+ br label %D
+C:
+ br i1 undef, label %D, label %E
+D:
+ %P = phi i32 [0, %A], [0, %B], [%Y, %C]
+ %S = ashr i32 %P, 16
+ ret i32 %S
+E:
+ ret i32 0
+}
+
+; (X >>s C1) >>s C2 --> X >>s (C1 + C2)
+
+define i32 @ashr_ashr(i32 %x) {
+; CHECK-LABEL: @ashr_ashr(
+; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 12
+; CHECK-NEXT: ret i32 [[SH2]]
+;
+ %sh1 = ashr i32 %x, 5
+ %sh2 = ashr i32 %sh1, 7
+ ret i32 %sh2
+}
+
+; PR3851
+; (X >>s C1) >>s C2 --> X >>s (Bitwidth - 1)
+
+define i32 @ashr_overshift(i32 %x) {
+; CHECK-LABEL: @ashr_overshift(
+; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 31
+; CHECK-NEXT: ret i32 [[SH2]]
+;
+ %sh1 = ashr i32 %x, 15
+ %sh2 = ashr i32 %sh1, 17
+ ret i32 %sh2
+}
+
+; (X >>s C1) >>s C2 --> X >>s (C1 + C2)
+
+define <2 x i32> @ashr_ashr_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @ashr_ashr_splat_vec(
+; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> %x, <i32 12, i32 12>
+; CHECK-NEXT: ret <2 x i32> [[SH2]]
+;
+ %sh1 = ashr <2 x i32> %x, <i32 5, i32 5>
+ %sh2 = ashr <2 x i32> %sh1, <i32 7, i32 7>
+ ret <2 x i32> %sh2
+}
+
+; (X >>s C1) >>s C2 --> X >>s (Bitwidth - 1)
+
+define <2 x i32> @ashr_overshift_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @ashr_overshift_splat_vec(
+; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> %x, <i32 31, i32 31>
+; CHECK-NEXT: ret <2 x i32> [[SH2]]
+;
+ %sh1 = ashr <2 x i32> %x, <i32 15, i32 15>
+ %sh2 = ashr <2 x i32> %sh1, <i32 17, i32 17>
+ ret <2 x i32> %sh2
+}
+
+; ashr (sext X), C --> sext (ashr X, C')
+
+define i32 @hoist_ashr_ahead_of_sext_1(i8 %x) {
+; CHECK-LABEL: @hoist_ashr_ahead_of_sext_1(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 3
+; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %sext = sext i8 %x to i32
+ %r = ashr i32 %sext, 3
+ ret i32 %r
+}
+
+; ashr (sext X), C --> sext (ashr X, C')
+
+define <2 x i32> @hoist_ashr_ahead_of_sext_1_splat(<2 x i8> %x) {
+; CHECK-LABEL: @hoist_ashr_ahead_of_sext_1_splat(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> %x, <i8 3, i8 3>
+; CHECK-NEXT: [[R:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %sext = sext <2 x i8> %x to <2 x i32>
+ %r = ashr <2 x i32> %sext, <i32 3, i32 3>
+ ret <2 x i32> %r
+}
+
+; ashr (sext X), C --> sext (ashr X, C') -- the shift amount must be clamped
+
+define i32 @hoist_ashr_ahead_of_sext_2(i8 %x) {
+; CHECK-LABEL: @hoist_ashr_ahead_of_sext_2(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 7
+; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %sext = sext i8 %x to i32
+ %r = ashr i32 %sext, 8
+ ret i32 %r
+}
+
+; ashr (sext X), C --> sext (ashr X, C') -- the shift amount must be clamped
+
+define <2 x i32> @hoist_ashr_ahead_of_sext_2_splat(<2 x i8> %x) {
+; CHECK-LABEL: @hoist_ashr_ahead_of_sext_2_splat(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT: [[R:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %sext = sext <2 x i8> %x to <2 x i32>
+ %r = ashr <2 x i32> %sext, <i32 8, i32 8>
+ ret <2 x i32> %r
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shift.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1539 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define <4 x i32> @lshr_non_splat_vector(<4 x i32> %A) {
+; CHECK-LABEL: @lshr_non_splat_vector(
+; CHECK-NEXT: [[B:%.*]] = lshr <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[B]]
+;
+ %B = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3>
+ ret <4 x i32> %B
+}
+
+define <4 x i32> @shl_non_splat_vector(<4 x i32> %A) {
+; CHECK-LABEL: @shl_non_splat_vector(
+; CHECK-NEXT: [[B:%.*]] = shl <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[B]]
+;
+ %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3>
+ ret <4 x i32> %B
+}
+
+define i32 @test6(i32 %A) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = shl i32 %A, 1 ;; convert to an mul instruction
+ %C = mul i32 %B, 3
+ ret i32 %C
+}
+
+define i32 @test6a(i32 %A) {
+; CHECK-LABEL: @test6a(
+; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = mul i32 %A, 3
+ %C = shl i32 %B, 1 ;; convert to an mul instruction
+ ret i32 %C
+}
+
+;; (A << 5) << 3 === A << 8 == 0
+define i8 @test8(i8 %A) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: ret i8 0
+;
+ %B = shl i8 %A, 5
+ %C = shl i8 %B, 3
+ ret i8 %C
+}
+
+;; (A << 7) >> 7 === A & 1
+define i8 @test9(i8 %A) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: [[B:%.*]] = and i8 %A, 1
+; CHECK-NEXT: ret i8 [[B]]
+;
+ %B = shl i8 %A, 7
+ %C = lshr i8 %B, 7
+ ret i8 %C
+}
+
+;; (A >> 7) << 7 === A & 128
+
+define i8 @test10(i8 %A) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: [[B:%.*]] = and i8 %A, -128
+; CHECK-NEXT: ret i8 [[B]]
+;
+ %B = lshr i8 %A, 7
+ %C = shl i8 %B, 7
+ ret i8 %C
+}
+
+;; Allow the simplification when the lshr shift is exact.
+define i8 @test10a(i8 %A) {
+; CHECK-LABEL: @test10a(
+; CHECK-NEXT: ret i8 %A
+;
+ %B = lshr exact i8 %A, 7
+ %C = shl i8 %B, 7
+ ret i8 %C
+}
+
+;; This transformation is deferred to DAGCombine:
+;; (A >> 3) << 4 === (A & 0x1F) << 1
+;; The shl may be valuable to scalar evolution.
+define i8 @test11(i8 %A) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3
+; CHECK-NEXT: [[B:%.*]] = lshr i8 [[A]], 3
+; CHECK-NEXT: [[C:%.*]] = shl i8 [[B]], 4
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = mul i8 %A, 3
+ %B = lshr i8 %a, 3
+ %C = shl i8 %B, 4
+ ret i8 %C
+}
+
+;; Allow the simplification in InstCombine when the lshr shift is exact.
+define i8 @test11a(i8 %A) {
+; CHECK-LABEL: @test11a(
+; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = mul i8 %A, 3
+ %B = lshr exact i8 %a, 3
+ %C = shl i8 %B, 4
+ ret i8 %C
+}
+
+;; This is deferred to DAGCombine unless %B is single-use.
+;; (A >> 8) << 8 === A & -256
+define i32 @test12(i32 %A) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: [[B1:%.*]] = and i32 %A, -256
+; CHECK-NEXT: ret i32 [[B1]]
+;
+ %B = ashr i32 %A, 8
+ %C = shl i32 %B, 8
+ ret i32 %C
+}
+
+;; ((A >>s 6) << 6 === (A & FFFFFFC0)
+define i8 @shishi(i8 %x) {
+; CHECK-LABEL: @shishi(
+; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 6
+; CHECK-NEXT: [[B:%.*]] = and i8 [[X]], -64
+; CHECK-NEXT: [[EXTRA_USE_OF_A:%.*]] = mul nsw i8 [[A]], 5
+; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[EXTRA_USE_OF_A]], [[B]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %a = ashr i8 %x, 6
+ %b = shl i8 %a, 6
+ %extra_use_of_a = mul i8 %a, 5
+ %r = sdiv i8 %extra_use_of_a, %b
+ ret i8 %r
+}
+
+;; This transformation is deferred to DAGCombine:
+;; (A >> 3) << 4 === (A & -8) * 2
+;; The shl may be valuable to scalar evolution.
+define i8 @test13(i8 %A) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3
+; CHECK-NEXT: [[B1:%.*]] = lshr i8 [[A]], 3
+; CHECK-NEXT: [[C:%.*]] = shl i8 [[B1]], 4
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = mul i8 %A, 3
+ %B = ashr i8 %a, 3
+ %C = shl i8 %B, 4
+ ret i8 %C
+}
+
+define i8 @test13a(i8 %A) {
+; CHECK-LABEL: @test13a(
+; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %a = mul i8 %A, 3
+ %B = ashr exact i8 %a, 3
+ %C = shl i8 %B, 4
+ ret i8 %C
+}
+
+;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
+define i32 @test14(i32 %A) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT: [[B:%.*]] = and i32 %A, -19760
+; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], 19744
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = lshr i32 %A, 4
+ %C = or i32 %B, 1234
+ %D = shl i32 %C, 4
+ ret i32 %D
+}
+
+;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
+define i32 @test14a(i32 %A) {
+; CHECK-LABEL: @test14a(
+; CHECK-NEXT: [[C:%.*]] = and i32 %A, 77
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = shl i32 %A, 4
+ %C = and i32 %B, 1234
+ %D = lshr i32 %C, 4
+ ret i32 %D
+}
+
+define i32 @test15(i1 %C) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: [[A:%.*]] = select i1 %C, i32 12, i32 4
+; CHECK-NEXT: ret i32 [[A]]
+;
+ %A = select i1 %C, i32 3, i32 1
+ %V = shl i32 %A, 2
+ ret i32 %V
+}
+
+define i32 @test15a(i1 %C) {
+; CHECK-LABEL: @test15a(
+; CHECK-NEXT: [[V:%.*]] = select i1 %C, i32 512, i32 128
+; CHECK-NEXT: ret i32 [[V]]
+;
+ %A = select i1 %C, i8 3, i8 1
+ %shift.upgrd.4 = zext i8 %A to i32
+ %V = shl i32 64, %shift.upgrd.4
+ ret i32 %V
+}
+
+define i1 @test16(i32 %X) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: [[TMP_6:%.*]] = and i32 %X, 16
+; CHECK-NEXT: [[TMP_7:%.*]] = icmp ne i32 [[TMP_6]], 0
+; CHECK-NEXT: ret i1 [[TMP_7]]
+;
+ %tmp.3 = ashr i32 %X, 4
+ %tmp.6 = and i32 %tmp.3, 1
+ %tmp.7 = icmp ne i32 %tmp.6, 0
+ ret i1 %tmp.7
+}
+
+define i1 @test17(i32 %A) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[B_MASK:%.*]] = and i32 %A, -8
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %B = lshr i32 %A, 3
+ %C = icmp eq i32 %B, 1234
+ ret i1 %C
+}
+
+define <2 x i1> @test17vec(<2 x i32> %A) {
+; CHECK-LABEL: @test17vec(
+; CHECK-NEXT: [[B_MASK:%.*]] = and <2 x i32> %A, <i32 -8, i32 -8>
+; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[B_MASK]], <i32 9872, i32 9872>
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %B = lshr <2 x i32> %A, <i32 3, i32 3>
+ %C = icmp eq <2 x i32> %B, <i32 1234, i32 1234>
+ ret <2 x i1> %C
+}
+
+define i1 @test18(i8 %A) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: ret i1 false
+;
+ %B = lshr i8 %A, 7
+ ;; false
+ %C = icmp eq i8 %B, 123
+ ret i1 %C
+}
+
+define i1 @test19(i32 %A) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 %A, 4
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %B = ashr i32 %A, 2
+ ;; (X & -4) == 0
+ %C = icmp eq i32 %B, 0
+ ret i1 %C
+}
+
+define <2 x i1> @test19vec(<2 x i32> %A) {
+; CHECK-LABEL: @test19vec(
+; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i32> %A, <i32 4, i32 4>
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %B = ashr <2 x i32> %A, <i32 2, i32 2>
+ %C = icmp eq <2 x i32> %B, zeroinitializer
+ ret <2 x i1> %C
+}
+
+;; X >u ~4
+define i1 @test19a(i32 %A) {
+; CHECK-LABEL: @test19a(
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %A, -5
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %B = ashr i32 %A, 2
+ %C = icmp eq i32 %B, -1
+ ret i1 %C
+}
+
+define <2 x i1> @test19a_vec(<2 x i32> %A) {
+; CHECK-LABEL: @test19a_vec(
+; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> %A, <i32 -5, i32 -5>
+; CHECK-NEXT: ret <2 x i1> [[C]]
+;
+ %B = ashr <2 x i32> %A, <i32 2, i32 2>
+ %C = icmp eq <2 x i32> %B, <i32 -1, i32 -1>
+ ret <2 x i1> %C
+}
+
+define i1 @test20(i8 %A) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT: ret i1 false
+;
+ %B = ashr i8 %A, 7
+ ;; false
+ %C = icmp eq i8 %B, 123
+ ret i1 %C
+}
+
+define i1 @test21(i8 %A) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15
+; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 8
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %B = shl i8 %A, 4
+ %C = icmp eq i8 %B, -128
+ ret i1 %C
+}
+
+define i1 @test22(i8 %A) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15
+; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 0
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %B = shl i8 %A, 4
+ %C = icmp eq i8 %B, 0
+ ret i1 %C
+}
+
+define i8 @test23(i32 %A) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT: [[D:%.*]] = trunc i32 %A to i8
+; CHECK-NEXT: ret i8 [[D]]
+;
+ ;; casts not needed
+ %B = shl i32 %A, 24
+ %C = ashr i32 %B, 24
+ %D = trunc i32 %C to i8
+ ret i8 %D
+}
+
+define i8 @test24(i8 %X) {
+; CHECK-LABEL: @test24(
+; CHECK-NEXT: [[Z:%.*]] = and i8 %X, 3
+; CHECK-NEXT: ret i8 [[Z]]
+;
+ %Y = and i8 %X, -5
+ %Z = shl i8 %Y, 5
+ %Q = ashr i8 %Z, 5
+ ret i8 %Q
+}
+
+define i32 @test25(i32 %tmp.2, i32 %AA) {
+; CHECK-LABEL: @test25(
+; CHECK-NEXT: [[TMP_3:%.*]] = and i32 %tmp.2, -131072
+; CHECK-NEXT: [[X2:%.*]] = add i32 [[TMP_3]], %AA
+; CHECK-NEXT: [[TMP_6:%.*]] = and i32 [[X2]], -131072
+; CHECK-NEXT: ret i32 [[TMP_6]]
+;
+ %x = lshr i32 %AA, 17
+ %tmp.3 = lshr i32 %tmp.2, 17
+ %tmp.5 = add i32 %tmp.3, %x
+ %tmp.6 = shl i32 %tmp.5, 17
+ ret i32 %tmp.6
+}
+
+define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) {
+; CHECK-LABEL: @test25_vector(
+; CHECK-NEXT: [[TMP_3:%.*]] = and <2 x i32> %tmp.2, <i32 -131072, i32 -131072>
+; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[TMP_3]], %AA
+; CHECK-NEXT: [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072>
+; CHECK-NEXT: ret <2 x i32> [[TMP_6]]
+;
+ %x = lshr <2 x i32> %AA, <i32 17, i32 17>
+ %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17>
+ %tmp.5 = add <2 x i32> %tmp.3, %x
+ %tmp.6 = shl <2 x i32> %tmp.5, <i32 17, i32 17>
+ ret <2 x i32> %tmp.6
+}
+
+;; handle casts between shifts.
+define i32 @test26(i32 %A) {
+; CHECK-LABEL: @test26(
+; CHECK-NEXT: [[B:%.*]] = and i32 %A, -2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %B = lshr i32 %A, 1
+ %C = bitcast i32 %B to i32
+ %D = shl i32 %C, 1
+ ret i32 %D
+}
+
+
+define i1 @test27(i32 %x) nounwind {
+; CHECK-LABEL: @test27(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 8
+; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[Z]]
+;
+ %y = lshr i32 %x, 3
+ %z = trunc i32 %y to i1
+ ret i1 %z
+}
+
+define i1 @test28(i8 %x) {
+; CHECK-LABEL: @test28(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 %x, 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %shr = lshr i8 %x, 7
+ %cmp = icmp ne i8 %shr, 0
+ ret i1 %cmp
+}
+
+define <2 x i1> @test28vec(<2 x i8> %x) {
+; CHECK-LABEL: @test28vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> %x, zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[CMP]]
+;
+ %shr = lshr <2 x i8> %x, <i8 7, i8 7>
+ %cmp = icmp ne <2 x i8> %shr, zeroinitializer
+ ret <2 x i1> %cmp
+}
+
+define i8 @test28a(i8 %x, i8 %y) {
+; CHECK-LABEL: @test28a(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 %x, 7
+; CHECK-NEXT: [[COND1:%.*]] = icmp eq i8 [[TMP1]], 0
+; CHECK-NEXT: br i1 [[COND1]], label %bb2, label %bb1
+; CHECK: bb1:
+; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK: bb2:
+; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], %y
+; CHECK-NEXT: ret i8 [[TMP2]]
+;
+entry:
+; This shouldn't be transformed.
+ %tmp1 = lshr i8 %x, 7
+ %cond1 = icmp ne i8 %tmp1, 0
+ br i1 %cond1, label %bb1, label %bb2
+bb1:
+ ret i8 %tmp1
+bb2:
+ %tmp2 = add i8 %tmp1, %y
+ ret i8 %tmp2
+}
+
+
+define i32 @test29(i64 %d18) {
+; CHECK-LABEL: @test29(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP916:%.*]] = lshr i64 %d18, 63
+; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP916]] to i32
+; CHECK-NEXT: ret i32 [[TMP10]]
+;
+entry:
+ %tmp916 = lshr i64 %d18, 32
+ %tmp917 = trunc i64 %tmp916 to i32
+ %tmp10 = lshr i32 %tmp917, 31
+ ret i32 %tmp10
+}
+
+
+define i32 @test30(i32 %A, i32 %B, i32 %C) {
+; CHECK-LABEL: @test30(
+; CHECK-NEXT: [[X1:%.*]] = and i32 %A, %B
+; CHECK-NEXT: [[Z:%.*]] = shl i32 [[X1]], %C
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %X = shl i32 %A, %C
+ %Y = shl i32 %B, %C
+ %Z = and i32 %X, %Y
+ ret i32 %Z
+}
+
+define i32 @test31(i32 %A, i32 %B, i32 %C) {
+; CHECK-LABEL: @test31(
+; CHECK-NEXT: [[X1:%.*]] = or i32 %A, %B
+; CHECK-NEXT: [[Z:%.*]] = lshr i32 [[X1]], %C
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %X = lshr i32 %A, %C
+ %Y = lshr i32 %B, %C
+ %Z = or i32 %X, %Y
+ ret i32 %Z
+}
+
+define i32 @test32(i32 %A, i32 %B, i32 %C) {
+; CHECK-LABEL: @test32(
+; CHECK-NEXT: [[X1:%.*]] = xor i32 %A, %B
+; CHECK-NEXT: [[Z:%.*]] = ashr i32 [[X1]], %C
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %X = ashr i32 %A, %C
+ %Y = ashr i32 %B, %C
+ %Z = xor i32 %X, %Y
+ ret i32 %Z
+}
+
+define i1 @test33(i32 %X) {
+; CHECK-LABEL: @test33(
+; CHECK-NEXT: [[TMP1_MASK:%.*]] = and i32 %X, 16777216
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1_MASK]], 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %tmp1 = shl i32 %X, 7
+ %tmp2 = icmp slt i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define <2 x i1> @test33vec(<2 x i32> %X) {
+; CHECK-LABEL: @test33vec(
+; CHECK-NEXT: [[TMP1_MASK:%.*]] = and <2 x i32> %X, <i32 16777216, i32 16777216>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1_MASK]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+;
+ %tmp1 = shl <2 x i32> %X, <i32 7, i32 7>
+ %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer
+ ret <2 x i1> %tmp2
+}
+
+define i1 @test34(i32 %X) {
+; CHECK-LABEL: @test34(
+; CHECK-NEXT: ret i1 false
+;
+ %tmp1 = lshr i32 %X, 7
+ %tmp2 = icmp slt i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define i1 @test35(i32 %X) {
+; CHECK-LABEL: @test35(
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 %X, 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %tmp1 = ashr i32 %X, 7
+ %tmp2 = icmp slt i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define <2 x i1> @test35vec(<2 x i32> %X) {
+; CHECK-LABEL: @test35vec(
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> %X, zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+;
+ %tmp1 = ashr <2 x i32> %X, <i32 7, i32 7>
+ %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer
+ ret <2 x i1> %tmp2
+}
+
+define i128 @test36(i128 %A, i128 %B) {
+; CHECK-LABEL: @test36(
+; CHECK-NEXT: [[TMP231:%.*]] = or i128 %B, %A
+; CHECK-NEXT: [[INS:%.*]] = and i128 [[TMP231]], 18446744073709551615
+; CHECK-NEXT: ret i128 [[INS]]
+;
+ %tmp27 = shl i128 %A, 64
+ %tmp23 = shl i128 %B, 64
+ %ins = or i128 %tmp23, %tmp27
+ %tmp45 = lshr i128 %ins, 64
+ ret i128 %tmp45
+}
+
+define i64 @test37(i128 %A, i32 %B) {
+; CHECK-LABEL: @test37(
+; CHECK-NEXT: [[TMP22:%.*]] = zext i32 %B to i128
+; CHECK-NEXT: [[TMP23:%.*]] = shl nuw nsw i128 [[TMP22]], 32
+; CHECK-NEXT: [[INS:%.*]] = or i128 [[TMP23]], %A
+; CHECK-NEXT: [[TMP46:%.*]] = trunc i128 [[INS]] to i64
+; CHECK-NEXT: ret i64 [[TMP46]]
+;
+ %tmp27 = shl i128 %A, 64
+ %tmp22 = zext i32 %B to i128
+ %tmp23 = shl i128 %tmp22, 96
+ %ins = or i128 %tmp23, %tmp27
+ %tmp45 = lshr i128 %ins, 64
+ %tmp46 = trunc i128 %tmp45 to i64
+ ret i64 %tmp46
+}
+
+define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) {
+; CHECK-LABEL: @shl_nuw_nsw_splat_vec(
+; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> %x to <2 x i32>
+; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17>
+; CHECK-NEXT: ret <2 x i32> [[T3]]
+;
+ %t2 = zext <2 x i8> %x to <2 x i32>
+ %t3 = shl <2 x i32> %t2, <i32 17, i32 17>
+ ret <2 x i32> %t3
+}
+
+define i32 @test38(i32 %x) nounwind readnone {
+; CHECK-LABEL: @test38(
+; CHECK-NEXT: [[REM1:%.*]] = and i32 %x, 31
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]]
+; CHECK-NEXT: ret i32 [[SHL]]
+;
+ %rem = srem i32 %x, 32
+ %shl = shl i32 1, %rem
+ ret i32 %shl
+}
+
+; <rdar://problem/8756731>
+define i8 @test39(i32 %a0) {
+; CHECK-LABEL: @test39(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 %a0 to i8
+; CHECK-NEXT: [[TMP5:%.*]] = shl i8 [[TMP4]], 5
+; CHECK-NEXT: [[TMP49:%.*]] = shl i8 [[TMP4]], 6
+; CHECK-NEXT: [[TMP50:%.*]] = and i8 [[TMP49]], 64
+; CHECK-NEXT: [[TMP51:%.*]] = xor i8 [[TMP50]], [[TMP5]]
+; CHECK-NEXT: [[TMP0:%.*]] = shl i8 [[TMP4]], 2
+; CHECK-NEXT: [[TMP54:%.*]] = and i8 [[TMP0]], 16
+; CHECK-NEXT: [[TMP551:%.*]] = or i8 [[TMP54]], [[TMP51]]
+; CHECK-NEXT: ret i8 [[TMP551]]
+;
+entry:
+ %tmp4 = trunc i32 %a0 to i8
+ %tmp5 = shl i8 %tmp4, 5
+ %tmp48 = and i8 %tmp5, 32
+ %tmp49 = lshr i8 %tmp48, 5
+ %tmp50 = mul i8 %tmp49, 64
+ %tmp51 = xor i8 %tmp50, %tmp5
+ %tmp52 = and i8 %tmp51, -128
+ %tmp53 = lshr i8 %tmp52, 7
+ %tmp54 = mul i8 %tmp53, 16
+ %tmp55 = xor i8 %tmp54, %tmp51
+ ret i8 %tmp55
+}
+
+; PR9809
+define i32 @test40(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: @test40(
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 2
+; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, [[TMP1]]
+; CHECK-NEXT: ret i32 [[DIV]]
+;
+ %shl1 = shl i32 1, %b
+ %shl2 = shl i32 %shl1, 2
+ %div = udiv i32 %a, %shl2
+ ret i32 %div
+}
+
+define i32 @test41(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: @test41(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 8, %b
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %1 = shl i32 1, %b
+ %2 = shl i32 %1, 3
+ ret i32 %2
+}
+
+define i32 @test42(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: @test42(
+; CHECK-NEXT: [[DIV:%.*]] = lshr exact i32 4096, %b
+; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]]
+; CHECK-NEXT: ret i32 [[DIV2]]
+;
+ %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero
+ %div2 = udiv i32 %a, %div
+ ret i32 %div2
+}
+
+define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: @test42vec(
+; CHECK-NEXT: [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, %b
+; CHECK-NEXT: [[DIV2:%.*]] = udiv <2 x i32> %a, [[DIV]]
+; CHECK-NEXT: ret <2 x i32> [[DIV2]]
+;
+ %div = lshr <2 x i32> <i32 4096, i32 4096>, %b ; must be exact otherwise we'd divide by zero
+ %div2 = udiv <2 x i32> %a, %div
+ ret <2 x i32> %div2
+}
+
+define i32 @test43(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: @test43(
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 12
+; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]]
+; CHECK-NEXT: ret i32 [[DIV2]]
+;
+ %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero
+ %div2 = udiv i32 %a, %div
+ ret i32 %div2
+}
+
+define i32 @test44(i32 %a) nounwind {
+; CHECK-LABEL: @test44(
+; CHECK-NEXT: [[Y:%.*]] = shl i32 %a, 5
+; CHECK-NEXT: ret i32 [[Y]]
+;
+ %y = shl nuw i32 %a, 1
+ %z = shl i32 %y, 4
+ ret i32 %z
+}
+
+define i32 @test45(i32 %a) nounwind {
+; CHECK-LABEL: @test45(
+; CHECK-NEXT: [[Y:%.*]] = lshr i32 %a, 5
+; CHECK-NEXT: ret i32 [[Y]]
+;
+ %y = lshr exact i32 %a, 1
+ %z = lshr i32 %y, 4
+ ret i32 %z
+}
+
+; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
+
+define i32 @test46(i32 %a) {
+; CHECK-LABEL: @test46(
+; CHECK-NEXT: [[Z:%.*]] = ashr exact i32 %a, 2
+; CHECK-NEXT: ret i32 [[Z]]
+;
+ %y = ashr exact i32 %a, 3
+ %z = shl i32 %y, 1
+ ret i32 %z
+}
+
+; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
+
+define <2 x i32> @test46_splat_vec(<2 x i32> %a) {
+; CHECK-LABEL: @test46_splat_vec(
+; CHECK-NEXT: [[Z:%.*]] = ashr exact <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i32> [[Z]]
+;
+ %y = ashr exact <2 x i32> %a, <i32 3, i32 3>
+ %z = shl <2 x i32> %y, <i32 1, i32 1>
+ ret <2 x i32> %z
+}
+
+; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
+
+define i8 @test47(i8 %a) {
+; CHECK-LABEL: @test47(
+; CHECK-NEXT: [[Z:%.*]] = lshr exact i8 %a, 2
+; CHECK-NEXT: ret i8 [[Z]]
+;
+ %y = lshr exact i8 %a, 3
+ %z = shl i8 %y, 1
+ ret i8 %z
+}
+
+; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
+
+define <2 x i8> @test47_splat_vec(<2 x i8> %a) {
+; CHECK-LABEL: @test47_splat_vec(
+; CHECK-NEXT: [[Z:%.*]] = lshr exact <2 x i8> %a, <i8 2, i8 2>
+; CHECK-NEXT: ret <2 x i8> [[Z]]
+;
+ %y = lshr exact <2 x i8> %a, <i8 3, i8 3>
+ %z = shl <2 x i8> %y, <i8 1, i8 1>
+ ret <2 x i8> %z
+}
+
+; (X >>u,exact C1) << C2 --> X << (C2-C1) when C2 > C1
+
+define i32 @test48(i32 %x) {
+; CHECK-LABEL: @test48(
+; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = lshr exact i32 %x, 1
+ %B = shl i32 %A, 3
+ ret i32 %B
+}
+
+; Verify that wrap flags are preserved from the original 'shl'.
+
+define i32 @test48_nuw_nsw(i32 %x) {
+; CHECK-LABEL: @test48_nuw_nsw(
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = lshr exact i32 %x, 1
+ %B = shl nuw nsw i32 %A, 3
+ ret i32 %B
+}
+
+; (X >>u,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1
+
+define <2 x i32> @test48_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test48_splat_vec(
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = lshr exact <2 x i32> %x, <i32 1, i32 1>
+ %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3>
+ ret <2 x i32> %B
+}
+
+; (X >>s,exact C1) << C2 --> X << (C2-C1) when C2 > C1
+
+define i32 @test49(i32 %x) {
+; CHECK-LABEL: @test49(
+; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = ashr exact i32 %x, 1
+ %B = shl i32 %A, 3
+ ret i32 %B
+}
+
+; Verify that wrap flags are preserved from the original 'shl'.
+
+define i32 @test49_nuw_nsw(i32 %x) {
+; CHECK-LABEL: @test49_nuw_nsw(
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = ashr exact i32 %x, 1
+ %B = shl nuw nsw i32 %A, 3
+ ret i32 %B
+}
+
+; (X >>s,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1
+
+define <2 x i32> @test49_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test49_splat_vec(
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = ashr exact <2 x i32> %x, <i32 1, i32 1>
+ %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3>
+ ret <2 x i32> %B
+}
+
+; (X <<nsw C1) >>s C2 --> X >>s (C2-C1)
+
+define i32 @test50(i32 %x) {
+; CHECK-LABEL: @test50(
+; CHECK-NEXT: [[B:%.*]] = ashr i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = shl nsw i32 %x, 1
+ %B = ashr i32 %A, 3
+ ret i32 %B
+}
+
+; (X <<nsw C1) >>s C2 --> X >>s (C2-C1)
+; Also, check that exact is propagated.
+
+define <2 x i32> @test50_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test50_splat_vec(
+; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = shl nsw <2 x i32> %x, <i32 1, i32 1>
+ %B = ashr exact <2 x i32> %A, <i32 3, i32 3>
+ ret <2 x i32> %B
+}
+
+; (X <<nuw C1) >>u C2 --> X >>u (C2-C1)
+
+define i32 @test51(i32 %x) {
+; CHECK-LABEL: @test51(
+; CHECK-NEXT: [[B:%.*]] = lshr i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = shl nuw i32 %x, 1
+ %B = lshr i32 %A, 3
+ ret i32 %B
+}
+
+; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) with splats
+; Also, check that exact is propagated.
+
+define <2 x i32> @test51_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test51_splat_vec(
+; CHECK-NEXT: [[B:%.*]] = lshr exact <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = shl nuw <2 x i32> %x, <i32 1, i32 1>
+ %B = lshr exact <2 x i32> %A, <i32 3, i32 3>
+ ret <2 x i32> %B
+}
+
+; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2)
+; Also, check that exact is propagated.
+
+define i32 @test51_no_nuw(i32 %x) {
+; CHECK-LABEL: @test51_no_nuw(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 %x, 2
+; CHECK-NEXT: [[B:%.*]] = and i32 [[TMP1]], 536870911
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = shl i32 %x, 1
+ %B = lshr exact i32 %A, 3
+ ret i32 %B
+}
+
+; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2)
+
+define <2 x i32> @test51_no_nuw_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test51_no_nuw_splat_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[TMP1]], <i32 536870911, i32 536870911>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = shl <2 x i32> %x, <i32 1, i32 1>
+ %B = lshr <2 x i32> %A, <i32 3, i32 3>
+ ret <2 x i32> %B
+}
+
+; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2)
+
+define i32 @test52(i32 %x) {
+; CHECK-LABEL: @test52(
+; CHECK-NEXT: [[B:%.*]] = shl nsw i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = shl nsw i32 %x, 3
+ %B = ashr i32 %A, 1
+ ret i32 %B
+}
+
+; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2)
+
+define <2 x i32> @test52_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test52_splat_vec(
+; CHECK-NEXT: [[B:%.*]] = shl nsw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = shl nsw <2 x i32> %x, <i32 3, i32 3>
+ %B = ashr <2 x i32> %A, <i32 1, i32 1>
+ ret <2 x i32> %B
+}
+
+; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2)
+
+define i32 @test53(i32 %x) {
+; CHECK-LABEL: @test53(
+; CHECK-NEXT: [[B:%.*]] = shl nuw i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = shl nuw i32 %x, 3
+ %B = lshr i32 %A, 1
+ ret i32 %B
+}
+
+; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2)
+
+define <2 x i32> @test53_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test53_splat_vec(
+; CHECK-NEXT: [[B:%.*]] = shl nuw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = shl nuw <2 x i32> %x, <i32 3, i32 3>
+ %B = lshr <2 x i32> %A, <i32 1, i32 1>
+ ret <2 x i32> %B
+}
+
+; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2)
+
+define i8 @test53_no_nuw(i8 %x) {
+; CHECK-LABEL: @test53_no_nuw(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i8 %x, 2
+; CHECK-NEXT: [[B:%.*]] = and i8 [[TMP1]], 124
+; CHECK-NEXT: ret i8 [[B]]
+;
+ %A = shl i8 %x, 3
+ %B = lshr i8 %A, 1
+ ret i8 %B
+}
+
+; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2)
+
+define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) {
+; CHECK-LABEL: @test53_no_nuw_splat_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> %x, <i8 2, i8 2>
+; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 124, i8 124>
+; CHECK-NEXT: ret <2 x i8> [[B]]
+;
+ %A = shl <2 x i8> %x, <i8 3, i8 3>
+ %B = lshr <2 x i8> %A, <i8 1, i8 1>
+ ret <2 x i8> %B
+}
+
+define i32 @test54(i32 %x) {
+; CHECK-LABEL: @test54(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 16
+; CHECK-NEXT: ret i32 [[AND]]
+;
+ %shr2 = lshr i32 %x, 1
+ %shl = shl i32 %shr2, 4
+ %and = and i32 %shl, 16
+ ret i32 %and
+}
+
+define <2 x i32> @test54_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test54_splat_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> %x, <i32 3, i32 3>
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[TMP1]], <i32 16, i32 16>
+; CHECK-NEXT: ret <2 x i32> [[AND]]
+;
+ %shr2 = lshr <2 x i32> %x, <i32 1, i32 1>
+ %shl = shl <2 x i32> %shr2, <i32 4, i32 4>
+ %and = and <2 x i32> %shl, <i32 16, i32 16>
+ ret <2 x i32> %and
+}
+
+define i32 @test55(i32 %x) {
+; CHECK-LABEL: @test55(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 8
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %shr2 = lshr i32 %x, 1
+ %shl = shl i32 %shr2, 4
+ %or = or i32 %shl, 8
+ ret i32 %or
+}
+
+define i32 @test56(i32 %x) {
+; CHECK-LABEL: @test56(
+; CHECK-NEXT: [[SHR2:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR2]], 4
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %shr2 = lshr i32 %x, 1
+ %shl = shl i32 %shr2, 4
+ %or = or i32 %shl, 7
+ ret i32 %or
+}
+
+define i32 @test57(i32 %x) {
+; CHECK-LABEL: @test57(
+; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR1]], 4
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %shr = ashr i32 %x, 1
+ %shl = shl i32 %shr, 4
+ %or = or i32 %shl, 7
+ ret i32 %or
+}
+
+define i32 @test58(i32 %x) {
+; CHECK-LABEL: @test58(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 %x, 3
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 1
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %shr = ashr i32 %x, 4
+ %shl = shl i32 %shr, 1
+ %or = or i32 %shl, 1
+ ret i32 %or
+}
+
+define <2 x i32> @test58_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test58_splat_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> %x, <i32 3, i32 3>
+; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[OR]]
+;
+ %shr = ashr <2 x i32> %x, <i32 4, i32 4>
+ %shl = shl <2 x i32> %shr, <i32 1, i32 1>
+ %or = or <2 x i32> %shl, <i32 1, i32 1>
+ ret <2 x i32> %or
+}
+
+define i32 @test59(i32 %x) {
+; CHECK-LABEL: @test59(
+; CHECK-NEXT: [[SHR:%.*]] = ashr i32 %x, 4
+; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SHR]], 1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 2
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %shr = ashr i32 %x, 4
+ %shl = shl i32 %shr, 1
+ %or = or i32 %shl, 2
+ ret i32 %or
+}
+
+; propagate "exact" trait
+define i32 @test60(i32 %x) {
+; CHECK-LABEL: @test60(
+; CHECK-NEXT: [[SHL:%.*]] = ashr exact i32 %x, 3
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 1
+; CHECK-NEXT: ret i32 [[OR]]
+;
+ %shr = ashr exact i32 %x, 4
+ %shl = shl i32 %shr, 1
+ %or = or i32 %shl, 1
+ ret i32 %or
+}
+
+; PR17026
+define void @test61(i128 %arg) {
+; CHECK-LABEL: @test61(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: br i1 undef, label %bb1, label %bb12
+; CHECK: bb1:
+; CHECK-NEXT: br label %bb2
+; CHECK: bb2:
+; CHECK-NEXT: br i1 undef, label %bb3, label %bb7
+; CHECK: bb3:
+; CHECK-NEXT: br label %bb8
+; CHECK: bb7:
+; CHECK-NEXT: br i1 undef, label %bb8, label %bb2
+; CHECK: bb8:
+; CHECK-NEXT: br i1 undef, label %bb11, label %bb12
+; CHECK: bb11:
+; CHECK-NEXT: br i1 undef, label %bb1, label %bb12
+; CHECK: bb12:
+; CHECK-NEXT: ret void
+;
+bb:
+ br i1 undef, label %bb1, label %bb12
+
+bb1: ; preds = %bb11, %bb
+ br label %bb2
+
+bb2: ; preds = %bb7, %bb1
+ br i1 undef, label %bb3, label %bb7
+
+bb3: ; preds = %bb2
+ %tmp = lshr i128 %arg, 36893488147419103232
+ %tmp4 = shl i128 %tmp, 0
+ %tmp5 = or i128 %tmp4, undef
+ %tmp6 = trunc i128 %tmp5 to i16
+ br label %bb8
+
+bb7: ; preds = %bb2
+ br i1 undef, label %bb8, label %bb2
+
+bb8: ; preds = %bb7, %bb3
+ %tmp9 = phi i16 [ %tmp6, %bb3 ], [ undef, %bb7 ]
+ %tmp10 = icmp eq i16 %tmp9, 0
+ br i1 %tmp10, label %bb11, label %bb12
+
+bb11: ; preds = %bb8
+ br i1 undef, label %bb1, label %bb12
+
+bb12: ; preds = %bb11, %bb8, %bb
+ ret void
+}
+
+define i32 @test62(i32 %a) {
+; CHECK-LABEL: @test62(
+; CHECK-NEXT: ret i32 undef
+;
+ %b = ashr i32 %a, 32 ; shift all bits out
+ ret i32 %b
+}
+
+define <4 x i32> @test62_splat_vector(<4 x i32> %a) {
+; CHECK-LABEL: @test62_splat_vector(
+; CHECK-NEXT: ret <4 x i32> undef
+;
+ %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out
+ ret <4 x i32> %b
+}
+
+define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) {
+; CHECK-LABEL: @test62_non_splat_vector(
+; CHECK-NEXT: [[B:%.*]] = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2>
+; CHECK-NEXT: ret <4 x i32> [[B]]
+;
+ %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out
+ ret <4 x i32> %b
+}
+
+define <2 x i65> @test_63(<2 x i64> %t) {
+; CHECK-LABEL: @test_63(
+; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> %t to <2 x i65>
+; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33>
+; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i65> [[SEXT]], <i65 33, i65 33>
+; CHECK-NEXT: ret <2 x i65> [[B]]
+;
+ %a = zext <2 x i64> %t to <2 x i65>
+ %sext = shl <2 x i65> %a, <i65 33, i65 33>
+ %b = ashr <2 x i65> %sext, <i65 33, i65 33>
+ ret <2 x i65> %b
+}
+
+define i64 @test_64(i32 %t) {
+; CHECK-LABEL: @test_64(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %t, 8
+; CHECK-NEXT: [[SHL:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[SHL]]
+;
+ %and = and i32 %t, 16777215
+ %ext = zext i32 %and to i64
+ %shl = shl i64 %ext, 8
+ ret i64 %shl
+}
+
+define <2 x i64> @test_64_splat_vec(<2 x i32> %t) {
+; CHECK-LABEL: @test_64_splat_vec(
+; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> %t, <i32 8, i32 8>
+; CHECK-NEXT: [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[SHL]]
+;
+ %and = and <2 x i32> %t, <i32 16777215, i32 16777215>
+ %ext = zext <2 x i32> %and to <2 x i64>
+ %shl = shl <2 x i64> %ext, <i64 8, i64 8>
+ ret <2 x i64> %shl
+}
+
+define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) {
+; CHECK-LABEL: @ashr_demanded_bits_splat(
+; CHECK-NEXT: [[SHR:%.*]] = ashr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT: ret <2 x i8> [[SHR]]
+;
+ %and = and <2 x i8> %x, <i8 128, i8 128>
+ %shr = ashr <2 x i8> %and, <i8 7, i8 7>
+ ret <2 x i8> %shr
+}
+
+define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_demanded_bits_splat(
+; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT: ret <2 x i8> [[SHR]]
+;
+ %and = and <2 x i8> %x, <i8 128, i8 128>
+ %shr = lshr <2 x i8> %and, <i8 7, i8 7>
+ ret <2 x i8> %shr
+}
+
+; Make sure known bits works correctly with non power of 2 bit widths.
+define i7 @test65(i7 %a, i7 %b) {
+; CHECK-LABEL: @test65(
+; CHECK-NEXT: ret i7 0
+;
+ %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width.
+ %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit.
+ %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0.
+ ret i7 %y
+}
+
+define i32 @shl_select_add_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_add_true(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = add i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @shl_select_add_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_add_false(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = add i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @shl_select_and_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_and_true(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @shl_select_and_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_and_false(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @lshr_select_and_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @lshr_select_and_true(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = lshr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @lshr_select_and_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @lshr_select_and_false(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = lshr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @ashr_select_and_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @ashr_select_and_true(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 2147483655
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = ashr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @ashr_select_and_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @ashr_select_and_false(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = and i32 %x, 2147483655
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = ashr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @shl_select_or_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_or_true(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = or i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @shl_select_or_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_or_false(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = or i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @lshr_select_or_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @lshr_select_or_true(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = or i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = lshr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @lshr_select_or_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @lshr_select_or_false(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = or i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = lshr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @ashr_select_or_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @ashr_select_or_true(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = or i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = ashr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @ashr_select_or_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @ashr_select_or_false(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = or i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = ashr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @shl_select_xor_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_xor_true(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = xor i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @shl_select_xor_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @shl_select_xor_false(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = xor i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = shl i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @lshr_select_xor_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @lshr_select_xor_true(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = xor i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = lshr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @lshr_select_xor_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @lshr_select_xor_false(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = xor i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = lshr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @ashr_select_xor_true(i32 %x, i1 %cond) {
+; CHECK-LABEL: @ashr_select_xor_true(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = xor i32 %x, 7
+ %2 = select i1 %cond, i32 %1, i32 %x
+ %3 = ashr i32 %2, 1
+ ret i32 %3
+}
+
+define i32 @ashr_select_xor_false(i32 %x, i1 %cond) {
+; CHECK-LABEL: @ashr_select_xor_false(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
+; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = xor i32 %x, 7
+ %2 = select i1 %cond, i32 %x, i32 %1
+ %3 = ashr i32 %2, 1
+ ret i32 %3
+}
+
+; OSS Fuzz #4871
+; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4871
+define i177 @lshr_out_of_range(i177 %Y, i177** %A2) {
+; CHECK-LABEL: @lshr_out_of_range(
+; CHECK-NEXT: store i177** [[A2:%.*]], i177*** undef, align 8
+; CHECK-NEXT: ret i177 0
+;
+ %B5 = udiv i177 %Y, -1
+ %B4 = add i177 %B5, -1
+ %B2 = add i177 %B4, -1
+ %B6 = mul i177 %B5, %B2
+ %B3 = add i177 %B2, %B2
+ %B10 = sub i177 %B5, %B3
+ %B12 = lshr i177 %Y, %B6
+ %C8 = icmp ugt i177 %B12, %B4
+ %G18 = getelementptr i177*, i177** %A2, i1 %C8
+ store i177** %G18, i177*** undef
+ %B1 = udiv i177 %B10, %B6
+ ret i177 %B1
+}
+
+; OSS Fuzz #5032
+; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5032
+define void @ashr_out_of_range(i177* %A) {
+; CHECK-LABEL: @ashr_out_of_range(
+; CHECK-NEXT: ret void
+;
+ %L = load i177, i177* %A
+ %B5 = udiv i177 %L, -1
+ %B4 = add i177 %B5, -1
+ %B2 = add i177 %B4, -1
+ %G11 = getelementptr i177, i177* %A, i177 %B2
+ %L7 = load i177, i177* %G11
+ %B6 = mul i177 %B5, %B2
+ %B24 = ashr i177 %L7, %B6
+ %B36 = and i177 %L7, %B4
+ %C17 = icmp sgt i177 %B36, %B24
+ %G62 = getelementptr i177, i177* %G11, i1 %C17
+ %B28 = urem i177 %B24, %B6
+ store i177 %B28, i177* %G62
+ ret void
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/should-change-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/should-change-type.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/should-change-type.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/should-change-type.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "n64"
+
+; Tests for removing zext/trunc from/to i8, i16 and i32, even if it is
+; not a legal type.
+
+define i8 @test1(i8 %x, i8 %y) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[C:%.*]] = add i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %xz = zext i8 %x to i64
+ %yz = zext i8 %y to i64
+ %c = add i64 %xz, %yz
+ %d = trunc i64 %c to i8
+ ret i8 %d
+}
+
+define i16 @test2(i16 %x, i16 %y) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[C:%.*]] = add i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i16 [[C]]
+;
+ %xz = zext i16 %x to i64
+ %yz = zext i16 %y to i64
+ %c = add i64 %xz, %yz
+ %d = trunc i64 %c to i16
+ ret i16 %d
+}
+
+define i32 @test3(i32 %x, i32 %y) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[C:%.*]] = add i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %xz = zext i32 %x to i64
+ %yz = zext i32 %y to i64
+ %c = add i64 %xz, %yz
+ %d = trunc i64 %c to i32
+ ret i32 %d
+}
+
+define i9 @test4(i9 %x, i9 %y) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[XZ:%.*]] = zext i9 [[X:%.*]] to i64
+; CHECK-NEXT: [[YZ:%.*]] = zext i9 [[Y:%.*]] to i64
+; CHECK-NEXT: [[C:%.*]] = add nuw nsw i64 [[XZ]], [[YZ]]
+; CHECK-NEXT: [[D:%.*]] = trunc i64 [[C]] to i9
+; CHECK-NEXT: ret i9 [[D]]
+;
+ %xz = zext i9 %x to i64
+ %yz = zext i9 %y to i64
+ %c = add i64 %xz, %yz
+ %d = trunc i64 %c to i9
+ ret i9 %d
+}
Added: llvm/trunk/test/Transforms/InstCombine/shuffle-select-narrow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shuffle-select-narrow.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shuffle-select-narrow.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shuffle-select-narrow.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,144 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Narrow the select operands to eliminate the existing shuffles and replace a wide select with a narrow select.
+
+define <2 x i8> @narrow_shuffle_of_select(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[TMP2]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
+ %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x i8> %r
+}
+
+; The 1st shuffle is not extending with undefs, but demanded elements corrects that.
+
+define <2 x i8> @narrow_shuffle_of_select_overspecified_extend(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select_overspecified_extend(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[TMP2]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+ %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
+ %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x i8> %r
+}
+
+; Verify that undef elements are acceptable for identity shuffle mask. Also check FP types.
+
+define <3 x float> @narrow_shuffle_of_select_undefs(<3 x i1> %cmp, <4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select_undefs(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[Y:%.*]], <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+; CHECK-NEXT: [[R:%.*]] = select <3 x i1> [[CMP:%.*]], <3 x float> [[TMP1]], <3 x float> [[TMP2]]
+; CHECK-NEXT: ret <3 x float> [[R]]
+;
+ %widecmp = shufflevector <3 x i1> %cmp, <3 x i1> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 undef>
+ %widesel = select <4 x i1> %widecmp, <4 x float> %x, <4 x float> %y
+ %r = shufflevector <4 x float> %widesel, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+ ret <3 x float> %r
+}
+
+declare void @use(<4 x i8>)
+declare void @use_cmp(<4 x i1>)
+
+; Negative test - extra use would require more instructions than we started with.
+
+define <2 x i8> @narrow_shuffle_of_select_use1(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select_use1(
+; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]]
+; CHECK-NEXT: call void @use(<4 x i8> [[WIDESEL]])
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
+ call void @use(<4 x i8> %widesel)
+ %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x i8> %r
+}
+
+; Negative test - extra use would require more instructions than we started with.
+
+define <2 x i8> @narrow_shuffle_of_select_use2(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select_use2(
+; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT: call void @use_cmp(<4 x i1> [[WIDECMP]])
+; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ call void @use_cmp(<4 x i1> %widecmp)
+ %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
+ %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x i8> %r
+}
+
+; Negative test - mismatched types would require extra shuffling.
+
+define <3 x i8> @narrow_shuffle_of_select_mismatch_types1(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select_mismatch_types1(
+; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: ret <3 x i8> [[R]]
+;
+ %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
+ %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+ ret <3 x i8> %r
+}
+
+; Negative test - mismatched types would require extra shuffling.
+
+define <3 x i8> @narrow_shuffle_of_select_mismatch_types2(<4 x i1> %cmp, <6 x i8> %x, <6 x i8> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select_mismatch_types2(
+; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <6 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: [[WIDESEL:%.*]] = select <6 x i1> [[WIDECMP]], <6 x i8> [[X:%.*]], <6 x i8> [[Y:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <6 x i8> [[WIDESEL]], <6 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: ret <3 x i8> [[R]]
+;
+ %widecmp = shufflevector <4 x i1> %cmp, <4 x i1> undef, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef>
+ %widesel = select <6 x i1> %widecmp, <6 x i8> %x, <6 x i8> %y
+ %r = shufflevector <6 x i8> %widesel, <6 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
+ ret <3 x i8> %r
+}
+
+; Narrowing constants does not require creating new narrowing shuffle instructions.
+
+define <2 x i8> @narrow_shuffle_of_select_consts(<2 x i1> %cmp) {
+; CHECK-LABEL: @narrow_shuffle_of_select_consts(
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i8> <i8 -1, i8 -2>, <2 x i8> <i8 1, i8 2>
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %widesel = select <4 x i1> %widecmp, <4 x i8> <i8 -1, i8 -2, i8 -3, i8 -4>, <4 x i8> <i8 1, i8 2, i8 3, i8 4>
+ %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x i8> %r
+}
+
+; PR38691 - https://bugs.llvm.org/show_bug.cgi?id=38691
+; If the operands are widened only to be narrowed back, then all of the shuffles are unnecessary.
+
+define <2 x i8> @narrow_shuffle_of_select_with_widened_ops(<2 x i1> %cmp, <2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @narrow_shuffle_of_select_with_widened_ops(
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
+;
+ %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %widey = shufflevector <2 x i8> %y, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %widesel = select <4 x i1> %widecmp, <4 x i8> %widex, <4 x i8> %widey
+ %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x i8> %r
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shuffle_select.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,1466 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Try to eliminate binops and shuffles when the shuffle is a select in disguise:
+; PR37806 - https://bugs.llvm.org/show_bug.cgi?id=37806
+
+define <4 x i32> @add(<4 x i32> %v) {
+; CHECK-LABEL: @add(
+; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[V:%.*]], <i32 11, i32 0, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = add <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+; Propagate flags when possible.
+
+define <4 x i32> @add_nuw_nsw(<4 x i32> %v) {
+; CHECK-LABEL: @add_nuw_nsw(
+; CHECK-NEXT: [[S:%.*]] = add nuw nsw <4 x i32> [[V:%.*]], <i32 11, i32 0, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = add nuw nsw <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @add_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @add_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[V:%.*]], <i32 11, i32 0, i32 undef, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = add <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 5, i32 undef, i32 7>
+ ret <4 x i32> %s
+}
+
+; Poison flags must be dropped or undef must be replaced with safe constant.
+
+define <4 x i32> @add_nuw_nsw_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @add_nuw_nsw_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[V:%.*]], <i32 11, i32 undef, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = add nuw nsw <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+; Constant operand 0 (LHS) could work for some non-commutative binops?
+
+define <4 x i32> @sub(<4 x i32> %v) {
+; CHECK-LABEL: @sub(
+; CHECK-NEXT: [[B:%.*]] = sub <4 x i32> <i32 undef, i32 undef, i32 undef, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = sub <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+; If any element of the shuffle mask operand is undef, that element of the result is undef.
+; The shuffle is eliminated in this transform, but we can replace a constant element with undef.
+; Preserve flags when possible. It's not safe to propagate poison-generating flags with undef constants.
+
+define <4 x i32> @mul(<4 x i32> %v) {
+; CHECK-LABEL: @mul(
+; CHECK-NEXT: [[S:%.*]] = mul <4 x i32> [[V:%.*]], <i32 undef, i32 12, i32 1, i32 14>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = mul nsw nuw <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @shl(<4 x i32> %v) {
+; CHECK-LABEL: @shl(
+; CHECK-NEXT: [[S:%.*]] = shl <4 x i32> [[V:%.*]], <i32 0, i32 12, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = shl <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @shl_nsw(<4 x i32> %v) {
+; CHECK-LABEL: @shl_nsw(
+; CHECK-NEXT: [[S:%.*]] = shl nsw <4 x i32> [[V:%.*]], <i32 0, i32 12, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = shl nsw <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @shl_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @shl_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = shl <4 x i32> [[V:%.*]], <i32 0, i32 12, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = shl <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @shl_nuw_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @shl_nuw_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = shl nuw <4 x i32> [[V:%.*]], <i32 0, i32 0, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = shl nuw <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @lshr_constant_op0(<4 x i32> %v) {
+; CHECK-LABEL: @lshr_constant_op0(
+; CHECK-NEXT: [[S:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 11, i32 12, i32 0, i32 14>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = lshr <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @lshr_exact_constant_op0(<4 x i32> %v) {
+; CHECK-LABEL: @lshr_exact_constant_op0(
+; CHECK-NEXT: [[S:%.*]] = lshr exact <4 x i32> [[V:%.*]], <i32 11, i32 12, i32 0, i32 14>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = lshr exact <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @lshr_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @lshr_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = shl <4 x i32> [[V:%.*]], <i32 0, i32 12, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = shl <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @lshr_exact_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @lshr_exact_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = lshr exact <4 x i32> [[V:%.*]], <i32 0, i32 0, i32 13, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = lshr exact <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @lshr_constant_op1(<4 x i32> %v) {
+; CHECK-LABEL: @lshr_constant_op1(
+; CHECK-NEXT: [[B:%.*]] = lshr exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = lshr exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+; Try weird types.
+
+define <3 x i32> @ashr(<3 x i32> %v) {
+; CHECK-LABEL: @ashr(
+; CHECK-NEXT: [[S:%.*]] = ashr <3 x i32> [[V:%.*]], <i32 0, i32 12, i32 13>
+; CHECK-NEXT: ret <3 x i32> [[S]]
+;
+ %b = ashr <3 x i32> %v, <i32 11, i32 12, i32 13>
+ %s = shufflevector <3 x i32> %b, <3 x i32> %v, <3 x i32> <i32 3, i32 1, i32 2>
+ ret <3 x i32> %s
+}
+
+define <3 x i42> @and(<3 x i42> %v) {
+; CHECK-LABEL: @and(
+; CHECK-NEXT: [[S:%.*]] = and <3 x i42> [[V:%.*]], <i42 -1, i42 12, i42 undef>
+; CHECK-NEXT: ret <3 x i42> [[S]]
+;
+ %b = and <3 x i42> %v, <i42 11, i42 12, i42 13>
+ %s = shufflevector <3 x i42> %v, <3 x i42> %b, <3 x i32> <i32 0, i32 4, i32 undef>
+ ret <3 x i42> %s
+}
+
+; It doesn't matter if the intermediate op has extra uses.
+
+declare void @use_v4i32(<4 x i32>)
+
+define <4 x i32> @or(<4 x i32> %v) {
+; CHECK-LABEL: @or(
+; CHECK-NEXT: [[B:%.*]] = or <4 x i32> [[V:%.*]], <i32 11, i32 12, i32 13, i32 14>
+; CHECK-NEXT: [[S:%.*]] = or <4 x i32> [[V]], <i32 0, i32 0, i32 13, i32 14>
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[B]])
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = or <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ call void @use_v4i32(<4 x i32> %b)
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @xor(<4 x i32> %v) {
+; CHECK-LABEL: @xor(
+; CHECK-NEXT: [[S:%.*]] = xor <4 x i32> [[V:%.*]], <i32 0, i32 12, i32 0, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = xor <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @udiv(<4 x i32> %v) {
+; CHECK-LABEL: @udiv(
+; CHECK-NEXT: [[B:%.*]] = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @udiv_exact(<4 x i32> %v) {
+; CHECK-LABEL: @udiv_exact(
+; CHECK-NEXT: [[B:%.*]] = udiv exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = udiv exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @udiv_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @udiv_undef_mask_elt(
+; CHECK-NEXT: [[B:%.*]] = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @udiv_exact_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @udiv_exact_undef_mask_elt(
+; CHECK-NEXT: [[B:%.*]] = udiv exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = udiv exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @sdiv(<4 x i32> %v) {
+; CHECK-LABEL: @sdiv(
+; CHECK-NEXT: [[S:%.*]] = sdiv <4 x i32> [[V:%.*]], <i32 11, i32 1, i32 13, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = sdiv <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @sdiv_exact(<4 x i32> %v) {
+; CHECK-LABEL: @sdiv_exact(
+; CHECK-NEXT: [[S:%.*]] = sdiv exact <4 x i32> [[V:%.*]], <i32 11, i32 1, i32 13, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = sdiv exact <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
+ ret <4 x i32> %s
+}
+
+; Div/rem need special handling if the shuffle has undef elements.
+
+define <4 x i32> @sdiv_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @sdiv_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = sdiv <4 x i32> [[V:%.*]], <i32 1, i32 1, i32 13, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = sdiv <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @sdiv_exact_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @sdiv_exact_undef_mask_elt(
+; CHECK-NEXT: [[S:%.*]] = sdiv exact <4 x i32> [[V:%.*]], <i32 1, i32 1, i32 13, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = sdiv exact <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @urem(<4 x i32> %v) {
+; CHECK-LABEL: @urem(
+; CHECK-NEXT: [[B:%.*]] = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @urem_undef_mask_elt(<4 x i32> %v) {
+; CHECK-LABEL: @urem_undef_mask_elt(
+; CHECK-NEXT: [[B:%.*]] = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %s
+}
+
+define <4 x i32> @srem(<4 x i32> %v) {
+; CHECK-LABEL: @srem(
+; CHECK-NEXT: [[B:%.*]] = srem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[S]]
+;
+ %b = srem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
+ %s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+ ret <4 x i32> %s
+}
+
+; Try FP ops/types.
+
+define <4 x float> @fadd(<4 x float> %v) {
+; CHECK-LABEL: @fadd(
+; CHECK-NEXT: [[S:%.*]] = fadd <4 x float> [[V:%.*]], <float 4.100000e+01, float 4.200000e+01, float -0.000000e+00, float -0.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[S]]
+;
+ %b = fadd <4 x float> %v, <float 41.0, float 42.0, float 43.0, float 44.0>
+ %s = shufflevector <4 x float> %b, <4 x float> %v, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x float> %s
+}
+
+define <4 x double> @fsub(<4 x double> %v) {
+; CHECK-LABEL: @fsub(
+; CHECK-NEXT: [[B:%.*]] = fsub <4 x double> <double undef, double undef, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x double> [[S]]
+;
+ %b = fsub <4 x double> <double 41.0, double 42.0, double 43.0, double 44.0>, %v
+ %s = shufflevector <4 x double> %v, <4 x double> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+ ret <4 x double> %s
+}
+
+; Propagate any FMF.
+
+define <4 x float> @fmul(<4 x float> %v) {
+; CHECK-LABEL: @fmul(
+; CHECK-NEXT: [[S:%.*]] = fmul nnan ninf <4 x float> [[V:%.*]], <float 4.100000e+01, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[S]]
+;
+ %b = fmul nnan ninf <4 x float> %v, <float 41.0, float 42.0, float 43.0, float 44.0>
+ %s = shufflevector <4 x float> %b, <4 x float> %v, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+ ret <4 x float> %s
+}
+
+define <4 x double> @fdiv_constant_op0(<4 x double> %v) {
+; CHECK-LABEL: @fdiv_constant_op0(
+; CHECK-NEXT: [[B:%.*]] = fdiv fast <4 x double> <double undef, double undef, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x double> [[S]]
+;
+ %b = fdiv fast <4 x double> <double 41.0, double 42.0, double 43.0, double 44.0>, %v
+ %s = shufflevector <4 x double> %v, <4 x double> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+ ret <4 x double> %s
+}
+
+define <4 x double> @fdiv_constant_op1(<4 x double> %v) {
+; CHECK-LABEL: @fdiv_constant_op1(
+; CHECK-NEXT: [[S:%.*]] = fdiv reassoc <4 x double> [[V:%.*]], <double undef, double 1.000000e+00, double 4.300000e+01, double 4.400000e+01>
+; CHECK-NEXT: ret <4 x double> [[S]]
+;
+ %b = fdiv reassoc <4 x double> %v, <double 41.0, double 42.0, double 43.0, double 44.0>
+ %s = shufflevector <4 x double> %v, <4 x double> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+ ret <4 x double> %s
+}
+
+define <4 x double> @frem(<4 x double> %v) {
+; CHECK-LABEL: @frem(
+; CHECK-NEXT: [[B:%.*]] = frem <4 x double> <double 4.100000e+01, double 4.200000e+01, double undef, double undef>, [[V:%.*]]
+; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[B]], <4 x double> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x double> [[S]]
+;
+ %b = frem <4 x double> <double 41.0, double 42.0, double 43.0, double 44.0>, %v
+ %s = shufflevector <4 x double> %b, <4 x double> %v, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x double> %s
+}
+
+; Tests where both operands of the shuffle are binops with the same opcode.
+
+define <4 x i32> @add_add(<4 x i32> %v0) {
+; CHECK-LABEL: @add_add(
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @add_add_nsw(<4 x i32> %v0) {
+; CHECK-LABEL: @add_add_nsw(
+; CHECK-NEXT: [[T3:%.*]] = add nsw <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @add_add_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @add_add_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 undef, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Poison flags must be dropped or undef must be replaced with safe constant.
+
+define <4 x i32> @add_add_nsw_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @add_add_nsw_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 undef, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Constant operand 0 (LHS) also works.
+
+define <4 x i32> @sub_sub(<4 x i32> %v0) {
+; CHECK-LABEL: @sub_sub(
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sub_sub_nuw(<4 x i32> %v0) {
+; CHECK-LABEL: @sub_sub_nuw(
+; CHECK-NEXT: [[T3:%.*]] = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sub_sub_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @sub_sub_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Poison flags must be dropped or undef must be replaced with safe constant.
+
+define <4 x i32> @sub_sub_nuw_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @sub_sub_nuw_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; If any element of the shuffle mask operand is undef, that element of the result is undef.
+; The shuffle is eliminated in this transform, but we can replace a constant element with undef.
+
+define <4 x i32> @mul_mul(<4 x i32> %v0) {
+; CHECK-LABEL: @mul_mul(
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = mul <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Preserve flags when possible.
+
+define <4 x i32> @shl_shl(<4 x i32> %v0) {
+; CHECK-LABEL: @shl_shl(
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @shl_shl_nuw(<4 x i32> %v0) {
+; CHECK-LABEL: @shl_shl_nuw(
+; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Shift by undef is poison. Undef must be replaced by safe constant.
+
+define <4 x i32> @shl_shl_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @shl_shl_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+ ret <4 x i32> %t3
+}
+
+; Shift by undef is poison. Undef must be replaced by safe constant.
+
+define <4 x i32> @shl_shl_nuw_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @shl_shl_nuw_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+ ret <4 x i32> %t3
+}
+
+; Can't propagate the flag here.
+
+define <4 x i32> @lshr_lshr(<4 x i32> %v0) {
+; CHECK-LABEL: @lshr_lshr(
+; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Try weird types.
+
+define <3 x i32> @ashr_ashr(<3 x i32> %v0) {
+; CHECK-LABEL: @ashr_ashr(
+; CHECK-NEXT: [[T3:%.*]] = ashr <3 x i32> [[V0:%.*]], <i32 4, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t1 = ashr <3 x i32> %v0, <i32 1, i32 2, i32 3>
+ %t2 = ashr <3 x i32> %v0, <i32 4, i32 5, i32 6>
+ %t3 = shufflevector <3 x i32> %t1, <3 x i32> %t2, <3 x i32> <i32 3, i32 1, i32 2>
+ ret <3 x i32> %t3
+}
+
+define <3 x i42> @and_and(<3 x i42> %v0) {
+; CHECK-LABEL: @and_and(
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i42> [[V0:%.*]], <i42 1, i42 5, i42 undef>
+; CHECK-NEXT: ret <3 x i42> [[T3]]
+;
+ %t1 = and <3 x i42> %v0, <i42 1, i42 2, i42 3>
+ %t2 = and <3 x i42> %v0, <i42 4, i42 5, i42 6>
+ %t3 = shufflevector <3 x i42> %t1, <3 x i42> %t2, <3 x i32> <i32 0, i32 4, i32 undef>
+ ret <3 x i42> %t3
+}
+
+; It doesn't matter if the intermediate ops have extra uses.
+
+define <4 x i32> @or_or(<4 x i32> %v0) {
+; CHECK-LABEL: @or_or(
+; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
+; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[V0]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = or <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ call void @use_v4i32(<4 x i32> %t1)
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @xor_xor(<4 x i32> %v0) {
+; CHECK-LABEL: @xor_xor(
+; CHECK-NEXT: [[T2:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 7, i32 8>
+; CHECK-NEXT: [[T3:%.*]] = xor <4 x i32> [[V0]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = xor <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = xor <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+ call void @use_v4i32(<4 x i32> %t2)
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @udiv_udiv(<4 x i32> %v0) {
+; CHECK-LABEL: @udiv_udiv(
+; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
+; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0]]
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ call void @use_v4i32(<4 x i32> %t1)
+ call void @use_v4i32(<4 x i32> %t2)
+ ret <4 x i32> %t3
+}
+
+; Div/rem need special handling if the shuffle has undef elements.
+
+define <4 x i32> @sdiv_sdiv(<4 x i32> %v0) {
+; CHECK-LABEL: @sdiv_sdiv(
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sdiv_sdiv_exact(<4 x i32> %v0) {
+; CHECK-LABEL: @sdiv_sdiv_exact(
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sdiv_sdiv_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @sdiv_sdiv_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sdiv_sdiv_exact_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @sdiv_sdiv_exact_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @urem_urem(<4 x i32> %v0) {
+; CHECK-LABEL: @urem_urem(
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x i32> %t3
+}
+
+; This is folded by using a safe constant.
+
+define <4 x i32> @urem_urem_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @urem_urem_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 0>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @srem_srem(<4 x i32> %v0) {
+; CHECK-LABEL: @srem_srem(
+; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+ ret <4 x i32> %t3
+}
+
+; This is folded by using a safe constant.
+
+define <4 x i32> @srem_srem_undef_mask_elt(<4 x i32> %v0) {
+; CHECK-LABEL: @srem_srem_undef_mask_elt(
+; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 0, i32 7, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 6, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Try FP ops/types.
+
+define <4 x float> @fadd_fadd(<4 x float> %v0) {
+; CHECK-LABEL: @fadd_fadd(
+; CHECK-NEXT: [[T3:%.*]] = fadd <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
+;
+ %t1 = fadd <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
+ %t2 = fadd <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
+ %t3 = shufflevector <4 x float> %t1, <4 x float> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x float> %t3
+}
+
+define <4 x double> @fsub_fsub(<4 x double> %v0) {
+; CHECK-LABEL: @fsub_fsub(
+; CHECK-NEXT: [[T3:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
+;
+ %t1 = fsub <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
+ %t2 = fsub <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
+ %t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+ ret <4 x double> %t3
+}
+
+; Intersect any FMF.
+
+define <4 x float> @fmul_fmul(<4 x float> %v0) {
+; CHECK-LABEL: @fmul_fmul(
+; CHECK-NEXT: [[T3:%.*]] = fmul nnan ninf <4 x float> [[V0:%.*]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
+;
+ %t1 = fmul nnan ninf <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
+ %t2 = fmul nnan ninf <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
+ %t3 = shufflevector <4 x float> %t1, <4 x float> %t2, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+ ret <4 x float> %t3
+}
+
+define <4 x double> @fdiv_fdiv(<4 x double> %v0) {
+; CHECK-LABEL: @fdiv_fdiv(
+; CHECK-NEXT: [[T3:%.*]] = fdiv nnan arcp <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
+;
+ %t1 = fdiv fast <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
+ %t2 = fdiv nnan arcp <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
+ %t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+ ret <4 x double> %t3
+}
+
+; The variable operand must be either the first operand or second operand in both binops.
+
+define <4 x double> @frem_frem(<4 x double> %v0) {
+; CHECK-LABEL: @frem_frem(
+; CHECK-NEXT: [[T1:%.*]] = frem <4 x double> <double 1.000000e+00, double 2.000000e+00, double undef, double undef>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = frem <4 x double> [[V0]], <double undef, double undef, double 7.000000e+00, double 8.000000e+00>
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x double> [[T3]]
+;
+ %t1 = frem <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
+ %t2 = frem <4 x double> %v0, <double 5.0, double 6.0, double 7.0, double 8.0>
+ %t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x double> %t3
+}
+
+define <4 x i32> @add_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @add_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = add <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Constant operand 0 (LHS) also works.
+
+define <4 x i32> @sub_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sub_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sub_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sub_2_vars_nsw(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sub_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sub_2_vars_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Poison flags must be dropped or undef must be replaced with safe constant.
+
+define <4 x i32> @sub_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sub_2_vars_nsw_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; If any element of the shuffle mask operand is undef, that element of the result is undef.
+; The shuffle is eliminated in this transform, but we can replace a constant element with undef.
+
+define <4 x i32> @mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @mul_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @mul_2_vars_nuw(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @mul_2_vars_nuw(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @mul_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @mul_2_vars_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Poison flags must be dropped or undef must be replaced with safe constant.
+
+define <4 x i32> @mul_2_vars_nuw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @mul_2_vars_nuw_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Preserve flags when possible.
+
+define <4 x i32> @shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @shl_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @shl_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @shl_2_vars_nsw(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Shift by undef is poison. Undef is replaced by safe constant.
+
+define <4 x i32> @shl_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @shl_2_vars_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+ ret <4 x i32> %t3
+}
+
+; Shift by undef is poison. Undef is replaced by safe constant.
+
+define <4 x i32> @shl_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @shl_2_vars_nsw_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+; CHECK-NEXT: [[T3:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
+ ret <4 x i32> %t3
+}
+
+; Can't propagate the flag here.
+
+define <4 x i32> @lshr_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @lshr_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @lshr_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @lshr_2_vars_exact(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = lshr exact <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; TODO: This would require a new shuffle mask (replace undef with op0 or op1 lane). Otherwise, we have shift-by-undef.
+
+define <4 x i32> @lshr_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @lshr_2_vars_undef_mask_elt(
+; CHECK-NEXT: [[T1:%.*]] = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; TODO: This would require a new shuffle mask (replace undef with op0 or op1 lane). Otherwise, we have shift-by-undef.
+
+define <4 x i32> @lshr_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @lshr_2_vars_exact_undef_mask_elt(
+; CHECK-NEXT: [[T1:%.*]] = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Try weird types.
+
+define <3 x i32> @ashr_2_vars(<3 x i32> %v0, <3 x i32> %v1) {
+; CHECK-LABEL: @ashr_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[V1:%.*]], <3 x i32> [[V0:%.*]], <3 x i32> <i32 0, i32 4, i32 5>
+; CHECK-NEXT: [[T3:%.*]] = ashr <3 x i32> [[TMP1]], <i32 4, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t1 = ashr <3 x i32> %v0, <i32 1, i32 2, i32 3>
+ %t2 = ashr <3 x i32> %v1, <i32 4, i32 5, i32 6>
+ %t3 = shufflevector <3 x i32> %t1, <3 x i32> %t2, <3 x i32> <i32 3, i32 1, i32 2>
+ ret <3 x i32> %t3
+}
+
+define <3 x i42> @and_2_vars(<3 x i42> %v0, <3 x i42> %v1) {
+; CHECK-LABEL: @and_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i42> [[V0:%.*]], <3 x i42> [[V1:%.*]], <3 x i32> <i32 0, i32 4, i32 undef>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i42> [[TMP1]], <i42 1, i42 5, i42 undef>
+; CHECK-NEXT: ret <3 x i42> [[T3]]
+;
+ %t1 = and <3 x i42> %v0, <i42 1, i42 2, i42 3>
+ %t2 = and <3 x i42> %v1, <i42 4, i42 5, i42 6>
+ %t3 = shufflevector <3 x i42> %t1, <3 x i42> %t2, <3 x i32> <i32 0, i32 4, i32 undef>
+ ret <3 x i42> %t3
+}
+
+; It doesn't matter if only one intermediate op has extra uses.
+
+define <4 x i32> @or_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @or_2_vars(
+; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[TMP1]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = or <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ call void @use_v4i32(<4 x i32> %t1)
+ ret <4 x i32> %t3
+}
+
+; But we don't transform if both intermediate values have extra uses.
+
+define <4 x i32> @xor_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @xor_2_vars(
+; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
+; CHECK-NEXT: [[T2:%.*]] = xor <4 x i32> [[V1:%.*]], <i32 5, i32 6, i32 7, i32 8>
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
+; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = xor <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = xor <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+ call void @use_v4i32(<4 x i32> %t1)
+ call void @use_v4i32(<4 x i32> %t2)
+ ret <4 x i32> %t3
+}
+
+; Div/rem need special handling if the shuffle has undef elements.
+
+define <4 x i32> @udiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @udiv_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @udiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @udiv_2_vars_exact(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = udiv exact <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; TODO: This could be transformed using a safe constant.
+
+define <4 x i32> @udiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @udiv_2_vars_undef_mask_elt(
+; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; TODO: This could be transformed using a safe constant.
+
+define <4 x i32> @udiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @udiv_2_vars_exact_undef_mask_elt(
+; CHECK-NEXT: [[T1:%.*]] = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
+ ret <4 x i32> %t3
+}
+
+; If the shuffle has no undefs, it's safe to shuffle the variables first.
+
+define <4 x i32> @sdiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sdiv_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @sdiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sdiv_2_vars_exact(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Div by undef is UB. Undef is replaced by safe constant.
+
+define <4 x i32> @sdiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sdiv_2_vars_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %t3
+}
+
+; Div by undef is UB. Undef is replaced by safe constant.
+
+define <4 x i32> @sdiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @sdiv_2_vars_exact_undef_mask_elt(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+ ret <4 x i32> %t3
+}
+
+; If the shuffle has no undefs, it's safe to shuffle the variables first.
+
+define <4 x i32> @urem_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @urem_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @srem_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @srem_2_vars(
+; CHECK-NEXT: [[T1:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 undef, i32 6, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 6, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Try FP ops/types.
+
+define <4 x float> @fadd_2_vars(<4 x float> %v0, <4 x float> %v1) {
+; CHECK-LABEL: @fadd_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[V0:%.*]], <4 x float> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = fadd <4 x float> [[TMP1]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
+;
+ %t1 = fadd <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
+ %t2 = fadd <4 x float> %v1, <float 5.0, float 6.0, float 7.0, float 8.0>
+ %t3 = shufflevector <4 x float> %t1, <4 x float> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x float> %t3
+}
+
+define <4 x double> @fsub_2_vars(<4 x double> %v0, <4 x double> %v1) {
+; CHECK-LABEL: @fsub_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
+;
+ %t1 = fsub <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
+ %t2 = fsub <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v1
+ %t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+ ret <4 x double> %t3
+}
+
+; Intersect any FMF.
+
+define <4 x float> @fmul_2_vars(<4 x float> %v0, <4 x float> %v1) {
+; CHECK-LABEL: @fmul_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[V0:%.*]], <4 x float> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = fmul reassoc nsz <4 x float> [[TMP1]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
+;
+ %t1 = fmul reassoc nsz <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
+ %t2 = fmul reassoc nsz <4 x float> %v1, <float 5.0, float 6.0, float 7.0, float 8.0>
+ %t3 = shufflevector <4 x float> %t1, <4 x float> %t2, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+ ret <4 x float> %t3
+}
+
+define <4 x double> @frem_2_vars(<4 x double> %v0, <4 x double> %v1) {
+; CHECK-LABEL: @frem_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = frem nnan <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
+;
+ %t1 = frem nnan ninf <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
+ %t2 = frem nnan arcp <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v1
+ %t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
+ ret <4 x double> %t3
+}
+
+; The variable operand must be either the first operand or second operand in both binops.
+
+define <4 x double> @fdiv_2_vars(<4 x double> %v0, <4 x double> %v1) {
+; CHECK-LABEL: @fdiv_2_vars(
+; CHECK-NEXT: [[T1:%.*]] = fdiv <4 x double> <double 1.000000e+00, double 2.000000e+00, double undef, double undef>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = fdiv <4 x double> [[V1:%.*]], <double undef, double undef, double 7.000000e+00, double 8.000000e+00>
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x double> [[T3]]
+;
+ %t1 = fdiv <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
+ %t2 = fdiv <4 x double> %v1, <double 5.0, double 6.0, double 7.0, double 8.0>
+ %t3 = shufflevector <4 x double> %t1, <4 x double> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x double> %t3
+}
+
+; Shift-left with constant shift amount can be converted to mul to enable the fold.
+
+define <4 x i32> @mul_shl(<4 x i32> %v0) {
+; CHECK-LABEL: @mul_shl(
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[V0:%.*]], <i32 32, i32 64, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Try with shift as operand 0 of the shuffle; 'nsw' is dropped for safety, but that could be improved.
+
+define <4 x i32> @shl_mul(<4 x i32> %v0) {
+; CHECK-LABEL: @shl_mul(
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 5, i32 undef, i32 8, i32 16>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = mul nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Demanded elements + simplification can remove the mul alone, but that's not the best case.
+
+define <4 x i32> @mul_is_nop_shl(<4 x i32> %v0) {
+; CHECK-LABEL: @mul_is_nop_shl(
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+ ret <4 x i32> %t3
+}
+
+; Negative test: shift amount (operand 1) must be constant.
+
+define <4 x i32> @shl_mul_not_constant_shift_amount(<4 x i32> %v0) {
+; CHECK-LABEL: @shl_mul_not_constant_shift_amount(
+; CHECK-NEXT: [[T1:%.*]] = shl <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = mul <4 x i32> [[V0]], <i32 5, i32 6, i32 undef, i32 undef>
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T2]], <4 x i32> [[T1]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
+ %t2 = mul <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Try with 2 variable inputs.
+
+define <4 x i32> @mul_shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @mul_shl_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 32, i32 64, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = shl nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+define <4 x i32> @shl_mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @shl_mul_2_vars(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 undef, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 5, i32 undef, i32 8, i32 16>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
+ %t2 = mul nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Or with constant can be converted to add to enable the fold.
+; The 'shl' is here to allow analysis to determine that the 'or' can be transformed to 'add'.
+; TODO: The 'or' constant is limited to a splat.
+
+define <4 x i32> @add_or(<4 x i32> %v) {
+; CHECK-LABEL: @add_or(
+; CHECK-NEXT: [[V0:%.*]] = shl <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0]], <i32 31, i32 31, i32 65536, i32 65537>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %v0 = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> ; clear the bottom bits
+ %t1 = add <4 x i32> %v0, <i32 65534, i32 65535, i32 65536, i32 65537> ; this can't be converted to 'or'
+ %t2 = or <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31> ; set the bottom bits
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+; Try with 'or' as operand 0 of the shuffle.
+
+define <4 x i8> @or_add(<4 x i8> %v) {
+; CHECK-LABEL: @or_add(
+; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 3, i8 3, i8 3, i8 3>
+; CHECK-NEXT: [[T3:%.*]] = add nuw nsw <4 x i8> [[V0]], <i8 1, i8 2, i8 -64, i8 -64>
+; CHECK-NEXT: ret <4 x i8> [[T3]]
+;
+ %v0 = lshr <4 x i8> %v, <i8 3, i8 3, i8 3, i8 3> ; clear the top bits
+ %t1 = or <4 x i8> %v0, <i8 192, i8 192, i8 192, i8 192> ; set some top bits
+ %t2 = add nsw nuw <4 x i8> %v0, <i8 1, i8 2, i8 3, i8 4> ; this can't be converted to 'or'
+ %t3 = shufflevector <4 x i8> %t1, <4 x i8> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i8> %t3
+}
+
+; Negative test: not all 'or' insts can be converted to 'add'.
+
+define <4 x i8> @or_add_not_enough_masking(<4 x i8> %v) {
+; CHECK-LABEL: @or_add_not_enough_masking(
+; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 1, i8 1, i8 1, i8 1>
+; CHECK-NEXT: [[T1:%.*]] = or <4 x i8> [[V0]], <i8 undef, i8 undef, i8 -64, i8 -64>
+; CHECK-NEXT: [[T2:%.*]] = add <4 x i8> [[V0]], <i8 1, i8 2, i8 undef, i8 undef>
+; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i8> [[T2]], <4 x i8> [[T1]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: ret <4 x i8> [[T3]]
+;
+ %v0 = lshr <4 x i8> %v, <i8 1, i8 1, i8 1, i8 1> ; clear not enough top bits
+ %t1 = or <4 x i8> %v0, <i8 192, i8 192, i8 192, i8 192> ; set some top bits
+ %t2 = add nsw nuw <4 x i8> %v0, <i8 1, i8 2, i8 3, i8 4> ; this can't be converted to 'or'
+ %t3 = shufflevector <4 x i8> %t1, <4 x i8> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i8> %t3
+}
+
+; Try with 2 variable inputs.
+
+define <4 x i32> @add_or_2_vars(<4 x i32> %v, <4 x i32> %v1) {
+; CHECK-LABEL: @add_or_2_vars(
+; CHECK-NEXT: [[V0:%.*]] = shl <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[TMP1]], <i32 31, i32 31, i32 65536, i32 65537>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
+;
+ %v0 = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> ; clear the bottom bits
+ %t1 = add <4 x i32> %v1, <i32 65534, i32 65535, i32 65536, i32 65537> ; this can't be converted to 'or'
+ %t2 = or <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31> ; set the bottom bits
+ %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i32> %t3
+}
+
+define <4 x i8> @or_add_2_vars(<4 x i8> %v, <4 x i8> %v1) {
+; CHECK-LABEL: @or_add_2_vars(
+; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 3, i8 3, i8 3, i8 3>
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[V1:%.*]], <4 x i8> [[V0]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT: [[T3:%.*]] = add nuw nsw <4 x i8> [[TMP1]], <i8 1, i8 2, i8 -64, i8 -64>
+; CHECK-NEXT: ret <4 x i8> [[T3]]
+;
+ %v0 = lshr <4 x i8> %v, <i8 3, i8 3, i8 3, i8 3> ; clear the top bits
+ %t1 = or <4 x i8> %v0, <i8 192, i8 192, i8 192, i8 192> ; set some top bits
+ %t2 = add nsw nuw <4 x i8> %v1, <i8 1, i8 2, i8 3, i8 4> ; this can't be converted to 'or'
+ %t3 = shufflevector <4 x i8> %t1, <4 x i8> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+ ret <4 x i8> %t3
+}
+
+; The undef operand is used to simplify the shuffle mask, but don't assert that too soon.
+
+define <4 x i32> @PR41419(<4 x i32> %v) {
+; CHECK-LABEL: @PR41419(
+; CHECK-NEXT: ret <4 x i32> [[V:%.*]]
+;
+ %s = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+ ret <4 x i32> %s
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/shufflevec-bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shufflevec-bitcast.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shufflevec-bitcast.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shufflevec-bitcast.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,16 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define void @test(<16 x i8> %w, i32* %o1, float* %o2) {
+
+; CHECK: %v.bc = bitcast <16 x i8> %w to <4 x i32>
+; CHECK-NEXT: %v.extract = extractelement <4 x i32> %v.bc, i32 3
+; CHECK-NEXT: %v.bc{{[0-9]*}} = bitcast <16 x i8> %w to <4 x float>
+; CHECK-NEXT: %v.extract{{[0-9]*}} = extractelement <4 x float> %v.bc{{[0-9]*}}, i32 3
+
+ %v = shufflevector <16 x i8> %w, <16 x i8> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
+ %f = bitcast <4 x i8> %v to float
+ %i = bitcast <4 x i8> %v to i32
+ store i32 %i, i32* %o1, align 4
+ store float %f, float* %o2, align 4
+ ret void
+}
Added: llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shufflevec-constant.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9"
+
+define <4 x float> @__inff4() nounwind readnone {
+; CHECK-LABEL: @__inff4(
+; CHECK-NEXT: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0x7FF0000000000000, float 0x7FF0000000000000>
+;
+ %tmp14 = extractelement <1 x double> bitcast (<2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000> to <1 x double>), i32 0
+ %tmp4 = bitcast double %tmp14 to i64
+ %tmp3 = bitcast i64 %tmp4 to <2 x float>
+ %tmp8 = shufflevector <2 x float> %tmp3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+ %tmp9 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp8, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+ ret <4 x float> %tmp9
+}
Added: llvm/trunk/test/Transforms/InstCombine/sign-test-and-or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sign-test-and-or.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sign-test-and-or.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sign-test-and-or.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+declare void @foo()
+
+define i1 @test1(i32 %a, i32 %b) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %1 = icmp slt i32 %a, 0
+ %2 = icmp slt i32 %b, 0
+ %or.cond = or i1 %1, %2
+ ret i1 %or.cond
+}
+
+define i1 @test2(i32 %a, i32 %b) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %1 = icmp sgt i32 %a, -1
+ %2 = icmp sgt i32 %b, -1
+ %or.cond = or i1 %1, %2
+ ret i1 %or.cond
+}
+
+define i1 @test3(i32 %a, i32 %b) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %1 = icmp slt i32 %a, 0
+ %2 = icmp slt i32 %b, 0
+ %or.cond = and i1 %1, %2
+ ret i1 %or.cond
+}
+
+define i1 @test4(i32 %a, i32 %b) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %1 = icmp sgt i32 %a, -1
+ %2 = icmp sgt i32 %b, -1
+ %or.cond = and i1 %1, %2
+ ret i1 %or.cond
+}
+
+define void @test5(i32 %a) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, -2013265920
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: br i1 [[TMP2]], label %if.then, label %if.end
+;
+ %and = and i32 %a, 134217728
+ %1 = icmp eq i32 %and, 0
+ %2 = icmp sgt i32 %a, -1
+ %or.cond = and i1 %1, %2
+ br i1 %or.cond, label %if.then, label %if.end
+
+
+if.then:
+ tail call void @foo() nounwind
+ ret void
+
+if.end:
+ ret void
+}
+
+define void @test6(i32 %a) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, -2013265920
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: br i1 [[TMP2]], label %if.then, label %if.end
+;
+ %1 = icmp sgt i32 %a, -1
+ %and = and i32 %a, 134217728
+ %2 = icmp eq i32 %and, 0
+ %or.cond = and i1 %1, %2
+ br i1 %or.cond, label %if.then, label %if.end
+
+
+if.then:
+ tail call void @foo() nounwind
+ ret void
+
+if.end:
+ ret void
+}
+
+define void @test7(i32 %a) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, -2013265920
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: br i1 [[TMP2]], label %if.end, label %if.then
+;
+ %and = and i32 %a, 134217728
+ %1 = icmp ne i32 %and, 0
+ %2 = icmp slt i32 %a, 0
+ %or.cond = or i1 %1, %2
+ br i1 %or.cond, label %if.then, label %if.end
+
+
+if.then:
+ tail call void @foo() nounwind
+ ret void
+
+if.end:
+ ret void
+}
+
+define void @test8(i32 %a) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, -2013265920
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: br i1 [[TMP2]], label %if.end, label %if.then
+;
+ %1 = icmp slt i32 %a, 0
+ %and = and i32 %a, 134217728
+ %2 = icmp ne i32 %and, 0
+ %or.cond = or i1 %1, %2
+ br i1 %or.cond, label %if.then, label %if.end
+
+
+if.then:
+ tail call void @foo()
+ ret void
+
+if.end:
+ ret void
+}
+
+define i1 @test9(i32 %a) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, -1073741824
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1073741824
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %1 = and i32 %a, 1073741824
+ %2 = icmp ne i32 %1, 0
+ %3 = icmp sgt i32 %a, -1
+ %or.cond = and i1 %2, %3
+ ret i1 %or.cond
+}
+
+define i1 @test10(i32 %a) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %a, 2
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %1 = and i32 %a, 2
+ %2 = icmp eq i32 %1, 0
+ %3 = icmp ult i32 %a, 4
+ %or.cond = and i1 %2, %3
+ ret i1 %or.cond
+}
+
+define i1 @test11(i32 %a) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 %a, 1
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %1 = and i32 %a, 2
+ %2 = icmp ne i32 %1, 0
+ %3 = icmp ugt i32 %a, 3
+ %or.cond = or i1 %2, %3
+ ret i1 %or.cond
+}
Added: llvm/trunk/test/Transforms/InstCombine/signed-comparison.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/signed-comparison.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/signed-comparison.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/signed-comparison.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Convert the zext+slt into a simple ult.
+
+define i1 @scalar_zext_slt(i16 %t4) {
+; CHECK-LABEL: @scalar_zext_slt(
+; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 %t4, 500
+; CHECK-NEXT: ret i1 [[T6]]
+;
+ %t5 = zext i16 %t4 to i32
+ %t6 = icmp slt i32 %t5, 500
+ ret i1 %t6
+}
+
+define <4 x i1> @vector_zext_slt(<4 x i16> %t4) {
+; CHECK-LABEL: @vector_zext_slt(
+; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> %t4, <i16 500, i16 0, i16 501, i16 -1>
+; CHECK-NEXT: ret <4 x i1> [[T6]]
+;
+ %t5 = zext <4 x i16> %t4 to <4 x i32>
+ %t6 = icmp slt <4 x i32> %t5, <i32 500, i32 0, i32 501, i32 65535>
+ ret <4 x i1> %t6
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/signed-truncation-check.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/signed-truncation-check.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/signed-truncation-check.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/signed-truncation-check.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,621 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; General pattern:
+; X & Y
+;
+; Where Y is checking that all the high bits (covered by a mask 4294967168)
+; are uniform, i.e. %arg & 4294967168 can be either 4294967168 or 0
+; Pattern can be one of:
+; %t = add i32 %arg, 128
+; %r = icmp ult i32 %t, 256
+; Or
+; %t0 = shl i32 %arg, 24
+; %t1 = ashr i32 %t0, 24
+; %r = icmp eq i32 %t1, %arg
+; Or
+; %t0 = trunc i32 %arg to i8
+; %t1 = sext i8 %t0 to i32
+; %r = icmp eq i32 %t1, %arg
+; This pattern is a signed truncation check.
+;
+; And X is checking that some bit in that same mask is zero.
+; I.e. can be one of:
+; %r = icmp sgt i32 %arg, -1
+; Or
+; %t = and i32 %arg, 2147483648
+; %r = icmp eq i32 %t, 0
+;
+; Since we are checking that all the bits in that mask are the same,
+; and a particular bit is zero, what we are really checking is that all the
+; masked bits are zero.
+; So this should be transformed to:
+; %r = icmp ult i32 %arg, 128
+
+; ============================================================================ ;
+; Basic positive test
+; ============================================================================ ;
+
+define i1 @positive_with_signbit(i32 %arg) {
+; CHECK-LABEL: @positive_with_signbit(
+; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
+;
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg, 128
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+define i1 @positive_with_mask(i32 %arg) {
+; CHECK-LABEL: @positive_with_mask(
+; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
+;
+ %t1 = and i32 %arg, 1107296256
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = add i32 %arg, 128
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @positive_with_icmp(i32 %arg) {
+; CHECK-LABEL: @positive_with_icmp(
+; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
+;
+ %t1 = icmp ult i32 %arg, 512
+ %t2 = add i32 %arg, 128
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+; Still the same
+define i1 @positive_with_aggressive_icmp(i32 %arg) {
+; CHECK-LABEL: @positive_with_aggressive_icmp(
+; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
+;
+ %t1 = icmp ult i32 %arg, 128
+ %t2 = add i32 %arg, 256
+ %t3 = icmp ult i32 %t2, 512
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+; I'm sure there is a bunch more patterns possible :/
+
+; This used to trigger an assert, because the icmp's are not direct
+; operands of the and.
+define i1 @positive_with_extra_and(i32 %arg, i1 %z) {
+; CHECK-LABEL: @positive_with_extra_and(
+; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[T5_SIMPLIFIED]], [[Z:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg, 128
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %z
+ %t5 = and i1 %t3, %t4
+ ret i1 %t5
+}
+
+; ============================================================================ ;
+; Vector tests
+; ============================================================================ ;
+
+define <2 x i1> @positive_vec_splat(<2 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_splat(
+; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <2 x i32> [[ARG:%.*]], <i32 128, i32 128>
+; CHECK-NEXT: ret <2 x i1> [[T4_SIMPLIFIED]]
+;
+ %t1 = icmp sgt <2 x i32> %arg, <i32 -1, i32 -1>
+ %t2 = add <2 x i32> %arg, <i32 128, i32 128>
+ %t3 = icmp ult <2 x i32> %t2, <i32 256, i32 256>
+ %t4 = and <2 x i1> %t1, %t3
+ ret <2 x i1> %t4
+}
+
+define <2 x i1> @positive_vec_nonsplat(<2 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_nonsplat(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[ARG:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[ARG]], <i32 128, i32 256>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <2 x i32> [[T2]], <i32 256, i32 512>
+; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <2 x i1> [[T4]]
+;
+ %t1 = icmp sgt <2 x i32> %arg, <i32 -1, i32 -1>
+ %t2 = add <2 x i32> %arg, <i32 128, i32 256>
+ %t3 = icmp ult <2 x i32> %t2, <i32 256, i32 512>
+ %t4 = and <2 x i1> %t1, %t3
+ ret <2 x i1> %t4
+}
+
+define <3 x i1> @positive_vec_undef0(<3 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_undef0(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], <i32 -1, i32 undef, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[ARG]], <i32 128, i32 128, i32 128>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 256, i32 256>
+; CHECK-NEXT: [[T4:%.*]] = and <3 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <3 x i1> [[T4]]
+;
+ %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 undef, i32 -1>
+ %t2 = add <3 x i32> %arg, <i32 128, i32 128, i32 128>
+ %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 256, i32 256>
+ %t4 = and <3 x i1> %t1, %t3
+ ret <3 x i1> %t4
+}
+
+define <3 x i1> @positive_vec_undef1(<3 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_undef1(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[ARG]], <i32 128, i32 undef, i32 128>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 256, i32 256>
+; CHECK-NEXT: [[T4:%.*]] = and <3 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <3 x i1> [[T4]]
+;
+ %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 -1, i32 -1>
+ %t2 = add <3 x i32> %arg, <i32 128, i32 undef, i32 128>
+ %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 256, i32 256>
+ %t4 = and <3 x i1> %t1, %t3
+ ret <3 x i1> %t4
+}
+
+define <3 x i1> @positive_vec_undef2(<3 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_undef2(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[ARG]], <i32 128, i32 128, i32 128>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
+; CHECK-NEXT: [[T4:%.*]] = and <3 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <3 x i1> [[T4]]
+;
+ %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 -1, i32 -1>
+ %t2 = add <3 x i32> %arg, <i32 128, i32 128, i32 128>
+ %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
+ %t4 = and <3 x i1> %t1, %t3
+ ret <3 x i1> %t4
+}
+
+define <3 x i1> @positive_vec_undef3(<3 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_undef3(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], <i32 -1, i32 undef, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[ARG]], <i32 128, i32 undef, i32 128>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 256, i32 256>
+; CHECK-NEXT: [[T4:%.*]] = and <3 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <3 x i1> [[T4]]
+;
+ %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 undef, i32 -1>
+ %t2 = add <3 x i32> %arg, <i32 128, i32 undef, i32 128>
+ %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 256, i32 256>
+ %t4 = and <3 x i1> %t1, %t3
+ ret <3 x i1> %t4
+}
+
+define <3 x i1> @positive_vec_undef4(<3 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_undef4(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], <i32 -1, i32 undef, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[ARG]], <i32 128, i32 128, i32 128>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
+; CHECK-NEXT: [[T4:%.*]] = and <3 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <3 x i1> [[T4]]
+;
+ %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 undef, i32 -1>
+ %t2 = add <3 x i32> %arg, <i32 128, i32 128, i32 128>
+ %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
+ %t4 = and <3 x i1> %t1, %t3
+ ret <3 x i1> %t4
+}
+
+define <3 x i1> @positive_vec_undef5(<3 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_undef5(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[ARG]], <i32 128, i32 undef, i32 128>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
+; CHECK-NEXT: [[T4:%.*]] = and <3 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <3 x i1> [[T4]]
+;
+ %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 -1, i32 -1>
+ %t2 = add <3 x i32> %arg, <i32 128, i32 undef, i32 128>
+ %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
+ %t4 = and <3 x i1> %t1, %t3
+ ret <3 x i1> %t4
+}
+
+define <3 x i1> @positive_vec_undef6(<3 x i32> %arg) {
+; CHECK-LABEL: @positive_vec_undef6(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], <i32 -1, i32 undef, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[ARG]], <i32 128, i32 undef, i32 128>
+; CHECK-NEXT: [[T3:%.*]] = icmp ult <3 x i32> [[T2]], <i32 256, i32 undef, i32 256>
+; CHECK-NEXT: [[T4:%.*]] = and <3 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <3 x i1> [[T4]]
+;
+ %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 undef, i32 -1>
+ %t2 = add <3 x i32> %arg, <i32 128, i32 undef, i32 128>
+ %t3 = icmp ult <3 x i32> %t2, <i32 256, i32 undef, i32 256>
+ %t4 = and <3 x i1> %t1, %t3
+ ret <3 x i1> %t4
+}
+
+; ============================================================================ ;
+; Commutativity tests.
+; ============================================================================ ;
+
+declare i32 @gen32()
+
+define i1 @commutative() {
+; CHECK-LABEL: @commutative(
+; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
+; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
+;
+ %arg = call i32 @gen32()
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg, 128
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t3, %t1 ; swapped order
+ ret i1 %t4
+}
+
+define i1 @commutative_with_icmp() {
+; CHECK-LABEL: @commutative_with_icmp(
+; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
+; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
+;
+ %arg = call i32 @gen32()
+ %t1 = icmp ult i32 %arg, 512
+ %t2 = add i32 %arg, 128
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t3, %t1 ; swapped order
+ ret i1 %t4
+}
+
+; ============================================================================ ;
+; Truncations.
+; ============================================================================ ;
+
+define i1 @positive_trunc_signbit(i32 %arg) {
+; CHECK-LABEL: @positive_trunc_signbit(
+; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
+; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
+;
+ %t1 = trunc i32 %arg to i8
+ %t2 = icmp sgt i8 %t1, -1
+ %t3 = add i32 %arg, 128
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @positive_trunc_base(i32 %arg) {
+; CHECK-LABEL: @positive_trunc_base(
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i16
+; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i16 [[T1]], 128
+; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
+;
+ %t1 = trunc i32 %arg to i16
+ %t2 = icmp sgt i16 %t1, -1
+ %t3 = add i16 %t1, 128
+ %t4 = icmp ult i16 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @positive_different_trunc_both(i32 %arg) {
+; CHECK-LABEL: @positive_different_trunc_both(
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i15
+; CHECK-NEXT: [[T2:%.*]] = icmp sgt i15 [[T1]], -1
+; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[ARG]] to i16
+; CHECK-NEXT: [[T4:%.*]] = add i16 [[T3]], 128
+; CHECK-NEXT: [[T5:%.*]] = icmp ult i16 [[T4]], 256
+; CHECK-NEXT: [[T6:%.*]] = and i1 [[T2]], [[T5]]
+; CHECK-NEXT: ret i1 [[T6]]
+;
+ %t1 = trunc i32 %arg to i15
+ %t2 = icmp sgt i15 %t1, -1
+ %t3 = trunc i32 %arg to i16
+ %t4 = add i16 %t3, 128
+ %t5 = icmp ult i16 %t4, 256
+ %t6 = and i1 %t2, %t5
+ ret i1 %t6
+}
+
+; ============================================================================ ;
+; One-use tests.
+;
+; We will only produce one instruction, so we do not care about one-use.
+; But, we *could* handle more patterns that we weren't able to canonicalize
+; because of extra-uses.
+; ============================================================================ ;
+
+declare void @use32(i32)
+declare void @use8(i8)
+declare void @use1(i1)
+
+define i1 @oneuse_with_signbit(i32 %arg) {
+; CHECK-LABEL: @oneuse_with_signbit(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
+; CHECK-NEXT: call void @use1(i1 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
+; CHECK-NEXT: call void @use1(i1 [[T3]])
+; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
+;
+ %t1 = icmp sgt i32 %arg, -1
+ call void @use1(i1 %t1)
+ %t2 = add i32 %arg, 128
+ call void @use32(i32 %t2)
+ %t3 = icmp ult i32 %t2, 256
+ call void @use1(i1 %t3)
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+define i1 @oneuse_with_mask(i32 %arg) {
+; CHECK-LABEL: @oneuse_with_mask(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 603979776
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
+; CHECK-NEXT: call void @use1(i1 [[T4]])
+; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
+; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
+;
+ %t1 = and i32 %arg, 603979776 ; some bit within the target 4294967168 mask.
+ call void @use32(i32 %t1)
+ %t2 = icmp eq i32 %t1, 0
+ call void @use1(i1 %t2)
+ %t3 = add i32 %arg, 128
+ call void @use32(i32 %t3)
+ %t4 = icmp ult i32 %t3, 256
+ call void @use1(i1 %t4)
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @oneuse_shl_ashr(i32 %arg) {
+; CHECK-LABEL: @oneuse_shl_ashr(
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
+; CHECK-NEXT: call void @use8(i8 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = icmp sgt i8 [[T1]], -1
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[ARG]], 24
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = ashr exact i32 [[T3]], 24
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], [[ARG]]
+; CHECK-NEXT: call void @use1(i1 [[T5]])
+; CHECK-NEXT: [[T6:%.*]] = and i1 [[T2]], [[T5]]
+; CHECK-NEXT: ret i1 [[T6]]
+;
+ %t1 = trunc i32 %arg to i8
+ call void @use8(i8 %t1)
+ %t2 = icmp sgt i8 %t1, -1
+ call void @use1(i1 %t2)
+ %t3 = shl i32 %arg, 24
+ call void @use32(i32 %t3)
+ %t4 = ashr i32 %t3, 24
+ call void @use32(i32 %t4)
+ %t5 = icmp eq i32 %t4, %arg
+ call void @use1(i1 %t5)
+ %t6 = and i1 %t2, %t5
+ ret i1 %t6
+}
+
+define zeroext i1 @oneuse_trunc_sext(i32 %arg) {
+; CHECK-LABEL: @oneuse_trunc_sext(
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
+; CHECK-NEXT: call void @use8(i8 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = icmp sgt i8 [[T1]], -1
+; CHECK-NEXT: call void @use1(i1 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[ARG]] to i8
+; CHECK-NEXT: call void @use8(i8 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = sext i8 [[T3]] to i32
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], [[ARG]]
+; CHECK-NEXT: call void @use1(i1 [[T5]])
+; CHECK-NEXT: [[T6:%.*]] = and i1 [[T2]], [[T5]]
+; CHECK-NEXT: ret i1 [[T6]]
+;
+ %t1 = trunc i32 %arg to i8
+ call void @use8(i8 %t1)
+ %t2 = icmp sgt i8 %t1, -1
+ call void @use1(i1 %t2)
+ %t3 = trunc i32 %arg to i8
+ call void @use8(i8 %t3)
+ %t4 = sext i8 %t3 to i32
+ call void @use32(i32 %t4)
+ %t5 = icmp eq i32 %t4, %arg
+ call void @use1(i1 %t5)
+ %t6 = and i1 %t2, %t5
+ ret i1 %t6
+}
+
+; ============================================================================ ;
+; Negative tests
+; ============================================================================ ;
+
+define i1 @negative_not_arg(i32 %arg, i32 %arg2) {
+; CHECK-LABEL: @negative_not_arg(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG2:%.*]], 128
+; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
+; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT: ret i1 [[T4]]
+;
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg2, 128 ; not %arg
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+define i1 @negative_trunc_not_arg(i32 %arg, i32 %arg2) {
+; CHECK-LABEL: @negative_trunc_not_arg(
+; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
+; CHECK-NEXT: [[T2:%.*]] = icmp sgt i8 [[T1]], -1
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG2:%.*]], 128
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = trunc i32 %arg to i8
+ %t2 = icmp sgt i8 %t1, -1
+ %t3 = add i32 %arg2, 128 ; not %arg
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @positive_with_mask_not_arg(i32 %arg, i32 %arg2) {
+; CHECK-LABEL: @positive_with_mask_not_arg(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1140850688
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG2:%.*]], 128
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = and i32 %arg, 1140850688
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = add i32 %arg2, 128 ; not %arg
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @negative_with_nonuniform_bad_mask(i32 %arg) {
+; CHECK-LABEL: @negative_with_nonuniform_bad_mask(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1711276033
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = and i32 %arg, 1711276033 ; lowest bit is set
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = add i32 %arg, 128
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @negative_with_uniform_bad_mask(i32 %arg) {
+; CHECK-LABEL: @negative_with_uniform_bad_mask(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], -16777152
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = and i32 %arg, 4278190144 ; 7'th bit is set
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = add i32 %arg, 128
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @negative_with_wrong_mask(i32 %arg) {
+; CHECK-LABEL: @negative_with_wrong_mask(
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1
+; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = and i32 %arg, 1 ; not even checking the right mask
+ %t2 = icmp eq i32 %t1, 0
+ %t3 = add i32 %arg, 128
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @negative_not_less_than(i32 %arg) {
+; CHECK-LABEL: @negative_not_less_than(
+; CHECK-NEXT: ret i1 false
+;
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg, 256 ; should be less than 256
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+define i1 @negative_not_power_of_two(i32 %arg) {
+; CHECK-LABEL: @negative_not_power_of_two(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 255
+; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
+; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT: ret i1 [[T4]]
+;
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg, 255 ; should be power of two
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+define i1 @negative_not_next_power_of_two(i32 %arg) {
+; CHECK-LABEL: @negative_not_next_power_of_two(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 64
+; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
+; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
+; CHECK-NEXT: ret i1 [[T4]]
+;
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg, 64 ; should be 256 >> 1
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %t3
+ ret i1 %t4
+}
+
+; I don't think this can be folded, at least not into single instruction.
+define i1 @two_signed_truncation_checks(i32 %arg) {
+; CHECK-LABEL: @two_signed_truncation_checks(
+; CHECK-NEXT: [[T1:%.*]] = add i32 [[ARG:%.*]], 512
+; CHECK-NEXT: [[T2:%.*]] = icmp ult i32 [[T1]], 1024
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = add i32 %arg, 512
+ %t2 = icmp ult i32 %t1, 1024
+ %t3 = add i32 %arg, 128
+ %t4 = icmp ult i32 %t3, 256
+ %t5 = and i1 %t2, %t4
+ ret i1 %t5
+}
+
+define i1 @bad_trunc_stc(i32 %arg) {
+; CHECK-LABEL: @bad_trunc_stc(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
+; CHECK-NEXT: [[T2:%.*]] = trunc i32 [[ARG]] to i16
+; CHECK-NEXT: [[T3:%.*]] = add i16 [[T2]], 128
+; CHECK-NEXT: [[T4:%.*]] = icmp ult i16 [[T3]], 256
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T1]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = icmp sgt i32 %arg, -1 ; checks a bit outside of the i16
+ %t2 = trunc i32 %arg to i16
+ %t3 = add i16 %t2, 128
+ %t4 = icmp ult i16 %t3, 256
+ %t5 = and i1 %t1, %t4
+ ret i1 %t5
+}
Added: llvm/trunk/test/Transforms/InstCombine/signext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/signext.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/signext.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/signext.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,102 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "n8:16:32:64"
+
+define i32 @test1(i32 %x) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
+; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
+; CHECK-NEXT: ret i32 [[TMP_3]]
+;
+ %tmp.1 = and i32 %x, 65535
+ %tmp.2 = xor i32 %tmp.1, -32768
+ %tmp.3 = add i32 %tmp.2, 32768
+ ret i32 %tmp.3
+}
+
+define i32 @test2(i32 %x) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
+; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
+; CHECK-NEXT: ret i32 [[TMP_3]]
+;
+ %tmp.1 = and i32 %x, 65535
+ %tmp.2 = xor i32 %tmp.1, 32768
+ %tmp.3 = add i32 %tmp.2, -32768
+ ret i32 %tmp.3
+}
+
+define i32 @test3(i16 %P) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[TMP_5:%.*]] = sext i16 %P to i32
+; CHECK-NEXT: ret i32 [[TMP_5]]
+;
+ %tmp.1 = zext i16 %P to i32
+ %tmp.4 = xor i32 %tmp.1, 32768
+ %tmp.5 = add i32 %tmp.4, -32768
+ ret i32 %tmp.5
+}
+
+define i32 @test4(i32 %x) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 24
+; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 24
+; CHECK-NEXT: ret i32 [[TMP_3]]
+;
+ %tmp.1 = and i32 %x, 255
+ %tmp.2 = xor i32 %tmp.1, 128
+ %tmp.3 = add i32 %tmp.2, -128
+ ret i32 %tmp.3
+}
+
+define i32 @test5(i32 %x) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: [[TMP_2:%.*]] = shl i32 %x, 16
+; CHECK-NEXT: [[TMP_4:%.*]] = ashr exact i32 [[TMP_2]], 16
+; CHECK-NEXT: ret i32 [[TMP_4]]
+;
+ %tmp.2 = shl i32 %x, 16
+ %tmp.4 = ashr i32 %tmp.2, 16
+ ret i32 %tmp.4
+}
+
+; If the shift amount equals the difference in width of the destination
+; and source scalar types:
+; ashr (shl (zext X), C), C --> sext X
+
+define i32 @test6(i16 %P) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[TMP_5:%.*]] = sext i16 %P to i32
+; CHECK-NEXT: ret i32 [[TMP_5]]
+;
+ %tmp.1 = zext i16 %P to i32
+ %sext1 = shl i32 %tmp.1, 16
+ %tmp.5 = ashr i32 %sext1, 16
+ ret i32 %tmp.5
+}
+
+; Vectors should get the same fold as above.
+
+define <2 x i32> @test6_splat_vec(<2 x i12> %P) {
+; CHECK-LABEL: @test6_splat_vec(
+; CHECK-NEXT: [[ASHR:%.*]] = sext <2 x i12> %P to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[ASHR]]
+;
+ %z = zext <2 x i12> %P to <2 x i32>
+ %shl = shl <2 x i32> %z, <i32 20, i32 20>
+ %ashr = ashr <2 x i32> %shl, <i32 20, i32 20>
+ ret <2 x i32> %ashr
+}
+
+define i32 @test7(i32 %x) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: [[SUB:%.*]] = ashr i32 %x, 5
+; CHECK-NEXT: ret i32 [[SUB]]
+;
+ %shr = lshr i32 %x, 5
+ %xor = xor i32 %shr, 67108864
+ %sub = add i32 %xor, -67108864
+ ret i32 %sub
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/simplify-demanded-bits-pointer.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,84 @@
+; RUN: opt < %s -instcombine -disable-output
+
+; SimplifyDemandedBits should cope with pointer types.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.VEC_rtx_base = type { i32, i32, [1 x %struct.rtx_def*] }
+ %struct.VEC_rtx_gc = type { %struct.VEC_rtx_base }
+ %struct.block_symbol = type { [3 x %struct.rtunion], %struct.object_block*, i64 }
+ %struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* }
+ %struct.omp_clause_subcode = type { i32 }
+ %struct.rtunion = type { i8* }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.section = type { %struct.unnamed_section }
+ %struct.u = type { %struct.block_symbol }
+ %struct.unnamed_section = type { %struct.omp_clause_subcode, void (i8*)*, i8*, %struct.section* }
+
+define fastcc void @cse_insn(%struct.rtx_def* %insn, %struct.rtx_def* %libcall_insn) nounwind {
+entry:
+ br i1 undef, label %bb43, label %bb88
+
+bb43: ; preds = %entry
+ br label %bb88
+
+bb88: ; preds = %bb43, %entry
+ br i1 undef, label %bb95, label %bb107
+
+bb95: ; preds = %bb88
+ unreachable
+
+bb107: ; preds = %bb88
+ %0 = load i16, i16* undef, align 8 ; <i16> [#uses=1]
+ %1 = icmp eq i16 %0, 38 ; <i1> [#uses=1]
+ %src_eqv_here.0 = select i1 %1, %struct.rtx_def* null, %struct.rtx_def* null ; <%struct.rtx_def*> [#uses=1]
+ br i1 undef, label %bb127, label %bb125
+
+bb125: ; preds = %bb107
+ br i1 undef, label %bb127, label %bb126
+
+bb126: ; preds = %bb125
+ br i1 undef, label %bb129, label %bb133
+
+bb127: ; preds = %bb125, %bb107
+ unreachable
+
+bb129: ; preds = %bb126
+ br label %bb133
+
+bb133: ; preds = %bb129, %bb126
+ br i1 undef, label %bb134, label %bb146
+
+bb134: ; preds = %bb133
+ unreachable
+
+bb146: ; preds = %bb133
+ br i1 undef, label %bb180, label %bb186
+
+bb180: ; preds = %bb146
+ %2 = icmp eq %struct.rtx_def* null, null ; <i1> [#uses=1]
+ %3 = zext i1 %2 to i8 ; <i8> [#uses=1]
+ %4 = icmp ne %struct.rtx_def* %src_eqv_here.0, null ; <i1> [#uses=1]
+ %5 = zext i1 %4 to i8 ; <i8> [#uses=1]
+ %toBool181 = icmp ne i8 %3, 0 ; <i1> [#uses=1]
+ %toBool182 = icmp ne i8 %5, 0 ; <i1> [#uses=1]
+ %6 = and i1 %toBool181, %toBool182 ; <i1> [#uses=1]
+ %7 = zext i1 %6 to i8 ; <i8> [#uses=1]
+ %toBool183 = icmp ne i8 %7, 0 ; <i1> [#uses=1]
+ br i1 %toBool183, label %bb184, label %bb186
+
+bb184: ; preds = %bb180
+ br i1 undef, label %bb185, label %bb186
+
+bb185: ; preds = %bb184
+ br label %bb186
+
+bb186: ; preds = %bb185, %bb184, %bb180, %bb146
+ br i1 undef, label %bb190, label %bb195
+
+bb190: ; preds = %bb186
+ unreachable
+
+bb195: ; preds = %bb186
+ unreachable
+}
Added: llvm/trunk/test/Transforms/InstCombine/simplify-libcalls-erased.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/simplify-libcalls-erased.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/simplify-libcalls-erased.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/simplify-libcalls-erased.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S < %s -instcombine | FileCheck %s
+
+target triple = "x86_64"
+
+define double @pow_exp(double %x, double %y) {
+; CHECK-LABEL: @pow_exp(
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[EXP:%.*]] = call fast double @llvm.exp.f64(double [[MUL]])
+; CHECK-NEXT: ret double [[EXP]]
+;
+ %A = alloca i1
+ %call = call fast double @exp(double %x) #1
+ %pow = call fast double @llvm.pow.f64(double %call, double %y)
+ %C1 = fcmp ule double %call, %pow
+ store i1 %C1, i1* %A
+ ret double %pow
+}
+
+declare double @exp(double)
+
+declare double @llvm.pow.f64(double, double) #0
+
+attributes #0 = { nounwind readnone speculatable }
+attributes #1 = { nounwind readnone }
Added: llvm/trunk/test/Transforms/InstCombine/simplify-libcalls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/simplify-libcalls.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/simplify-libcalls.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/simplify-libcalls.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,180 @@
+; RUN: opt -S < %s -instcombine | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
+
+ at G = constant [3 x i8] c"%s\00" ; <[3 x i8]*> [#uses=1]
+
+declare i32 @sprintf(i8*, i8*, ...)
+
+define void @foo(i8* %P, i32* %X) {
+ call i32 (i8*, i8*, ...) @sprintf( i8* %P, i8* getelementptr ([3 x i8], [3 x i8]* @G, i32 0, i32 0), i32* %X ) ; <i32>:1 [#uses=0]
+ ret void
+}
+
+; PR1307
+ at str = internal constant [5 x i8] c"foog\00"
+ at str1 = internal constant [8 x i8] c"blahhh!\00"
+ at str2 = internal constant [5 x i8] c"Ponk\00"
+
+define i8* @test1() {
+ %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str, i32 0, i32 2), i32 103 ) ; <i8*> [#uses=1]
+ ret i8* %tmp3
+
+; CHECK-LABEL: @test1(
+; CHECK: ret i8* getelementptr inbounds ([5 x i8], [5 x i8]* @str, i32 0, i32 3)
+}
+
+declare i8* @strchr(i8*, i32)
+
+define i8* @test2() {
+ %tmp3 = tail call i8* @strchr( i8* getelementptr ([8 x i8], [8 x i8]* @str1, i32 0, i32 2), i32 0 ) ; <i8*> [#uses=1]
+ ret i8* %tmp3
+
+; CHECK-LABEL: @test2(
+; CHECK: ret i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 7)
+}
+
+define i8* @test3() {
+entry:
+ %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8], [5 x i8]* @str2, i32 0, i32 1), i32 80 ) ; <i8*> [#uses=1]
+ ret i8* %tmp3
+
+; CHECK-LABEL: @test3(
+; CHECK: ret i8* null
+}
+
+ at _2E_str = external constant [5 x i8] ; <[5 x i8]*> [#uses=1]
+
+declare i32 @memcmp(i8*, i8*, i32) nounwind readonly
+
+define i1 @PR2341(i8** %start_addr) {
+entry:
+ %tmp4 = load i8*, i8** %start_addr, align 4 ; <i8*> [#uses=1]
+ %tmp5 = call i32 @memcmp( i8* %tmp4, i8* getelementptr ([5 x i8], [5 x i8]* @_2E_str, i32 0, i32 0), i32 4 ) nounwind readonly ; <i32> [#uses=1]
+ %tmp6 = icmp eq i32 %tmp5, 0 ; <i1> [#uses=1]
+ ret i1 %tmp6
+
+; CHECK-LABEL: @PR2341(
+; CHECK: i32
+}
+
+define i32 @PR4284() nounwind {
+entry:
+ %c0 = alloca i8, align 1 ; <i8*> [#uses=2]
+ %c2 = alloca i8, align 1 ; <i8*> [#uses=2]
+ store i8 64, i8* %c0
+ store i8 -127, i8* %c2
+ %call = call i32 @memcmp(i8* %c0, i8* %c2, i32 1) ; <i32> [#uses=1]
+ ret i32 %call
+
+; CHECK-LABEL: @PR4284(
+; CHECK: ret i32 -65
+}
+
+%struct.__sFILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64, %struct.pthread_mutex*, %struct.pthread*, i32, i32, %union.anon }
+%struct.__sbuf = type { i8*, i32, [4 x i8] }
+%struct.pthread = type opaque
+%struct.pthread_mutex = type opaque
+%union.anon = type { i64, [120 x i8] }
+ at .str13 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
+ at .str14 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
+
+define i32 @PR4641(i32 %argc, i8** %argv) nounwind {
+entry:
+ call void @exit(i32 0) nounwind
+ %cond392 = select i1 undef, i8* getelementptr ([2 x i8], [2 x i8]* @.str13, i32 0, i32 0), i8* getelementptr ([2 x i8], [2 x i8]* @.str14, i32 0, i32 0) ; <i8*> [#uses=1]
+ %call393 = call %struct.__sFILE* @fopen(i8* undef, i8* %cond392) nounwind ; <%struct.__sFILE*> [#uses=0]
+ unreachable
+}
+
+declare %struct.__sFILE* @fopen(i8*, i8*)
+
+declare void @exit(i32)
+
+define i32 @PR4645() {
+entry:
+ br label %if.then
+
+lor.lhs.false: ; preds = %while.body
+ br i1 undef, label %if.then, label %for.cond
+
+if.then: ; preds = %lor.lhs.false, %while.body
+ call void @exit(i32 1)
+ br label %for.cond
+
+for.cond: ; preds = %for.end, %if.then, %lor.lhs.false
+ %j.0 = phi i32 [ %inc47, %for.end ], [ 0, %if.then ], [ 0, %lor.lhs.false ] ; <i32> [#uses=1]
+ unreachable
+
+for.end: ; preds = %for.cond20
+ %inc47 = add i32 %j.0, 1 ; <i32> [#uses=1]
+ br label %for.cond
+}
+
+ at h = constant [2 x i8] c"h\00" ; <[2 x i8]*> [#uses=1]
+ at hel = constant [4 x i8] c"hel\00" ; <[4 x i8]*> [#uses=1]
+ at hello_u = constant [8 x i8] c"hello_u\00" ; <[8 x i8]*> [#uses=1]
+
+define i32 @MemCpy() {
+ %h_p = getelementptr [2 x i8], [2 x i8]* @h, i32 0, i32 0
+ %hel_p = getelementptr [4 x i8], [4 x i8]* @hel, i32 0, i32 0
+ %hello_u_p = getelementptr [8 x i8], [8 x i8]* @hello_u, i32 0, i32 0
+ %target = alloca [1024 x i8]
+ %target_p = getelementptr [1024 x i8], [1024 x i8]* %target, i32 0, i32 0
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 %target_p, i8* align 2 %h_p, i32 2, i1 false)
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %target_p, i8* align 4 %hel_p, i32 4, i1 false)
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %target_p, i8* align 8 %hello_u_p, i32 8, i1 false)
+ ret i32 0
+
+; CHECK-LABEL: @MemCpy(
+; CHECK-NOT: llvm.memcpy
+; CHECK: ret i32 0
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+
+declare i32 @strcmp(i8*, i8*) #0
+
+define void @test9(i8* %x) {
+; CHECK-LABEL: @test9(
+; CHECK-NOT: strcmp
+ %y = call i32 @strcmp(i8* %x, i8* %x) #1
+ ret void
+}
+
+; PR30484 - https://llvm.org/bugs/show_bug.cgi?id=30484
+; These aren't the library functions you're looking for...
+
+declare i32 @isdigit(i8)
+declare i32 @isascii(i8)
+declare i32 @toascii(i8)
+
+define i32 @fake_isdigit(i8 %x) {
+; CHECK-LABEL: @fake_isdigit(
+; CHECK-NEXT: [[Y:%.*]] = call i32 @isdigit(i8 %x)
+; CHECK-NEXT: ret i32 [[Y]]
+;
+ %y = call i32 @isdigit(i8 %x)
+ ret i32 %y
+}
+
+define i32 @fake_isascii(i8 %x) {
+; CHECK-LABEL: @fake_isascii(
+; CHECK-NEXT: [[Y:%.*]] = call i32 @isascii(i8 %x)
+; CHECK-NEXT: ret i32 [[Y]]
+;
+ %y = call i32 @isascii(i8 %x)
+ ret i32 %y
+}
+
+define i32 @fake_toascii(i8 %x) {
+; CHECK-LABEL: @fake_toascii(
+; CHECK-NEXT: [[Y:%.*]] = call i32 @toascii(i8 %x)
+; CHECK-NEXT: ret i32 [[Y]]
+;
+ %y = call i32 @toascii(i8 %x)
+ ret i32 %y
+}
+
+
+attributes #0 = { nobuiltin }
+attributes #1 = { builtin }
Added: llvm/trunk/test/Transforms/InstCombine/sincospi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sincospi.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sincospi.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sincospi.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,101 @@
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-FLOAT-IN-VEC
+; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios7.0 | FileCheck %s
+; RUN: opt -instcombine -S < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.8 | FileCheck %s --check-prefix=CHECK-NO-SINCOS
+; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios6.0 | FileCheck %s --check-prefix=CHECK-NO-SINCOS
+; RUN: opt -instcombine -S < %s -mtriple=x86_64-none-linux-gnu | FileCheck %s --check-prefix=CHECK-NO-SINCOS
+
+
+attributes #0 = { readnone nounwind }
+
+declare float @__sinpif(float %x) #0
+declare float @__cospif(float %x) #0
+
+declare double @__sinpi(double %x) #0
+declare double @__cospi(double %x) #0
+
+ at var32 = global float 0.0
+ at var64 = global double 0.0
+
+define float @test_instbased_f32() {
+ %val = load float, float* @var32
+ %sin = call float @__sinpif(float %val) #0
+ %cos = call float @__cospif(float %val) #0
+ %res = fadd float %sin, %cos
+ ret float %res
+; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
+; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
+; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
+; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
+
+; CHECK: [[VAL:%[a-z0-9]+]] = load float, float* @var32
+; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float [[VAL]])
+; CHECK: extractvalue { float, float } [[SINCOS]], 0
+; CHECK: extractvalue { float, float } [[SINCOS]], 1
+
+; CHECK-NO-SINCOS: call float @__sinpif
+; CHECK-NO-SINCOS: call float @__cospif
+}
+
+define float @test_constant_f32() {
+ %sin = call float @__sinpif(float 1.0) #0
+ %cos = call float @__cospif(float 1.0) #0
+ %res = fadd float %sin, %cos
+ ret float %res
+; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float 1.000000e+00)
+; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
+; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
+
+; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float 1.000000e+00)
+; CHECK: extractvalue { float, float } [[SINCOS]], 0
+; CHECK: extractvalue { float, float } [[SINCOS]], 1
+
+; CHECK-NO-SINCOS: call float @__sinpif
+; CHECK-NO-SINCOS: call float @__cospif
+}
+
+define double @test_instbased_f64() {
+ %val = load double, double* @var64
+ %sin = call double @__sinpi(double %val) #0
+ %cos = call double @__cospi(double %val) #0
+ %res = fadd double %sin, %cos
+ ret double %res
+; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
+; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VAL]])
+; CHECK-FLOAT-IN-VEC: extractvalue { double, double } [[SINCOS]], 0
+; CHECK-FLOAT-IN-VEC: extractvalue { double, double } [[SINCOS]], 1
+
+; CHECK: [[VAL:%[a-z0-9]+]] = load double, double* @var64
+; CHECK: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VAL]])
+; CHECK: extractvalue { double, double } [[SINCOS]], 0
+; CHECK: extractvalue { double, double } [[SINCOS]], 1
+
+; CHECK-NO-SINCOS: call double @__sinpi
+; CHECK-NO-SINCOS: call double @__cospi
+}
+
+define double @test_constant_f64() {
+ %sin = call double @__sinpi(double 1.0) #0
+ %cos = call double @__cospi(double 1.0) #0
+ %res = fadd double %sin, %cos
+ ret double %res
+; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double 1.000000e+00)
+; CHECK-FLOAT-IN-VEC: extractvalue { double, double } [[SINCOS]], 0
+; CHECK-FLOAT-IN-VEC: extractvalue { double, double } [[SINCOS]], 1
+
+; CHECK: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double 1.000000e+00)
+; CHECK: extractvalue { double, double } [[SINCOS]], 0
+; CHECK: extractvalue { double, double } [[SINCOS]], 1
+
+; CHECK-NO-SINCOS: call double @__sinpi
+; CHECK-NO-SINCOS: call double @__cospi
+}
+
+define double @test_fptr(double (double)* %fptr, double %p1) {
+ %sin = call double @__sinpi(double %p1) #0
+ %cos = call double %fptr(double %p1)
+ %res = fadd double %sin, %cos
+ ret double %res
+; CHECK-LABEL: @test_fptr
+; CHECK: __sinpi
+}
Added: llvm/trunk/test/Transforms/InstCombine/sink-alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sink-alloca.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sink-alloca.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sink-alloca.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,52 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i686-unknown-linux-gnu"
+
+; Check that instcombine doesn't sink dynamic allocas across llvm.stacksave.
+
+; Helper to generate branch conditions.
+declare i1 @cond()
+
+declare i32* @use_and_return(i32*)
+
+declare i8* @llvm.stacksave() #0
+
+declare void @llvm.stackrestore(i8*) #0
+
+define void @foo(i32 %x) {
+entry:
+ %c1 = call i1 @cond()
+ br i1 %c1, label %ret, label %nonentry
+
+nonentry: ; preds = %entry
+ %argmem = alloca i32, i32 %x, align 4
+ %sp = call i8* @llvm.stacksave()
+ %c2 = call i1 @cond()
+ br i1 %c2, label %ret, label %sinktarget
+
+sinktarget: ; preds = %nonentry
+ ; Arrange for there to be a single use of %argmem by returning it.
+ %p = call i32* @use_and_return(i32* nonnull %argmem)
+ store i32 13, i32* %p, align 4
+ call void @llvm.stackrestore(i8* %sp)
+ %0 = call i32* @use_and_return(i32* %p)
+ br label %ret
+
+ret: ; preds = %sinktarget, %nonentry, %entry
+ ret void
+}
+
+; CHECK-LABEL: define void @foo(i32 %x)
+; CHECK: nonentry:
+; CHECK: %argmem = alloca i32, i32 %x
+; CHECK: %sp = call i8* @llvm.stacksave()
+; CHECK: %c2 = call i1 @cond()
+; CHECK: br i1 %c2, label %ret, label %sinktarget
+; CHECK: sinktarget:
+; CHECK: %p = call i32* @use_and_return(i32* nonnull %argmem)
+; CHECK: store i32 13, i32* %p
+; CHECK: call void @llvm.stackrestore(i8* %sp)
+; CHECK: %0 = call i32* @use_and_return(i32* %p)
+
+attributes #0 = { nounwind }
Added: llvm/trunk/test/Transforms/InstCombine/sink-into-catchswitch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sink-into-catchswitch.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sink-into-catchswitch.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sink-into-catchswitch.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc18.0.0"
+
+%struct.B = type { i64, i64 }
+
+define void @test1(%struct.B* %p) personality i32 (...)* @__CxxFrameHandler3 {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: invoke.cont:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast %struct.B* [[P:%.*]] to <2 x i64>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 8
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
+; CHECK-NEXT: invoke void @throw()
+; CHECK-NEXT: to label [[UNREACHABLE:%.*]] unwind label [[CATCH_DISPATCH:%.*]]
+; CHECK: catch.dispatch:
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label %invoke.cont1] unwind label [[EHCLEANUP:%.*]]
+; CHECK: invoke.cont1:
+; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS]] [i8* null, i32 64, i8* null]
+; CHECK-NEXT: invoke void @throw() [ "funclet"(token [[CATCH]]) ]
+; CHECK-NEXT: to label [[UNREACHABLE]] unwind label [[EHCLEANUP]]
+; CHECK: ehcleanup:
+; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[TMP2]], [[CATCH_DISPATCH]] ], [ 9, [[INVOKE_CONT1:%.*]] ]
+; CHECK-NEXT: [[CLEANUP:%.*]] = cleanuppad within none []
+; CHECK-NEXT: call void @release(i64 [[PHI]]) [ "funclet"(token [[CLEANUP]]) ]
+; CHECK-NEXT: cleanupret from [[CLEANUP]] unwind to caller
+; CHECK: unreachable:
+; CHECK-NEXT: unreachable
+;
+invoke.cont:
+ %0 = bitcast %struct.B* %p to <2 x i64>*
+ %1 = load <2 x i64>, <2 x i64>* %0, align 8
+ %2 = extractelement <2 x i64> %1, i32 0
+ invoke void @throw()
+ to label %unreachable unwind label %catch.dispatch
+
+catch.dispatch: ; preds = %invoke.cont
+ %cs = catchswitch within none [label %invoke.cont1] unwind label %ehcleanup
+
+invoke.cont1: ; preds = %catch.dispatch
+ %catch = catchpad within %cs [i8* null, i32 64, i8* null]
+ invoke void @throw() [ "funclet"(token %catch) ]
+ to label %unreachable unwind label %ehcleanup
+
+ehcleanup: ; preds = %invoke.cont1, %catch.dispatch
+ %phi = phi i64 [ %2, %catch.dispatch ], [ 9, %invoke.cont1 ]
+ %cleanup = cleanuppad within none []
+ call void @release(i64 %phi) [ "funclet"(token %cleanup) ]
+ cleanupret from %cleanup unwind to caller
+
+unreachable: ; preds = %invoke.cont1, %invoke.cont
+ unreachable
+}
+
+declare i32 @__CxxFrameHandler3(...)
+declare void @throw()
+declare void @release(i64)
Added: llvm/trunk/test/Transforms/InstCombine/sink_instruction.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sink_instruction.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sink_instruction.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sink_instruction.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,79 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+;; This tests that the instructions in the entry blocks are sunk into each
+;; arm of the 'if'.
+
+define i32 @test1(i1 %C, i32 %A, i32 %B) {
+; CHECK-LABEL: @test1(
+entry:
+ %tmp.2 = sdiv i32 %A, %B ; <i32> [#uses=1]
+ %tmp.9 = add i32 %B, %A ; <i32> [#uses=1]
+ br i1 %C, label %then, label %endif
+
+then: ; preds = %entry
+ ret i32 %tmp.9
+
+endif: ; preds = %entry
+; CHECK: sdiv i32
+; CHECK-NEXT: ret i32
+ ret i32 %tmp.2
+}
+
+
+;; PHI use, sink divide before call.
+define i32 @test2(i32 %x) nounwind ssp {
+; CHECK-LABEL: @test2(
+; CHECK-NOT: sdiv i32
+entry:
+ br label %bb
+
+bb: ; preds = %bb2, %entry
+ %x_addr.17 = phi i32 [ %x, %entry ], [ %x_addr.0, %bb2 ] ; <i32> [#uses=4]
+ %i.06 = phi i32 [ 0, %entry ], [ %4, %bb2 ] ; <i32> [#uses=1]
+ %0 = add nsw i32 %x_addr.17, 1 ; <i32> [#uses=1]
+ %1 = sdiv i32 %0, %x_addr.17 ; <i32> [#uses=1]
+ %2 = icmp eq i32 %x_addr.17, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb1, label %bb2
+
+bb1: ; preds = %bb
+; CHECK: bb1:
+; CHECK-NEXT: add nsw i32 %x_addr.17, 1
+; CHECK-NEXT: sdiv i32
+; CHECK-NEXT: tail call i32 @bar()
+ %3 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
+ br label %bb2
+
+bb2: ; preds = %bb, %bb1
+ %x_addr.0 = phi i32 [ %1, %bb1 ], [ %x_addr.17, %bb ] ; <i32> [#uses=2]
+ %4 = add nsw i32 %i.06, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %4, 1000000 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb4, label %bb
+
+bb4: ; preds = %bb2
+ ret i32 %x_addr.0
+}
+
+declare i32 @bar()
+
+define i32 @test3(i32* nocapture readonly %P, i32 %i) {
+entry:
+ %idxprom = sext i32 %i to i64
+ %arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom
+ %0 = load i32, i32* %arrayidx, align 4
+ switch i32 %i, label %sw.epilog [
+ i32 5, label %sw.bb
+ i32 2, label %sw.bb
+ ]
+
+sw.bb: ; preds = %entry, %entry
+; CHECK-LABEL: sw.bb:
+; CHECK: %idxprom = sext i32 %i to i64
+; CHECK: %arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom
+; CHECK: %0 = load i32, i32* %arrayidx, align 4
+ %add = add nsw i32 %0, %i
+ br label %sw.epilog
+
+sw.epilog: ; preds = %entry, %sw.bb
+ %sum.0 = phi i32 [ %add, %sw.bb ], [ 0, %entry ]
+ ret i32 %sum.0
+}
Added: llvm/trunk/test/Transforms/InstCombine/sitofp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sitofp.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sitofp.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/sitofp.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,218 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i1 @test1(i8 %A) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: ret i1 true
+;
+ %B = sitofp i8 %A to double
+ %C = fcmp ult double %B, 128.0
+ ret i1 %C
+}
+
+define i1 @test2(i8 %A) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: ret i1 true
+;
+ %B = sitofp i8 %A to double
+ %C = fcmp ugt double %B, -128.1
+ ret i1 %C
+}
+
+define i1 @test3(i8 %A) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: ret i1 true
+;
+ %B = sitofp i8 %A to double
+ %C = fcmp ule double %B, 127.0
+ ret i1 %C
+}
+
+define i1 @test4(i8 %A) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A:%.*]], 127
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %B = sitofp i8 %A to double
+ %C = fcmp ult double %B, 127.0
+ ret i1 %C
+}
+
+define i32 @test5(i32 %A) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: ret i32 [[A:%.*]]
+;
+ %B = sitofp i32 %A to double
+ %C = fptosi double %B to i32
+ %D = uitofp i32 %C to double
+ %E = fptoui double %D to i32
+ ret i32 %E
+}
+
+define i32 @test6(i32 %A) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: [[ADDCONV:%.*]] = and i32 [[A:%.*]], 39
+; CHECK-NEXT: ret i32 [[ADDCONV]]
+;
+ %B = and i32 %A, 7
+ %C = and i32 %A, 32
+ %D = sitofp i32 %B to double
+ %E = sitofp i32 %C to double
+ %F = fadd double %D, %E
+ %G = fptosi double %F to i32
+ ret i32 %G
+}
+
+define i32 @test7(i32 %A) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: ret i32 [[A:%.*]]
+;
+ %B = sitofp i32 %A to double
+ %C = fptoui double %B to i32
+ ret i32 %C
+}
+
+define i32 @test8(i32 %A) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: ret i32 [[A:%.*]]
+;
+ %B = uitofp i32 %A to double
+ %C = fptosi double %B to i32
+ ret i32 %C
+}
+
+define i32 @test9(i8 %A) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT: [[C:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = sitofp i8 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
+}
+
+define i32 @test10(i8 %A) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT: [[C:%.*]] = sext i8 [[A:%.*]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = sitofp i8 %A to float
+ %C = fptosi float %B to i32
+ ret i32 %C
+}
+
+; If the input value is outside of the range of the output cast, it's
+; undefined behavior, so we can assume it fits.
+
+define i8 @test11(i32 %A) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: [[C:%.*]] = trunc i32 [[A:%.*]] to i8
+; CHECK-NEXT: ret i8 [[C]]
+;
+ %B = sitofp i32 %A to float
+ %C = fptosi float %B to i8
+ ret i8 %C
+}
+
+; If the input value is negative, it'll be outside the range of the
+; output cast, and thus undefined behavior.
+
+define i32 @test12(i8 %A) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: [[C:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = sitofp i8 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
+}
+
+; This can't fold because the 25-bit input doesn't fit in the mantissa.
+
+define i32 @test13(i25 %A) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT: [[B:%.*]] = uitofp i25 [[A:%.*]] to float
+; CHECK-NEXT: [[C:%.*]] = fptoui float [[B]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = uitofp i25 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
+}
+
+; But this one can.
+
+define i32 @test14(i24 %A) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT: [[C:%.*]] = zext i24 [[A:%.*]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = uitofp i24 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
+}
+
+; And this one can too.
+
+define i24 @test15(i32 %A) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: [[C:%.*]] = trunc i32 [[A:%.*]] to i24
+; CHECK-NEXT: ret i24 [[C]]
+;
+ %B = uitofp i32 %A to float
+ %C = fptoui float %B to i24
+ ret i24 %C
+}
+
+; This can fold because the 25-bit input is signed and we discard the sign bit.
+
+define i32 @test16(i25 %A) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: [[C:%.*]] = zext i25 [[A:%.*]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = sitofp i25 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
+}
+
+; This can't fold because the 26-bit input won't fit the mantissa
+; even after discarding the signed bit.
+
+define i32 @test17(i26 %A) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[B:%.*]] = sitofp i26 [[A:%.*]] to float
+; CHECK-NEXT: [[C:%.*]] = fptoui float [[B]] to i32
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %B = sitofp i26 %A to float
+ %C = fptoui float %B to i32
+ ret i32 %C
+}
+
+; This can fold because the 54-bit output is signed and we discard the sign bit.
+
+define i54 @test18(i64 %A) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: [[C:%.*]] = trunc i64 [[A:%.*]] to i54
+; CHECK-NEXT: ret i54 [[C]]
+;
+ %B = sitofp i64 %A to double
+ %C = fptosi double %B to i54
+ ret i54 %C
+}
+
+; This can't fold because the 55-bit output won't fit the mantissa
+; even after discarding the sign bit.
+
+define i55 @test19(i64 %A) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT: [[B:%.*]] = sitofp i64 [[A:%.*]] to double
+; CHECK-NEXT: [[C:%.*]] = fptosi double [[B]] to i55
+; CHECK-NEXT: ret i55 [[C]]
+;
+ %B = sitofp i64 %A to double
+ %C = fptosi double %B to i55
+ ret i55 %C
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/smax-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/smax-icmp.ll?rev=358552&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/smax-icmp.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/smax-icmp.ll Tue Apr 16 21:52:47 2019
@@ -0,0 +1,234 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+; If we have an smax feeding a signed or equality icmp that shares an
+; operand with the smax, the compare should always be folded.
+; Test all 4 foldable predicates (eq,ne,sgt,sle) * 4 commutation
+; possibilities for each predicate. Note that folds to true/false
+; (predicate = sge/slt) or folds to an existing instruction should be
+; handled by InstSimplify.
+
+; smax(X, Y) == X --> X >= Y
+
+define i1 @eq_smax1(i32 %x, i32 %y) {
+; CHECK-LABEL: @eq_smax1(
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 %x, %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp eq i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @eq_smax2(i32 %x, i32 %y) {
+; CHECK-LABEL: @eq_smax2(
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 %x, %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp eq i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Disguise the icmp predicate by commuting the max op to the RHS.
+
+define i1 @eq_smax3(i32 %a, i32 %y) {
+; CHECK-LABEL: @eq_smax3(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp eq i32 %x, %sel
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @eq_smax4(i32 %a, i32 %y) {
+; CHECK-LABEL: @eq_smax4(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp eq i32 %x, %sel
+ ret i1 %cmp2
+}
+
+; smax(X, Y) <= X --> X >= Y
+
+define i1 @sle_smax1(i32 %x, i32 %y) {
+; CHECK-LABEL: @sle_smax1(
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 %x, %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp sle i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @sle_smax2(i32 %x, i32 %y) {
+; CHECK-LABEL: @sle_smax2(
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 %x, %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp sle i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Disguise the icmp predicate by commuting the max op to the RHS.
+
+define i1 @sle_smax3(i32 %a, i32 %y) {
+; CHECK-LABEL: @sle_smax3(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp sge i32 %x, %sel
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @sle_smax4(i32 %a, i32 %y) {
+; CHECK-LABEL: @sle_smax4(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp sge i32 %x, %sel
+ ret i1 %cmp2
+}
+
+; smax(X, Y) != X --> X < Y
+
+define i1 @ne_smax1(i32 %x, i32 %y) {
+; CHECK-LABEL: @ne_smax1(
+; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 %x, %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp ne i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @ne_smax2(i32 %x, i32 %y) {
+; CHECK-LABEL: @ne_smax2(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 %y, %x
+; CHECK-NEXT: ret i1 [[CMP1]]
+;
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp ne i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Disguise the icmp predicate by commuting the max op to the RHS.
+
+define i1 @ne_smax3(i32 %a, i32 %y) {
+; CHECK-LABEL: @ne_smax3(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp ne i32 %x, %sel
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @ne_smax4(i32 %a, i32 %y) {
+; CHECK-LABEL: @ne_smax4(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP1]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp ne i32 %x, %sel
+ ret i1 %cmp2
+}
+
+; smax(X, Y) > X --> X < Y
+
+define i1 @sgt_smax1(i32 %x, i32 %y) {
+; CHECK-LABEL: @sgt_smax1(
+; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 %x, %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp sgt i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @sgt_smax2(i32 %x, i32 %y) {
+; CHECK-LABEL: @sgt_smax2(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 %y, %x
+; CHECK-NEXT: ret i1 [[CMP1]]
+;
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp sgt i32 %sel, %x
+ ret i1 %cmp2
+}
+
+; Disguise the icmp predicate by commuting the max op to the RHS.
+
+define i1 @sgt_smax3(i32 %a, i32 %y) {
+; CHECK-LABEL: @sgt_smax3(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP2]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp1, i32 %x, i32 %y
+ %cmp2 = icmp slt i32 %x, %sel
+ ret i1 %cmp2
+}
+
+; Commute max operands.
+
+define i1 @sgt_smax4(i32 %a, i32 %y) {
+; CHECK-LABEL: @sgt_smax4(
+; CHECK-NEXT: [[X:%.*]] = add i32 %a, 3
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], %y
+; CHECK-NEXT: ret i1 [[CMP1]]
+;
+ %x = add i32 %a, 3 ; thwart complexity-based canonicalization
+ %cmp1 = icmp sgt i32 %y, %x
+ %sel = select i1 %cmp1, i32 %y, i32 %x
+ %cmp2 = icmp slt i32 %x, %sel
+ ret i1 %cmp2
+}
+
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