[PATCH] D60799: Add a getSizeInBits() accessor to MachineMemOperand. NFC.

Amara Emerson via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 16 15:17:14 PDT 2019


aemerson created this revision.
aemerson added reviewers: arsenm, qcolombet, dsanders.
aemerson added a project: LLVM.
Herald added subscribers: Petar.Avramovic, hiraditya, wdng.

Cleans up a bunch of places where we do getSize() * 8.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60799

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/include/llvm/CodeGen/MachineMemOperand.h
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp


Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1022,13 +1022,13 @@
       const MachineMemOperand &MMO = **MI->memoperands_begin();
       if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
           MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
-        if (MMO.getSize() * 8 >= ValTy.getSizeInBits())
+        if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
           report("Generic extload must have a narrower memory type", MI);
       } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
-        if (MMO.getSize() > (ValTy.getSizeInBits() + 7) / 8)
+        if (MMO.getSizeInBits() > (ValTy.getSizeInBits() + 7))
           report("load memory size cannot exceed result size", MI);
       } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
-        if ((ValTy.getSizeInBits() + 7) / 8 < MMO.getSize())
+        if ((ValTy.getSizeInBits() + 7) < MMO.getSizeInBits())
           report("store memory size cannot exceed value size", MI);
       }
     }
Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -603,7 +603,7 @@
 
     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
     auto &MMO = **MI.memoperands_begin();
-    if (MMO.getSize() * 8 == NarrowSize) {
+    if (MMO.getSizeInBits() == NarrowSize) {
       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
     } else {
       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
@@ -1496,7 +1496,7 @@
     LLT DstTy = MRI.getType(DstReg);
     auto &MMO = **MI.memoperands_begin();
 
-    if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
+    if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
         // This load needs splitting into power of 2 sized loads.
         if (DstTy.isVector())
@@ -1551,8 +1551,8 @@
     }
 
     if (DstTy.isScalar()) {
-      unsigned TmpReg = MRI.createGenericVirtualRegister(
-          LLT::scalar(MMO.getSize() /* in bytes */ * 8));
+      unsigned TmpReg =
+          MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
       switch (MI.getOpcode()) {
       default:
@@ -1584,7 +1584,7 @@
     unsigned PtrReg = MI.getOperand(1).getReg();
     LLT SrcTy = MRI.getType(SrcReg);
     MachineMemOperand &MMO = **MI.memoperands_begin();
-    if (SrcTy.getSizeInBits() != MMO.getSize() /* in bytes */ * 8)
+    if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
       return UnableToLegalize;
     if (SrcTy.isVector())
       return UnableToLegalize;
Index: llvm/include/llvm/CodeGen/MachineMemOperand.h
===================================================================
--- llvm/include/llvm/CodeGen/MachineMemOperand.h
+++ llvm/include/llvm/CodeGen/MachineMemOperand.h
@@ -220,6 +220,9 @@
   /// Return the size in bytes of the memory reference.
   uint64_t getSize() const { return Size; }
 
+  /// Return the size in bits of the memory reference.
+  uint64_t getSizeInBits() const { return Size * 8; }
+
   /// Return the minimum known alignment in bytes of the actual memory
   /// reference.
   uint64_t getAlignment() const;
Index: llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
===================================================================
--- llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
+++ llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
@@ -437,15 +437,15 @@
 
       unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
       if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
-          MMO->getSize() * 8 != Size) {
+          MMO->getSizeInBits() != Size) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
-                 MMO->getSize() * 8 >= Size) {
+                 MMO->getSizeInBits() >= Size) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
-                 MMO->getSize() * 8 <= Size)
+                 MMO->getSizeInBits() <= Size)
         if (handleReject() == RejectAndGiveUp)
           return false;
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D60799.195472.patch
Type: text/x-patch
Size: 4476 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190416/74a03e4e/attachment.bin>


More information about the llvm-commits mailing list