[PATCH] D60294: [DAGCombiner] [CodeGenPrepare] WIP/RFC Splitting large offsets from base addresses

[Luís Marques via Phabricator via llvm-commits]

luismarques updated this revision to Diff 195351.
luismarques added a comment.
Herald added a subscriber: qcolombet.

This updates the patch to:

1. Add a check for `N0.hasOneUse()`, as suggested by Eli Friedman;
2. Changes the shuffling indices of the ARM `vector-spilling.ll` test, to ensure the desired multi-register vector spills and restores are generated;
3. Updates the ARM `misched-fusion-aes.ll` AES fusion test checks to account for the new instruction scheduling. We still seem to have the desired number of fusable instructions, just in a different order.

Those two tests would remain broken even if you always gave the OK to reassociate in `reassociationCanBreakAddressingModePattern`. With these changes the remaining failing tests should be:

Failing Tests (3):

  LLVM :: CodeGen/AMDGPU/salu-to-valu.ll
  LLVM :: CodeGen/SystemZ/int-sub-05.ll
  LLVM :: CodeGen/SystemZ/int-add-08.ll

I'll look more closely into those tests. If necessary we can tweak the reassociation gating for those.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60294/new/

https://reviews.llvm.org/D60294

Files:
  lib/CodeGen/CodeGenPrepare.cpp
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/ARM/misched-fusion-aes.ll
  test/CodeGen/ARM/vector-spilling.ll
  test/CodeGen/RISCV/split-offsets-1.ll
  test/CodeGen/RISCV/split-offsets-2.ll

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