[PATCH] D60694: [ARM] Introduce separate features for FP registers.

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrVFP.td:2357
  let Defs = [FPSCR] in {
+   let Predicates = [HasFPRegs] in
    // Application level GPR -> FPSCR
----------------
This only applies to VMSR at the moment, should it also cover the other four?


================
Comment at: llvm/test/MC/ARM/mve-vmov-lane.s:14
+
+vmov.32 r0, q0[2]
+// V80M-ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires: armv8.1m.main with FP or MVE
----------------
I don't think this instruction has been added at this point in the patch series, so this test should probably be moved to a later patch.


================
Comment at: llvm/test/MC/Disassembler/ARM/mve-vmov-lane.txt:6
+
+# The disassembly for this instruction varies between v8.1M and other
+# architectures. In v8.1M (with either scalar flotaing point, MVE or both), we
----------------
Again, I think this need to be in a later patch.


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  https://reviews.llvm.org/D60694/new/

https://reviews.llvm.org/D60694