[PATCH] D60705: [ARM] Turn some undefined encoding bits into mandatory 1s.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This affects Thumb-2 ORR instructions, in which bit 15 now has to be 1
instead of being unspecified; and move / shift instructions, in which
it has to be 0. This change comes from Arm v8.1-M, in which encodings
with the other values of those bits will now be used for different
instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60705

Files:
  llvm/lib/Target/ARM/ARMInstrThumb2.td


Index: llvm/lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -581,7 +581,7 @@
 /// changed to modify CPSR.
 multiclass T2I_bin_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
-                     SDPatternOperator opnode, bit Commutable = 0,
+                     SDPatternOperator opnode, bit SB, bit Commutable = 0,
                      string wide = ""> {
    // shifted imm
    def ri : T2sTwoRegImm<
@@ -603,6 +603,7 @@
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
+     let Inst{15} = SB;
      let Inst{14-12} = 0b000; // imm3
      let Inst{7-6} = 0b00; // imm2
      let Inst{5-4} = 0b00; // type
@@ -616,6 +617,7 @@
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
+     let Inst{15} = SB;
    }
   // Assembly aliases for optional destination operand when it's the same
   // as the source operand.
@@ -637,8 +639,8 @@
 //  the ".w" suffix to indicate that they are wide.
 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
-                     SDPatternOperator opnode, bit Commutable = 0> :
-    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
+                     SDPatternOperator opnode, bit SB, bit Commutable = 0> :
+    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, SB, Commutable, ".w"> {
   // Assembler aliases w/ the ".w" suffix.
   def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
      (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
@@ -879,6 +881,7 @@
      let Inst{31-27} = 0b11101;
      let Inst{26-21} = 0b010010;
      let Inst{19-16} = 0b1111; // Rn
+     let Inst{15}    = 0b0;
      let Inst{5-4} = opcod;
    }
    // register
@@ -1871,6 +1874,7 @@
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b0010;
   let Inst{19-16} = 0b1111; // Rn
+  let Inst{15} = 0;
   let Inst{14-12} = 0b000;
   let Inst{7-4} = 0b0000;
 }
@@ -2399,6 +2403,7 @@
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b0010;
   let Inst{19-16} = 0b1111; // Rn
+  let Inst{15} = 0;
   let Inst{14-12} = 0b000;
   let Inst{7-4} = 0b0011;
 }
@@ -2442,15 +2447,15 @@
 //
 
 defm t2AND  : T2I_bin_w_irs<0b0000, "and",
-                            IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>;
+                            IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, ?, 1>;
 defm t2ORR  : T2I_bin_w_irs<0b0010, "orr",
-                            IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>;
+                            IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 0, 1>;
 defm t2EOR  : T2I_bin_w_irs<0b0100, "eor",
-                            IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>;
+                            IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, ?, 1>;
 
 defm t2BIC  : T2I_bin_w_irs<0b0001, "bic",
                             IIC_iBITi, IIC_iBITr, IIC_iBITsi,
-                            BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
+                            BinOpFrag<(and node:$LHS, (not node:$RHS))>, ?>;
 
 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
@@ -2543,7 +2548,7 @@
 
 defm t2ORN  : T2I_bin_irs<0b0011, "orn",
                           IIC_iBITi, IIC_iBITr, IIC_iBITsi,
-                          BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
+                          BinOpFrag<(or node:$LHS, (not node:$RHS))>, ?, 0, "">;
 
 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
 /// unary operation that produces a value. These are predicable and can be


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