[PATCH] D60691: [ARM] Replace fp-only-sp and d16 with fp64 and d32.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer.
Herald added subscribers: llvm-commits, cfe-commits, Petar.Avramovic, zzheng, hiraditya, kristof.beyls, eraman, javed.absar, srhines.
Herald added projects: clang, LLVM.

Those two subtarget features were awkward because their semantics are
reversed: each one indicates the _lack_ of support for something in
the architecture, rather than the presence. As a consequence, you
don't get the behavior you want if you combine two sets of feature
bits.

Each SubtargetFeature for an FP architecture version now comes in four
versions, one for each combination of those options. So you can still
say (for example) '+vfp2' in a feature string and it will mean what
it's always meant, but there's a new string '+vfp2d16sp' meaning the
version without those extra options.

A lot of this change is just mechanically replacing positive checks
for the old features with negative checks for the new ones. But one
more interesting change is that I've rearranged getFPUFeatures() so
that the main FPU feature is appended to the output list *before*
rather than after the features derived from the Restriction field, so
that -fp64 and -d32 can override defaults added by the main feature.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60691

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/CodeGen/arm-target-features.c
  clang/test/Driver/arm-mfpu.c
  llvm/include/llvm/MC/MCSubtargetInfo.h
  llvm/lib/MC/MCSubtargetInfo.cpp
  llvm/lib/Object/ELFObjectFile.cpp
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMAsmPrinter.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMFastISel.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstructionSelector.cpp
  llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
  llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
  llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
  llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
  llvm/test/CodeGen/ARM/arm32-rounding.ll
  llvm/test/CodeGen/ARM/build-attributes.ll
  llvm/test/CodeGen/ARM/fast-isel-call.ll
  llvm/test/CodeGen/ARM/float-helpers.s
  llvm/test/CodeGen/ARM/fp-only-sp.ll
  llvm/test/CodeGen/ARM/fp16-instructions.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/fpconv.ll
  llvm/test/CodeGen/ARM/half.ll
  llvm/test/CodeGen/ARM/inlineasm-X-allocation.ll
  llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
  llvm/test/CodeGen/ARM/no-fpu.ll
  llvm/test/CodeGen/Thumb2/aapcs.ll
  llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
  llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll
  llvm/test/CodeGen/Thumb2/t2sizereduction.mir
  llvm/test/MC/ARM/armv8.3a-js.s
  llvm/test/MC/ARM/d16.s
  llvm/test/MC/ARM/invalid-neon-v8.s
  llvm/test/MC/ARM/single-precision-fp.s
  llvm/test/MC/ARM/vldm-vstm-diags.s
  llvm/test/Transforms/Inline/ARM/inline-fp.ll
  llvm/test/Transforms/LoopUnroll/runtime-epilog-debuginfo.ll

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