[PATCH] D58982: DAG: allow DAG pointer size different from memory representation.

Mon Apr 15 04:04:54 PDT 2019

arsenm added inline comments.

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Comment at: llvm/include/llvm/CodeGen/Analysis.h:76-81
+/// Variant of ComputeValueVTs that also produces the memory VTs.
+void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty,
+                     SmallVectorImpl<EVT> &ValueVTs,
+                     SmallVectorImpl<EVT> *MemVTs,
+                     SmallVectorImpl<uint64_t> *Offsets = nullptr,
+                     uint64_t StartingOffset = 0);
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Can you just consolidate this into one version?

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Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:245
+  MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
     return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
   }
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Shouldn't this be the ABI size in bits? At one point we were using 32-bit pointers with 64-bit ABI alignment for something similar

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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:1625-1626
+      SDValue Val = RetOp.getValue(i);
+      if (MemVTs[i] != ValueVTs[i])
+        Val = DAG.getZExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]);
+      Chains[i] = DAG.getStore(Chain, getCurSDLoc(), Val,
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It seems to me that this is target specific to assume zext

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58982/new/

https://reviews.llvm.org/D58982