[llvm] r357584 - [MIPS GlobalISel] Select floating point arithmetic operations
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 3 07:12:59 PDT 2019
Author: petar.avramovic
Date: Wed Apr 3 07:12:59 2019
New Revision: 357584
URL: http://llvm.org/viewvc/llvm-project?rev=357584&view=rev
Log:
[MIPS GlobalISel] Select floating point arithmetic operations
Select 32 and 64 bit floating point add, sub, mul and div for MIPS32.
Differential Revision: https://reviews.llvm.org/D60191
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=357584&r1=357583&r2=357584&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Wed Apr 3 07:12:59 2019
@@ -81,9 +81,6 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
.legalFor({s32})
.clampScalar(0, s32, s32);
- getActionDefinitionsBuilder(G_FCONSTANT)
- .legalFor({s32, s64});
-
getActionDefinitionsBuilder(G_GEP)
.legalFor({{p0, s32}});
@@ -93,6 +90,13 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
getActionDefinitionsBuilder(G_GLOBAL_VALUE)
.legalFor({p0});
+ // FP instructions
+ getActionDefinitionsBuilder(G_FCONSTANT)
+ .legalFor({s32, s64});
+
+ getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
+ .legalFor({s32, s64});
+
computeTables();
verify(*ST.getInstrInfo());
}
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp?rev=357584&r1=357583&r2=357584&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp Wed Apr 3 07:12:59 2019
@@ -81,6 +81,7 @@ const RegisterBank &MipsRegisterBankInfo
case Mips::SP32RegClassID:
return getRegBank(Mips::GPRBRegBankID);
case Mips::FGRCCRegClassID:
+ case Mips::FGR32RegClassID:
case Mips::FGR64RegClassID:
case Mips::AFGR64RegClassID:
return getRegBank(Mips::FPRBRegBankID);
@@ -128,9 +129,19 @@ MipsRegisterBankInfo::getInstrMapping(co
case G_UREM:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
break;
+ case G_FADD:
+ case G_FSUB:
+ case G_FMUL:
+ case G_FDIV: {
+ unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+ assert((Size == 32 || Size == 64) && "Unsupported floating point size");
+ OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
+ : &Mips::ValueMappings[Mips::DPRIdx];
+ break;
+ }
case G_FCONSTANT: {
- LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- unsigned Size = Ty.getSizeInBits();
+ unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+ assert((Size == 32 || Size == 64) && "Unsupported floating point size");
const RegisterBankInfo::ValueMapping *FPRValueMapping =
Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
: &Mips::ValueMappings[Mips::DPRIdx];
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir?rev=357584&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir Wed Apr 3 07:12:59 2019
@@ -0,0 +1,263 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+ define void @float_add() {entry: ret void}
+ define void @float_sub() {entry: ret void}
+ define void @float_mul() {entry: ret void}
+ define void @float_div() {entry: ret void}
+ define void @double_add() {entry: ret void}
+ define void @double_sub() {entry: ret void}
+ define void @double_mul() {entry: ret void}
+ define void @double_div() {entry: ret void}
+
+...
+---
+name: float_add
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_add
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP32: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FADD_S]]
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_add
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP64: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FADD_S]]
+ ; FP64: RetRA implicit $f0
+ %0:fprb(s32) = COPY $f12
+ %1:fprb(s32) = COPY $f14
+ %2:fprb(s32) = G_FADD %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_sub
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_sub
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP32: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FSUB_S]]
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_sub
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP64: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FSUB_S]]
+ ; FP64: RetRA implicit $f0
+ %0:fprb(s32) = COPY $f12
+ %1:fprb(s32) = COPY $f14
+ %2:fprb(s32) = G_FSUB %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_mul
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_mul
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP32: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FMUL_S]]
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_mul
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP64: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FMUL_S]]
+ ; FP64: RetRA implicit $f0
+ %0:fprb(s32) = COPY $f12
+ %1:fprb(s32) = COPY $f14
+ %2:fprb(s32) = G_FMUL %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_div
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_div
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP32: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FDIV_S]]
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_div
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+ ; FP64: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FDIV_S]]
+ ; FP64: RetRA implicit $f0
+ %0:fprb(s32) = COPY $f12
+ %1:fprb(s32) = COPY $f14
+ %2:fprb(s32) = G_FDIV %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: double_add
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_add
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
+ ; FP32: [[FADD_D32_:%[0-9]+]]:afgr64 = FADD_D32 [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FADD_D32_]]
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_add
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
+ ; FP64: [[FADD_D64_:%[0-9]+]]:fgr64 = FADD_D64 [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FADD_D64_]]
+ ; FP64: RetRA implicit $d0
+ %0:fprb(s64) = COPY $d6
+ %1:fprb(s64) = COPY $d7
+ %2:fprb(s64) = G_FADD %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_sub
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_sub
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
+ ; FP32: [[FSUB_D32_:%[0-9]+]]:afgr64 = FSUB_D32 [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FSUB_D32_]]
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_sub
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
+ ; FP64: [[FSUB_D64_:%[0-9]+]]:fgr64 = FSUB_D64 [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FSUB_D64_]]
+ ; FP64: RetRA implicit $d0
+ %0:fprb(s64) = COPY $d6
+ %1:fprb(s64) = COPY $d7
+ %2:fprb(s64) = G_FSUB %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_mul
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_mul
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
+ ; FP32: [[FMUL_D32_:%[0-9]+]]:afgr64 = FMUL_D32 [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FMUL_D32_]]
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_mul
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
+ ; FP64: [[FMUL_D64_:%[0-9]+]]:fgr64 = FMUL_D64 [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FMUL_D64_]]
+ ; FP64: RetRA implicit $d0
+ %0:fprb(s64) = COPY $d6
+ %1:fprb(s64) = COPY $d7
+ %2:fprb(s64) = G_FMUL %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_div
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_div
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
+ ; FP32: [[FDIV_D32_:%[0-9]+]]:afgr64 = FDIV_D32 [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FDIV_D32_]]
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_div
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
+ ; FP64: [[FDIV_D64_:%[0-9]+]]:fgr64 = FDIV_D64 [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FDIV_D64_]]
+ ; FP64: RetRA implicit $d0
+ %0:fprb(s64) = COPY $d6
+ %1:fprb(s64) = COPY $d7
+ %2:fprb(s64) = G_FDIV %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir?rev=357584&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir Wed Apr 3 07:12:59 2019
@@ -0,0 +1,248 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+
+--- |
+
+ define void @float_add() {entry: ret void}
+ define void @float_sub() {entry: ret void}
+ define void @float_mul() {entry: ret void}
+ define void @float_div() {entry: ret void}
+ define void @double_add() {entry: ret void}
+ define void @double_sub() {entry: ret void}
+ define void @double_mul() {entry: ret void}
+ define void @double_div() {entry: ret void}
+
+...
+---
+name: float_add
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_add
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP32: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FADD]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_add
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP64: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FADD]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FADD %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_sub
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_sub
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FSUB]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_sub
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FSUB]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FSUB %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_mul
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_mul
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP32: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FMUL]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_mul
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP64: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FMUL]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FMUL %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_div
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_div
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP32: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FDIV]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_div
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
+ ; FP64: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FDIV]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FDIV %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: double_add
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_add
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP32: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FADD]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_add
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP64: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FADD]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FADD %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_sub
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_sub
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FSUB]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_sub
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FSUB]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FSUB %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_mul
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_mul
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP32: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FMUL]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_mul
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP64: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FMUL]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FMUL %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_div
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_div
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP32: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FDIV]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_div
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; FP64: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FDIV]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FDIV %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll?rev=357584&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll Wed Apr 3 07:12:59 2019
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+
+define float @float_add(float %a, float %b) {
+; MIPS32-LABEL: float_add:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: add.s $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %add = fadd float %a, %b
+ ret float %add
+}
+
+define float @float_sub(float %a, float %b) {
+; MIPS32-LABEL: float_sub:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: sub.s $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %sub = fsub float %a, %b
+ ret float %sub
+}
+
+define float @float_mul(float %a, float %b) {
+; MIPS32-LABEL: float_mul:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: mul.s $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %mul = fmul float %a, %b
+ ret float %mul
+}
+
+define float @float_div(float %a, float %b) {
+; MIPS32-LABEL: float_div:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: div.s $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %div = fdiv float %a, %b
+ ret float %div
+}
+
+define double @double_add(double %a, double %b) {
+; MIPS32-LABEL: double_add:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: add.d $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %add = fadd double %a, %b
+ ret double %add
+}
+
+define double @double_sub(double %a, double %b) {
+; MIPS32-LABEL: double_sub:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: sub.d $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %sub = fsub double %a, %b
+ ret double %sub
+}
+
+define double @double_mul(double %a, double %b) {
+; MIPS32-LABEL: double_mul:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: mul.d $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %mul = fmul double %a, %b
+ ret double %mul
+}
+
+define double @double_div(double %a, double %b) {
+; MIPS32-LABEL: double_div:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: div.d $f0, $f12, $f14
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %div = fdiv double %a, %b
+ ret double %div
+}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir?rev=357584&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir Wed Apr 3 07:12:59 2019
@@ -0,0 +1,256 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+
+--- |
+
+ define void @float_add() {entry: ret void}
+ define void @float_sub() {entry: ret void}
+ define void @float_mul() {entry: ret void}
+ define void @float_div() {entry: ret void}
+ define void @double_add() {entry: ret void}
+ define void @double_sub() {entry: ret void}
+ define void @double_mul() {entry: ret void}
+ define void @double_div() {entry: ret void}
+
+...
+---
+name: float_add
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_add
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FADD]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_add
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP64: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FADD]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FADD %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_sub
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_sub
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP32: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FSUB]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_sub
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP64: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FSUB]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FSUB %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_mul
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_mul
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP32: [[FMUL:%[0-9]+]]:fprb(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FMUL]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_mul
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP64: [[FMUL:%[0-9]+]]:fprb(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FMUL]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FMUL %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: float_div
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_div
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP32: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP32: $f0 = COPY [[FDIV]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_div
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP64: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP64: $f0 = COPY [[FDIV]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ %2:_(s32) = G_FDIV %0, %1
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: double_add
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_add
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP32: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FADD]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_add
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP64: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FADD]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FADD %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_sub
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_sub
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP32: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FSUB]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_sub
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP64: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FSUB]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FSUB %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_mul
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_mul
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP32: [[FMUL:%[0-9]+]]:fprb(s64) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FMUL]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_mul
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP64: [[FMUL:%[0-9]+]]:fprb(s64) = G_FMUL [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FMUL]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FMUL %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: double_div
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_div
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP32: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP32: $d0 = COPY [[FDIV]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_div
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP64: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
+ ; FP64: $d0 = COPY [[FDIV]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ %2:_(s64) = G_FDIV %0, %1
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
More information about the llvm-commits
mailing list