[PATCH] D60150: [DAGCombiner][x86] scalarize splatted vector FP ops

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, lebedev.ri, efriedma.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.

There are a variety of vector patterns that may be profitably reduced to a scalar op when scalar ops are performed using a subset (typically, the first lane) of the vector register file.

For x86, this is true for float/double ops and element 0 because insert/extract is just a sub-register rename.

Other targets should likely enable the hook in a similar way.

Note that we will move the splat after the binop in instcombine for these patterns, but it's possible that we'll create splats here in the backend and form this pattern.

If this looks ok, the planned follow-ups would be to handle splat constant operands as well as the case where the splat follows the binop.


https://reviews.llvm.org/D60150

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/X86/scalarize-fp.ll

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