[PATCH] D60000: [llvm-exegesis] Post-processing for chained instrs in latency mode (PR41275)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 192976.
lebedev.ri edited the summary of this revision.
lebedev.ri added a comment.

While there, also model domain transfer delays.

I'm not sure about the first instruction though,

  vpextrb	$1, %xmm2, %edi
  vpinsrb	$1, %edi, %xmm7, %xmm2
  vpextrb	$1, %xmm2, %edi
  vpinsrb	$1, %edi, %xmm7, %xmm2

don't we go fpu->int->fpu ?
Shouldn't we be also modelling the fpu2int delays?

Also, still seeing some weird noise in some of these chained instructions.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60000/new/

https://reviews.llvm.org/D60000

Files:
  test/tools/llvm-exegesis/X86/analysis-latency-instruction-chaining-domain-transfer.test
  test/tools/llvm-exegesis/X86/analysis-latency-instruction-chaining.test
  tools/llvm-exegesis/lib/Analysis.cpp
  tools/llvm-exegesis/lib/Analysis.h
  tools/llvm-exegesis/lib/CMakeLists.txt
  tools/llvm-exegesis/lib/PostProcessing.cpp
  tools/llvm-exegesis/lib/PostProcessing.h
  tools/llvm-exegesis/llvm-exegesis.cpp

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