[llvm] r357281 - [ARM] Regenerate vector comparison tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 29 10:35:11 PDT 2019
Author: rksimon
Date: Fri Mar 29 10:35:11 2019
New Revision: 357281
URL: http://llvm.org/viewvc/llvm-project?rev=357281&view=rev
Log:
[ARM] Regenerate vector comparison tests
Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
Modified:
llvm/trunk/test/CodeGen/ARM/vceq.ll
llvm/trunk/test/CodeGen/ARM/vcge.ll
llvm/trunk/test/CodeGen/ARM/vcgt.ll
Modified: llvm/trunk/test/CodeGen/ARM/vceq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vceq.ll?rev=357281&r1=357280&r2=357281&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vceq.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vceq.ll Fri Mar 29 10:35:11 2019
@@ -1,92 +1,139 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s
define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vceqi8:
-;CHECK: vceq.i8
+; CHECK-LABEL: vceqi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vceq.i8 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = icmp eq <8 x i8> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vceqi16:
-;CHECK: vceq.i16
+; CHECK-LABEL: vceqi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vceq.i16 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = icmp eq <4 x i16> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vceqi32:
-;CHECK: vceq.i32
+; CHECK-LABEL: vceqi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vceq.i32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = icmp eq <2 x i32> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vceqf32:
-;CHECK: vceq.f32
+; CHECK-LABEL: vceqf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vceq.f32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vceqQi8:
-;CHECK: vceq.i8
+; CHECK-LABEL: vceqQi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vceq.i8 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = icmp eq <16 x i8> %tmp1, %tmp2
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vceqQi16:
-;CHECK: vceq.i16
+; CHECK-LABEL: vceqQi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vceq.i16 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = icmp eq <8 x i16> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vceqQi32:
-;CHECK: vceq.i32
+; CHECK-LABEL: vceqQi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vceq.i32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = icmp eq <4 x i32> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vceqQf32:
-;CHECK: vceq.f32
+; CHECK-LABEL: vceqQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vceq.f32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: vceqi8Z:
-;CHECK-NOT: vmov
-;CHECK-NOT: vmvn
-;CHECK: vceq.i8
+; CHECK-LABEL: vceqi8Z:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r0]
+; CHECK-NEXT: vceq.i8 d16, d16, #0
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
Modified: llvm/trunk/test/CodeGen/ARM/vcge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcge.ll?rev=357281&r1=357280&r2=357281&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcge.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcge.ll Fri Mar 29 10:35:11 2019
@@ -1,148 +1,231 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s
define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vcges8:
-;CHECK: vcge.s8
+; CHECK-LABEL: vcges8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vcge.s8 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = icmp sge <8 x i8> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vcges16:
-;CHECK: vcge.s16
+; CHECK-LABEL: vcges16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vcge.s16 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = icmp sge <4 x i16> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vcges32:
-;CHECK: vcge.s32
+; CHECK-LABEL: vcges32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vcge.s32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = icmp sge <2 x i32> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vcgeu8:
-;CHECK: vcge.u8
+; CHECK-LABEL: vcgeu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vcge.u8 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = icmp uge <8 x i8> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vcgeu16:
-;CHECK: vcge.u16
+; CHECK-LABEL: vcgeu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vcge.u16 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = icmp uge <4 x i16> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vcgeu32:
-;CHECK: vcge.u32
+; CHECK-LABEL: vcgeu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vcge.u32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = icmp uge <2 x i32> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vcgef32:
-;CHECK: vcge.f32
+; CHECK-LABEL: vcgef32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vcge.f32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vcgeQs8:
-;CHECK: vcge.s8
+; CHECK-LABEL: vcgeQs8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vcge.s8 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = icmp sge <16 x i8> %tmp1, %tmp2
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vcgeQs16:
-;CHECK: vcge.s16
+; CHECK-LABEL: vcgeQs16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vcge.s16 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = icmp sge <8 x i16> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vcgeQs32:
-;CHECK: vcge.s32
+; CHECK-LABEL: vcgeQs32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vcge.s32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = icmp sge <4 x i32> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vcgeQu8:
-;CHECK: vcge.u8
+; CHECK-LABEL: vcgeQu8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vcge.u8 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = icmp uge <16 x i8> %tmp1, %tmp2
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vcgeQu16:
-;CHECK: vcge.u16
+; CHECK-LABEL: vcgeQu16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vcge.u16 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = icmp uge <8 x i16> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vcgeQu32:
-;CHECK: vcge.u32
+; CHECK-LABEL: vcgeQu32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vcge.u32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = icmp uge <4 x i32> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vcgeQf32:
-;CHECK: vcge.f32
+; CHECK-LABEL: vcgeQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vcge.f32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vacgef32:
-;CHECK: vacge.f32
+; CHECK-LABEL: vacgef32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vacge.f32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
@@ -150,8 +233,14 @@ define <2 x i32> @vacgef32(<2 x float>*
}
define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vacgeQf32:
-;CHECK: vacge.f32
+; CHECK-LABEL: vacgeQf32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vacge.f32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
@@ -162,24 +251,28 @@ declare <2 x i32> @llvm.arm.neon.vacge.v
declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: vcgei8Z:
-;CHECK-NOT: vmov
-;CHECK-NOT: vmvn
-;CHECK: vcge.s8
+; CHECK-LABEL: vcgei8Z:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r0]
+; CHECK-NEXT: vcge.s8 d16, d16, #0
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = icmp sge <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: vclei8Z:
-;CHECK-NOT: vmov
-;CHECK-NOT: vmvn
-;CHECK: vcle.s8
+; CHECK-LABEL: vclei8Z:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r0]
+; CHECK-NEXT: vcle.s8 d16, d16, #0
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
@@ -187,8 +280,14 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) n
; Floating-point comparisons against zero produce results with integer
; elements, not floating-point elements.
define void @test_vclez_fp() nounwind optsize {
-;CHECK-LABEL: test_vclez_fp:
-;CHECK: vcle.f32
+; CHECK-LABEL: test_vclez_fp:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcle.f32 q8, q8, #0
+; CHECK-NEXT: vmovn.i32 d16, q8
+; CHECK-NEXT: vmov.i8 d17, #0x1
+; CHECK-NEXT: vuzp.8 d16, d18
+; CHECK-NEXT: vadd.i8 d16, d16, d17
+; CHECK-NEXT: vst1.8 {d16}, [r0]
entry:
%0 = fcmp ole <4 x float> undef, zeroinitializer
%1 = sext <4 x i1> %0 to <4 x i16>
Modified: llvm/trunk/test/CodeGen/ARM/vcgt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcgt.ll?rev=357281&r1=357280&r2=357281&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcgt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcgt.ll Fri Mar 29 10:35:11 2019
@@ -1,149 +1,359 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s --check-prefixes=CHECK,ALLOC,NOALLOC
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -regalloc=basic | FileCheck %s --check-prefixes=CHECK,BASIC
define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vcgts8:
-;CHECK: vcgt.s8
+; ALLOC-LABEL: vcgts8:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vcgt.s8 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgts8:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vcgt.s8 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vcgts16:
-;CHECK: vcgt.s16
+; ALLOC-LABEL: vcgts16:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vcgt.s16 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgts16:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vcgt.s16 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vcgts32:
-;CHECK: vcgt.s32
+; ALLOC-LABEL: vcgts32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vcgt.s32 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgts32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vcgt.s32 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vcgtu8:
-;CHECK: vcgt.u8
+; ALLOC-LABEL: vcgtu8:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vcgt.u8 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtu8:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vcgt.u8 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vcgtu16:
-;CHECK: vcgt.u16
+; ALLOC-LABEL: vcgtu16:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vcgt.u16 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtu16:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vcgt.u16 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vcgtu32:
-;CHECK: vcgt.u32
+; ALLOC-LABEL: vcgtu32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vcgt.u32 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtu32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vcgt.u32 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vcgtf32:
-;CHECK: vcgt.f32
+; ALLOC-LABEL: vcgtf32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vcgt.f32 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtf32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vcgt.f32 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vcgtQs8:
-;CHECK: vcgt.s8
+; ALLOC-LABEL: vcgtQs8:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.s8 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtQs8:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.s8 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vcgtQs16:
-;CHECK: vcgt.s16
+; ALLOC-LABEL: vcgtQs16:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.s16 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtQs16:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.s16 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vcgtQs32:
-;CHECK: vcgt.s32
+; ALLOC-LABEL: vcgtQs32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.s32 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtQs32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.s32 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vcgtQu8:
-;CHECK: vcgt.u8
+; ALLOC-LABEL: vcgtQu8:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.u8 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtQu8:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.u8 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vcgtQu16:
-;CHECK: vcgt.u16
+; ALLOC-LABEL: vcgtQu16:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.u16 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtQu16:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.u16 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vcgtQu32:
-;CHECK: vcgt.u32
+; ALLOC-LABEL: vcgtQu32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.u32 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtQu32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.u32 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vcgtQf32:
-;CHECK: vcgt.f32
+; ALLOC-LABEL: vcgtQf32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.f32 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgtQf32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.f32 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vacgtf32:
-;CHECK: vacgt.f32
+; ALLOC-LABEL: vacgtf32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vldr d16, [r1]
+; ALLOC-NEXT: vldr d17, [r0]
+; ALLOC-NEXT: vacgt.f32 d16, d17, d16
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vacgtf32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vldr d17, [r1]
+; BASIC-NEXT: vldr d16, [r0]
+; BASIC-NEXT: vacgt.f32 d16, d16, d17
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
@@ -151,8 +361,23 @@ define <2 x i32> @vacgtf32(<2 x float>*
}
define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vacgtQf32:
-;CHECK: vacgt.f32
+; ALLOC-LABEL: vacgtQf32:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vacgt.f32 q8, q9, q8
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vacgtQf32:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vacgt.f32 q8, q8, q9
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
@@ -161,14 +386,31 @@ define <4 x i32> @vacgtQf32(<4 x float>*
; rdar://7923010
define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vcgt_zext:
-;CHECK-DAG: vmov.i32 [[Q0:q[0-9]+]], #0x1
-;CHECK-DAG: vcgt.f32 [[Q1:q[0-9]+]]
-;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
+; ALLOC-LABEL: vcgt_zext:
+; ALLOC: @ %bb.0:
+; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
+; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]
+; ALLOC-NEXT: vcgt.f32 q8, q9, q8
+; ALLOC-NEXT: vmov.i32 q9, #0x1
+; ALLOC-NEXT: vand q8, q8, q9
+; ALLOC-NEXT: vmov r0, r1, d16
+; ALLOC-NEXT: vmov r2, r3, d17
+; ALLOC-NEXT: mov pc, lr
+;
+; BASIC-LABEL: vcgt_zext:
+; BASIC: @ %bb.0:
+; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
+; BASIC-NEXT: vld1.64 {d16, d17}, [r0]
+; BASIC-NEXT: vcgt.f32 q9, q8, q9
+; BASIC-NEXT: vmov.i32 q8, #0x1
+; BASIC-NEXT: vand q8, q9, q8
+; BASIC-NEXT: vmov r0, r1, d16
+; BASIC-NEXT: vmov r2, r3, d17
+; BASIC-NEXT: mov pc, lr
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
- %tmp4 = zext <4 x i1> %tmp3 to <4 x i32>
+ %tmp4 = zext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
@@ -176,23 +418,27 @@ declare <2 x i32> @llvm.arm.neon.vacgt.v
declare <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: vcgti8Z:
-;CHECK-NOT: vmov
-;CHECK-NOT: vmvn
-;CHECK: vcgt.s8
+; CHECK-LABEL: vcgti8Z:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r0]
+; CHECK-NEXT: vcgt.s8 d16, d16, #0
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = icmp sgt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: vclti8Z:
-;CHECK-NOT: vmov
-;CHECK-NOT: vmvn
-;CHECK: vclt.s8
+; CHECK-LABEL: vclti8Z:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r0]
+; CHECK-NEXT: vclt.s8 d16, d16, #0
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp3 = icmp slt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
More information about the llvm-commits
mailing list