[PATCH] D59952: [VPLAN] Remove option for stress testing.

[Diego Caballero via Phabricator via llvm-commits]

dcaballe added a comment.

Yep, I agree on that we should keep the stress testing mechanism. It will be very useful to make sure that the construction and predication (and maybe other transformation) are robust enough since we can run it on loop nests that are not necessarily vectorizable.
Something important, though, is that we shouldn't use this mechanism to bypass legality or pragma simd requirements to vectorize a loop, i.e., we shouldn't use it to generate actual vector code.
What are you trying to achieve, Francesco?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D59952/new/

https://reviews.llvm.org/D59952