[PATCH] D59821: [llvm-exegesis] Allow the target to disable the selection of some registers.

Wed Mar 27 08:01:53 PDT 2019

craig.topper added a comment.

In D59821#1444188 <https://reviews.llvm.org/D59821#1444188>, @courbet wrote:

> In D59821#1444043 <https://reviews.llvm.org/D59821#1444043>, @craig.topper wrote:
>
> > What protects R8 <https://reviews.llvm.org/source/libcxx/>-R15 in 32-bit mode or SIL/DIL/BPL/SPL?
>
>
> Thanks Craig,
>
> This is the `x86_64` target (the only one we support at the moment) so we're good on the first part :)
>
> For the rest, TBH I'm not well versed in the subtleties of X86 encoding, so got these registers from the list here <https://github.com/llvm/llvm-project/blob/2946cd701067404b99c39fb29dc9c74bd7193eb3/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp#L1049>.
>  As Guillaume mentioned if there is a register class I can use I'll be happy to.

I should have phrased my question better. SIL/DIL/BPL/SPL are only available in x86_64. So if that's all you support then you are ok.

Repository:
  rL LLVM

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https://reviews.llvm.org/D59821