[PATCH] D59758: [DAGCombiner] Combine OR as ADD when no common bits are set

Krzysztof Parzyszek via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 27 07:34:34 PDT 2019

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kparzysz added a comment.

The Hexagon testcase can be fixed---it's probably just a matter of changing the selection pattern for the instruction we're checking.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59758/new/

https://reviews.llvm.org/D59758

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