[PATCH] D59821: [llvm-exegesis] Allow the target to disable the selection of some registers.

[Guillaume Chatelet via Phabricator via llvm-commits]

gchatelet added a comment.

In D59821#1444043 <https://reviews.llvm.org/D59821#1444043>, @craig.topper wrote:

> What protects R8 <https://reviews.llvm.org/source/libcxx/>-R15 in 32-bit mode or SIL/DIL/BPL/SPL?


Is there a register class that can used reliably for this purpose?


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  rL LLVM

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