[PATCH] D59821: [llvm-exegesis] Allow the target to disable the selection of some registers.
Clement Courbet via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 26 08:43:51 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL357003: [llvm-exegesis] Allow the target to disable the selection of some registers. (authored by courbet, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D59821?vs=192282&id=192284#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D59821/new/
https://reviews.llvm.org/D59821
Files:
llvm/trunk/test/tools/llvm-exegesis/X86/latency-SBB8rr.s
llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp
llvm/trunk/tools/llvm-exegesis/lib/Target.h
llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
llvm/trunk/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
Index: llvm/trunk/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
===================================================================
--- llvm/trunk/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
+++ llvm/trunk/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
@@ -144,6 +144,10 @@
Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
};
+TEST_F(Core2TargetTest, NoHighByteRegs) {
+ EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));
+}
+
TEST_F(Core2TargetTest, SetFlags) {
const unsigned Reg = llvm::X86::EFLAGS;
EXPECT_THAT(
Index: llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
===================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
+++ llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -435,6 +435,12 @@
unsigned Reg,
const llvm::APInt &Value) const override;
+ ArrayRef<unsigned> getUnavailableRegisters() const override {
+ return makeArrayRef(kUnavailableRegisters,
+ sizeof(kUnavailableRegisters) /
+ sizeof(kUnavailableRegisters[0]));
+ }
+
std::unique_ptr<SnippetGenerator>
createLatencySnippetGenerator(const LLVMState &State) const override {
return llvm::make_unique<X86LatencySnippetGenerator>(State);
@@ -448,7 +454,14 @@
bool matchesArch(llvm::Triple::ArchType Arch) const override {
return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86;
}
+
+ static const unsigned kUnavailableRegisters[4];
};
+
+// We disable a few registers that cannot be encoded on instructions with a REX
+// prefix.
+const unsigned ExegesisX86Target::kUnavailableRegisters[4] = {X86::AH, X86::BH,
+ X86::CH, X86::DH};
} // namespace
void ExegesisX86Target::addTargetSpecificPasses(
Index: llvm/trunk/tools/llvm-exegesis/lib/Target.h
===================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/Target.h
+++ llvm/trunk/tools/llvm-exegesis/lib/Target.h
@@ -90,6 +90,11 @@
"fillMemoryOperands() requires getScratchMemoryRegister() > 0");
}
+ // Returns a list of unavailable registers.
+ // Targets can use this to prevent some registers to be automatically selected
+ // for use in snippets.
+ virtual ArrayRef<unsigned> getUnavailableRegisters() const { return {}; }
+
// Returns the maximum number of bytes a load/store instruction can access at
// once. This is typically the size of the largest register available on the
// processor. Note that this only used as a hint to generate independant
Index: llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp
===================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp
+++ llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp
@@ -38,8 +38,11 @@
}
PfmCounters = &TheExegesisTarget->getPfmCounters(CpuName);
- RATC.reset(new RegisterAliasingTrackerCache(
- getRegInfo(), getFunctionReservedRegs(getTargetMachine())));
+ BitVector ReservedRegs = getFunctionReservedRegs(getTargetMachine());
+ for (const unsigned Reg : TheExegesisTarget->getUnavailableRegisters())
+ ReservedRegs.set(Reg);
+ RATC.reset(
+ new RegisterAliasingTrackerCache(getRegInfo(), std::move(ReservedRegs)));
IC.reset(new InstructionsCache(getInstrInfo(), getRATC()));
}
Index: llvm/trunk/test/tools/llvm-exegesis/X86/latency-SBB8rr.s
===================================================================
--- llvm/trunk/test/tools/llvm-exegesis/X86/latency-SBB8rr.s
+++ llvm/trunk/test/tools/llvm-exegesis/X86/latency-SBB8rr.s
@@ -0,0 +1,11 @@
+# RUN: llvm-exegesis -mode=latency -opcode-name=SBB8rr | FileCheck %s
+
+CHECK: ---
+CHECK-NEXT: mode: latency
+CHECK-NEXT: key:
+CHECK-NEXT: instructions:
+CHECK-NEXT: SBB8rr
+CHECK-NEXT: config: ''
+CHECK-NEXT: register_initial_values:
+CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
+CHECK-LAST: ...
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