[llvm] r356990 - [RISCV] Improve codegen for icmp {ne, eq} with a constant

[Luis Marques via llvm-commits]

Author: luismarques
Date: Tue Mar 26 05:55:00 2019
New Revision: 356990

URL: http://llvm.org/viewvc/llvm-project?rev=356990&view=rev
Log:
[RISCV] Improve codegen for icmp {ne,eq} with a constant

Adds two patterns to improve the codegen of GPR value comparisons with small
constants. Instead of first loading the constant into another register and then
doing an XOR of those registers, these patterns directly use the constant as an
XORI immediate.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=356990&r1=356989&r2=356990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Tue Mar 26 05:55:00 2019
@@ -771,8 +771,12 @@ def : PatGprSimm12<setult, SLTIU>;
 // handled by a RISC-V instruction.
 def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>;
 def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
+def : Pat<(seteq GPR:$rs1, simm12:$imm12),
+          (SLTIU (XORI GPR:$rs1, simm12:$imm12), 1)>;
 def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
+def : Pat<(setne GPR:$rs1, simm12:$imm12),
+          (SLTU X0, (XORI GPR:$rs1, simm12:$imm12))>;
 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;

Modified: llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll?rev=356990&r1=356989&r2=356990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/i32-icmp.ll Tue Mar 26 05:55:00 2019
@@ -16,6 +16,17 @@ define i32 @icmp_eq(i32 %a, i32 %b) noun
   ret i32 %2
 }
 
+define i32 @icmp_eq_constant(i32 %a) nounwind {
+; RV32I-LABEL: icmp_eq_constant:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xori a0, a0, 42
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    ret
+  %1 = icmp eq i32 %a, 42
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
 define i32 @icmp_eqz(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_eqz:
 ; RV32I:       # %bb.0:
@@ -36,6 +47,17 @@ define i32 @icmp_ne(i32 %a, i32 %b) noun
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
+
+define i32 @icmp_ne_constant(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ne_constant:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xori a0, a0, 42
+; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    ret
+  %1 = icmp ne i32 %a, 42
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
 
 define i32 @icmp_nez(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_nez: