[PATCH] D59338: MISched: Don't schedule regions with 0 instructions

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 21 10:42:05 PDT 2019

Previous message: [PATCH] D58758: GlobalISel: Fix RegBankSelect for REG_SEQUENCE
Next message: [llvm] r356690 - [InstCombine] Don't transform ((C1 OP zext(X)) & C2) -> zext((C1 OP X) & C2) if either zext or OP has another use.
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arsenm added a comment.

ping


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59338/new/

https://reviews.llvm.org/D59338

Previous message: [PATCH] D58758: GlobalISel: Fix RegBankSelect for REG_SEQUENCE
Next message: [llvm] r356690 - [InstCombine] Don't transform ((C1 OP zext(X)) & C2) -> zext((C1 OP X) & C2) if either zext or OP has another use.
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