[PATCH] D59295: [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:154
+    // physical registers.
+    const unsigned MovOp = TII->getMovOpcode(TRI->getPhysRegClass(PhysReg));
+
----------------
Can't you just hardcoded this to v_mov_b32?


================
Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:156
+
+    for (MachineOperand &MO : MRI->reg_operands(PhysReg)) {
+      MachineInstr &MI = *MO.getParent();
----------------
MRI->reg_instructions()? It would also save the check that the operand matches later


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Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:160
+      // Only check copies.
+      if (MI.getOpcode() != AMDGPU::COPY) {
+        continue;
----------------
.isCopy()


================
Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:183-184
+
+      // And make it implicitly depend on exec (like all VALU movs should do).
+      MI.addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
+    }
----------------
I know we have a helper to do this somewhere


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  https://reviews.llvm.org/D59295/new/

https://reviews.llvm.org/D59295