[llvm] r356540 - [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel

[David Stuttard via llvm-commits]

Author: dstuttard
Date: Wed Mar 20 02:29:55 2019
New Revision: 356540

URL: http://llvm.org/viewvc/llvm-project?rev=356540&view=rev
Log:
[AMDGPU] Allow MIMG with no uses in adjustWritemask in isel

Summary:
If an MIMG instruction has managed to get through to adjustWritemask in isel but
has no uses (and doesn't enable TFC) then prevent an assertion by not attempting
to adjust the writemask.

The instruction will be removed anyway.

Change-Id: I9a5dba6bafe1f35ac99c1b73df390936e2ac27a7

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58964

Added:
    llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=356540&r1=356539&r2=356540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Wed Mar 20 02:29:55 2019
@@ -9263,6 +9263,10 @@ SDNode *SITargetLowering::adjustWritemas
   // Don't allow 0 dmask, as hardware assumes one channel enabled.
   bool NoChannels = !NewDmask;
   if (NoChannels) {
+    if (!UsesTFC) {
+      // No uses of the result and not using TFC. Then do nothing.
+      return Node;
+    }
     // If the original dmask has one channel - then nothing to do
     if (OldBitsSet == 1)
       return Node;

Added: llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll?rev=356540&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll Wed Mar 20 02:29:55 2019
@@ -0,0 +1,22 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN
+
+; We're really just checking for no crashes
+; The feature we're testing for in AdjustWriteMask leaves the image_load as an instruction just post amdgpu-isel
+; In reality, it's hard to get an image intrinsic into AdjustWriteMask with no uses as it will usually get removed
+; first, but it can happen, hence the fix associated with this test
+
+; GCN-LABEL: name: _amdgpu_cs_main
+; GCN-LABEL: bb.0
+; GCN: IMAGE_LOAD_V4_V2
+define amdgpu_cs void @_amdgpu_cs_main(i32 %dummy) local_unnamed_addr #0 {
+.entry:
+  %unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 0) #3
+  call void asm sideeffect ";", "" () #0
+  ret void
+}
+
+; Function Attrs: nounwind readonly
+declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
+  
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly  }