[www-releases] r356539 - Check in the 8.0.0 release
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 20 02:13:34 PDT 2019
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_64.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_64.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_64.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_64.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_dst_buf_96.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_buf_32.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_96.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_32.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-buf-64"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output: data read from a memory buffer.</p>
+<p><em>Size:</em> 2 dwords by default. <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> adds 1 dword if specified.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_96.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_32.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_96.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_96.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_96.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_96.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_dst_buf_lds.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_buf_64.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_lds.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_64.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-buf-96"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output: data read from a memory buffer.</p>
+<p><em>Size:</em> 3 dwords by default. <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> adds 1 dword if specified.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_lds.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_64.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_lds.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_lds.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_lds.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_buf_lds.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,98 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_dst_flat_atomic32.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_buf_96.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic32.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_96.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-buf-lds"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output: data read from a memory buffer.</p>
+<p>If <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-lds"><span class="std std-ref">lds</span></a> is specified, this operand is ignored by H/W and data are stored directly into LDS.</p>
+<p><em>Size:</em> 1 dword by default. <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> adds 1 dword if specified.</p>
+<blockquote>
+<div>Note that <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> and <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-lds"><span class="std std-ref">lds</span></a> cannot be used together.</div></blockquote>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic32.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_96.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic32.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic32.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic32.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic32.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,96 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_dst_flat_atomic64.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_buf_lds.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic64.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_lds.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-flat-atomic32"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Data returned by a 32-bit atomic flat instruction.</p>
+<p>This is an optional operand. It must be used if and only if <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-glc"><span class="std std-ref">glc</span></a> is specified.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic64.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_buf_lds.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic64.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic64.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic64.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_flat_atomic64.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,96 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_dst_mimg_gather4.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_flat_atomic32.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_gather4.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic32.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-flat-atomic64"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Data returned by a 64-bit atomic flat instruction.</p>
+<p>This is an optional operand. It must be used if and only if <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-glc"><span class="std std-ref">glc</span></a> is specified.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_gather4.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic32.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_gather4.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_gather4.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_gather4.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_gather4.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,100 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_dst_mimg_regular.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_flat_atomic64.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_regular.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic64.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-mimg-gather4"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Image data to load by an <em>image_gather4</em> instruction.</p>
+<p><em>Size:</em> 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-d16"><span class="std std-ref">d16</span></a>.</p>
+<p><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-d16"><span class="std std-ref">d16</span></a> and <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> affect operand size as follows:</p>
+<ul class="simple">
+<li><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-d16"><span class="std std-ref">d16</span></a> specifies that data elements in registers are packed; each value occupies 16 bits.</li>
+<li><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> adds one dword if specified.</li>
+</ul>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_regular.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_flat_atomic64.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,99 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_dst_mimg_regular_d16.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_mimg_gather4.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_regular_d16.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_gather4.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-mimg-regular"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Image data to load by an image instruction.</p>
+<p><em>Size:</em> depends on <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-dmask"><span class="std std-ref">dmask</span></a> and <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a>:</p>
+<ul class="simple">
+<li><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-dmask"><span class="std std-ref">dmask</span></a> may specify from 1 to 4 data elements. Each data element occupies 1 dword.</li>
+<li><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> adds 1 dword if specified.</li>
+</ul>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_regular_d16.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_gather4.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular_d16.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular_d16.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular_d16.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_dst_mimg_regular_d16.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,100 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="soffset" href="gfx9_offset_buf.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_mimg_regular.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_offset_buf.html" title="soffset"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_regular.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-dst-mimg-regular-d16"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Image data to load by an image instruction.</p>
+<p><em>Size:</em> depends on <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-dmask"><span class="std std-ref">dmask</span></a>, <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> and <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-d16"><span class="std std-ref">d16</span></a>:</p>
+<ul class="simple">
+<li><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-dmask"><span class="std std-ref">dmask</span></a> may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-d16"><span class="std std-ref">d16</span></a>.</li>
+<li><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-d16"><span class="std std-ref">d16</span></a> specifies that data elements in registers are packed; each value occupies 16 bits.</li>
+<li><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-tfe"><span class="std std-ref">tfe</span></a> adds 1 dword if specified.</li>
+</ul>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_offset_buf.html" title="soffset"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_dst_mimg_regular.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm16.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm16.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm16.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm16.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>imm32 — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="imm32" href="gfx9_fimm32.html" />
+ <link rel="prev" title="imm32" href="gfx9_bimm32.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_fimm32.html" title="imm32"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_bimm32.html" title="imm32"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="imm32">
+<span id="amdgpu-synid9-fimm16"></span><h1>imm32<a class="headerlink" href="#imm32" title="Permalink to this headline">¶</a></h1>
+<p>An <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a> or a <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point_number</span></a>. The number is converted to <em>f16</em> as described <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-lit-conv"><span class="std std-ref">here</span></a>.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_fimm32.html" title="imm32"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_bimm32.html" title="imm32"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
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+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm32.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm32.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm32.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_fimm32.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>imm32 — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
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+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="hwreg" href="gfx9_hwreg.html" />
+ <link rel="prev" title="imm32" href="gfx9_fimm16.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
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+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_hwreg.html" title="hwreg"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
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+ accesskey="P">previous</a> |</li>
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+ <li><a href="../index.html">Documentation</a>»</li>
+
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+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="imm32">
+<span id="amdgpu-synid9-fimm32"></span><h1>imm32<a class="headerlink" href="#imm32" title="Permalink to this headline">¶</a></h1>
+<p>An <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a> or a <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point_number</span></a>. The value is converted to <em>f32</em> as described <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-lit-conv"><span class="std std-ref">here</span></a>.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_hwreg.html" title="hwreg"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_fimm16.html" title="imm32"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
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+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_hwreg.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_hwreg.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_hwreg.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_hwreg.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,194 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>hwreg — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="imm4" href="gfx9_imm4.html" />
+ <link rel="prev" title="imm32" href="gfx9_fimm32.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_imm4.html" title="imm4"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_fimm32.html" title="imm32"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="hwreg">
+<span id="amdgpu-synid9-hwreg"></span><h1>hwreg<a class="headerlink" href="#hwreg" title="Permalink to this headline">¶</a></h1>
+<p>Bits of a hardware register being accessed.</p>
+<p>The bits of this operand have the following meaning:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="26%" />
+<col width="74%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>5:0</td>
+<td>Register <em>id</em>.</td>
+</tr>
+<tr class="row-odd"><td>10:6</td>
+<td>First bit <em>offset</em> (0..31).</td>
+</tr>
+<tr class="row-even"><td>15:11</td>
+<td><em>Size</em> in bits (1..32).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>This operand may be specified as a positive 16-bit <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a> or using the syntax described below.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="32%" />
+<col width="68%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>hwreg({0..63})</td>
+<td>All bits of a register indicated by its <em>id</em>.</td>
+</tr>
+<tr class="row-odd"><td>hwreg(<<em>name</em>>)</td>
+<td>All bits of a register indicated by its <em>name</em>.</td>
+</tr>
+<tr class="row-even"><td>hwreg({0..63}, {0..31}, {1..32})</td>
+<td>Register bits indicated by register <em>id</em>, first bit <em>offset</em> and <em>size</em>.</td>
+</tr>
+<tr class="row-odd"><td>hwreg(<<em>name</em>>, {0..31}, {1..32})</td>
+<td>Register bits indicated by register <em>name</em>, first bit <em>offset</em> and <em>size</em>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Register <em>id</em>, <em>offset</em> and <em>size</em> must be specified as positive <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
+<p>Defined register <em>names</em> include:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="31%" />
+<col width="69%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>HW_REG_MODE</td>
+<td>Shader writeable mode bits.</td>
+</tr>
+<tr class="row-odd"><td>HW_REG_STATUS</td>
+<td>Shader read-only status.</td>
+</tr>
+<tr class="row-even"><td>HW_REG_TRAPSTS</td>
+<td>Trap status.</td>
+</tr>
+<tr class="row-odd"><td>HW_REG_HW_ID</td>
+<td>Id of wave, simd, compute unit, etc.</td>
+</tr>
+<tr class="row-even"><td>HW_REG_GPR_ALLOC</td>
+<td>Per-wave SGPR and VGPR allocation.</td>
+</tr>
+<tr class="row-odd"><td>HW_REG_LDS_ALLOC</td>
+<td>Per-wave LDS allocation.</td>
+</tr>
+<tr class="row-even"><td>HW_REG_IB_STS</td>
+<td>Counters of outstanding instructions.</td>
+</tr>
+<tr class="row-odd"><td>HW_REG_SH_MEM_BASES</td>
+<td>Memory aperture.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="mh">0x6</span>
+<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="mi">15</span><span class="p">)</span>
+<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="mi">51</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">31</span><span class="p">)</span>
+<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="n">HW_REG_LDS_ALLOC</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
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+
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+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_imm4.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_imm4.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_imm4.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_imm4.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,121 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>imm4 — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
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+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="label" href="gfx9_label.html" />
+ <link rel="prev" title="hwreg" href="gfx9_hwreg.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
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+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
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+ <a href="gfx9_label.html" title="label"
+ accesskey="N">next</a> |</li>
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+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
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+
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+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
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+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="imm4">
+<span id="amdgpu-synid9-imm4"></span><h1>imm4<a class="headerlink" href="#imm4" title="Permalink to this headline">¶</a></h1>
+<p>A positive <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>. The value is truncated to 4 bits.</p>
+<p>This operand is a mask which controls indexing mode for operands of subsequent instructions. Value 1 enables indexing and value 0 disables it.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="23%" />
+<col width="77%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bit</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Enables or disables <em>src0</em> indexing.</td>
+</tr>
+<tr class="row-odd"><td>1</td>
+<td>Enables or disables <em>src1</em> indexing.</td>
+</tr>
+<tr class="row-even"><td>2</td>
+<td>Enables or disables <em>src2</em> indexing.</td>
+</tr>
+<tr class="row-odd"><td>3</td>
+<td>Enables or disables <em>dst</em> indexing.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
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+ >next</a> |</li>
+ <li class="right" >
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+ >previous</a> |</li>
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+
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+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
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+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_label.html
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==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_label.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_label.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,107 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>label — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="msg" href="gfx9_msg.html" />
+ <link rel="prev" title="imm4" href="gfx9_imm4.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_msg.html" title="msg"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_imm4.html" title="imm4"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="label">
+<span id="amdgpu-synid9-label"></span><h1>label<a class="headerlink" href="#label" title="Permalink to this headline">¶</a></h1>
+<p>A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.</p>
+<p>This operand may be specified as:</p>
+<ul class="simple">
+<li>An <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>. The number is truncated to 16 bits.</li>
+<li>An <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute_expression</span></a> which must start with an <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>. The value of the expression is truncated to 16 bits.</li>
+<li>A <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-symbol"><span class="std std-ref">symbol</span></a> (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.</li>
+</ul>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span> <span class="o">=</span> <span class="mi">30</span>
+<span class="n">s_branch</span> <span class="n">loop_end</span>
+<span class="n">s_branch</span> <span class="mi">2</span> <span class="o">+</span> <span class="n">offset</span>
+<span class="n">s_branch</span> <span class="mi">32</span>
+<span class="n">loop_end</span><span class="p">:</span>
+</pre></div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_msg.html" title="msg"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_imm4.html" title="imm4"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mad_type_dev.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mad_type_dev.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mad_type_dev.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mad_type_dev.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,97 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>fx — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="m" href="gfx9_mod_dpp_sdwa_abs_neg.html" />
+ <link rel="prev" title="vsrc" href="gfx9_vsrc64_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_mod_dpp_sdwa_abs_neg.html" title="m"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vsrc64_0.html" title="vsrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="fx">
+<span id="amdgpu-synid9-mad-type-dev"></span><h1>fx<a class="headerlink" href="#fx" title="Permalink to this headline">¶</a></h1>
+<p>This is an <em>f32</em> or <em>f16</em> operand depending on instruction modifiers:</p>
+<ul class="simple">
+<li>Operand size is controlled by <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-mad-mix-op-sel-hi"><span class="std std-ref">m_op_sel_hi</span></a>.</li>
+<li>Location of 16-bit operand is controlled by <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-mad-mix-op-sel"><span class="std std-ref">m_op_sel</span></a>.</li>
+</ul>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_mod_dpp_sdwa_abs_neg.html" title="m"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vsrc64_0.html" title="vsrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>m — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="m" href="gfx9_mod_sdwa_sext.html" />
+ <link rel="prev" title="fx" href="gfx9_mad_type_dev.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_mod_sdwa_sext.html" title="m"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_mad_type_dev.html" title="fx"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="m">
+<span id="amdgpu-synid9-mod-dpp-sdwa-abs-neg"></span><h1>m<a class="headerlink" href="#m" title="Permalink to this headline">¶</a></h1>
+<p>This operand may be used with floating point operand modifiers <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-abs"><span class="std std-ref">abs</span></a> and <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-neg"><span class="std std-ref">neg</span></a>.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_mod_sdwa_sext.html" title="m"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_mad_type_dev.html" title="fx"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_sdwa_sext.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_sdwa_sext.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_sdwa_sext.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_sdwa_sext.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>m — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="m" href="gfx9_mod_vop3_abs_neg.html" />
+ <link rel="prev" title="m" href="gfx9_mod_dpp_sdwa_abs_neg.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_mod_vop3_abs_neg.html" title="m"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_mod_dpp_sdwa_abs_neg.html" title="m"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="m">
+<span id="amdgpu-synid9-mod-sdwa-sext"></span><h1>m<a class="headerlink" href="#m" title="Permalink to this headline">¶</a></h1>
+<p>This operand may be used with integer operand modifier <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-sext"><span class="std std-ref">sext</span></a>.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_mod_vop3_abs_neg.html" title="m"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_mod_dpp_sdwa_abs_neg.html" title="m"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_vop3_abs_neg.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_vop3_abs_neg.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_vop3_abs_neg.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_mod_vop3_abs_neg.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>m — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="opt" href="gfx9_opt.html" />
+ <link rel="prev" title="m" href="gfx9_mod_sdwa_sext.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_opt.html" title="opt"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_mod_sdwa_sext.html" title="m"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="m">
+<span id="amdgpu-synid9-mod-vop3-abs-neg"></span><h1>m<a class="headerlink" href="#m" title="Permalink to this headline">¶</a></h1>
+<p>This operand may be used with floating point operand modifiers <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-abs"><span class="std std-ref">abs</span></a> and <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-neg"><span class="std std-ref">neg</span></a>.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_opt.html" title="opt"
+ >next</a> |</li>
+ <li class="right" >
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+ >previous</a> |</li>
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+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_msg.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_msg.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_msg.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_msg.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,253 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>msg — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
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+ <link rel="next" title="param" href="gfx9_param.html" />
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+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
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+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
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+ <h3>Navigation</h3>
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+ accesskey="I">index</a></li>
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+ accesskey="N">next</a> |</li>
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+ accesskey="P">previous</a> |</li>
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+ <li><a href="../index.html">Documentation</a>»</li>
+
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+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="msg">
+<span id="amdgpu-synid9-msg"></span><h1>msg<a class="headerlink" href="#msg" title="Permalink to this headline">¶</a></h1>
+<p>A 16-bit message code. The bits of this operand have the following meaning:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>3:0</td>
+<td>Message <em>type</em>.</td>
+</tr>
+<tr class="row-odd"><td>6:4</td>
+<td>Optional <em>operation</em>.</td>
+</tr>
+<tr class="row-even"><td>9:7</td>
+<td>Optional <em>parameters</em>.</td>
+</tr>
+<tr class="row-odd"><td>15:10</td>
+<td>Unused.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>This operand may be specified as a positive 16-bit <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a> or using the syntax described below:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>sendmsg(<<em>type</em>>)</td>
+<td>A message identified by its <em>type</em>.</td>
+</tr>
+<tr class="row-odd"><td>sendmsg(<<em>type</em>>, <<em>op</em>>)</td>
+<td>A message identified by its <em>type</em> and <em>operation</em>.</td>
+</tr>
+<tr class="row-even"><td>sendmsg(<<em>type</em>>, <<em>op</em>>, <<em>stream</em>>)</td>
+<td>A message identified by its <em>type</em> and <em>operation</em> with a stream <em>id</em>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p><em>Type</em> may be specified using message <em>name</em> or message <em>id</em>.</p>
+<p><em>Op</em> may be specified using operation <em>name</em> or operation <em>id</em>.</p>
+<p>Stream <em>id</em> is an integer in the range 0..3.</p>
+<p>Message <em>id</em>, operation <em>id</em> and stream <em>id</em> must be specified as positive <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
+<p>Each message type supports specific operations:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="22%" />
+<col width="13%" />
+<col width="38%" />
+<col width="15%" />
+<col width="13%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Message name</th>
+<th class="head">Message Id</th>
+<th class="head">Supported Operations</th>
+<th class="head">Operation Id</th>
+<th class="head">Stream Id</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>MSG_INTERRUPT</td>
+<td>1</td>
+<td>-</td>
+<td>-</td>
+<td>-</td>
+</tr>
+<tr class="row-odd"><td>MSG_GS</td>
+<td>2</td>
+<td>GS_OP_CUT</td>
+<td>1</td>
+<td>Optional</td>
+</tr>
+<tr class="row-even"><td></td>
+<td> </td>
+<td>GS_OP_EMIT</td>
+<td>2</td>
+<td>Optional</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td>GS_OP_EMIT_CUT</td>
+<td>3</td>
+<td>Optional</td>
+</tr>
+<tr class="row-even"><td>MSG_GS_DONE</td>
+<td>3</td>
+<td>GS_OP_NOP</td>
+<td>0</td>
+<td>-</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td>GS_OP_CUT</td>
+<td>1</td>
+<td>Optional</td>
+</tr>
+<tr class="row-even"><td></td>
+<td> </td>
+<td>GS_OP_EMIT</td>
+<td>2</td>
+<td>Optional</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td>GS_OP_EMIT_CUT</td>
+<td>3</td>
+<td>Optional</td>
+</tr>
+<tr class="row-even"><td>MSG_SYSMSG</td>
+<td>15</td>
+<td>SYSMSG_OP_ECC_ERR_INTERRUPT</td>
+<td>1</td>
+<td>-</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td>SYSMSG_OP_REG_RD</td>
+<td>2</td>
+<td>-</td>
+</tr>
+<tr class="row-even"><td></td>
+<td> </td>
+<td>SYSMSG_OP_HOST_TRAP_ACK</td>
+<td>3</td>
+<td>-</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td>SYSMSG_OP_TTRACE_PC</td>
+<td>4</td>
+<td>-</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s_sendmsg</span> <span class="mh">0x12</span>
+<span class="n">s_sendmsg</span> <span class="n">sendmsg</span><span class="p">(</span><span class="n">MSG_INTERRUPT</span><span class="p">)</span>
+<span class="n">s_sendmsg</span> <span class="n">sendmsg</span><span class="p">(</span><span class="mi">2</span><span class="p">,</span> <span class="n">GS_OP_CUT</span><span class="p">)</span>
+<span class="n">s_sendmsg</span> <span class="n">sendmsg</span><span class="p">(</span><span class="n">MSG_GS</span><span class="p">,</span> <span class="n">GS_OP_EMIT</span><span class="p">)</span>
+<span class="n">s_sendmsg</span> <span class="n">sendmsg</span><span class="p">(</span><span class="n">MSG_GS</span><span class="p">,</span> <span class="mi">2</span><span class="p">)</span>
+<span class="n">s_sendmsg</span> <span class="n">sendmsg</span><span class="p">(</span><span class="n">MSG_GS_DONE</span><span class="p">,</span> <span class="n">GS_OP_EMIT_CUT</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+<span class="n">s_sendmsg</span> <span class="n">sendmsg</span><span class="p">(</span><span class="n">MSG_SYSMSG</span><span class="p">,</span> <span class="n">SYSMSG_OP_TTRACE_PC</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_param.html" title="param"
+ >next</a> |</li>
+ <li class="right" >
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+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_buf.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_buf.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_buf.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_buf.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>soffset — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
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+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="soffset" href="gfx9_offset_smem_buf.html" />
+ <link rel="prev" title="vdst" href="gfx9_dst_mimg_regular_d16.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
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+ <h3>Navigation</h3>
+ <ul>
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+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
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+ accesskey="N">next</a> |</li>
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+ </ul>
+ </div>
+
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+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="soffset">
+<span id="amdgpu-synid9-offset-buf"></span><h1>soffset<a class="headerlink" href="#soffset" title="Permalink to this headline">¶</a></h1>
+<p>An unsigned byte offset.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
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+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
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+ >next</a> |</li>
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+ >previous</a> |</li>
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+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
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+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_buf.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_buf.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_buf.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_buf.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,99 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>soffset — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
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+ <link rel="prev" title="soffset" href="gfx9_offset_buf.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
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+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
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+ accesskey="I">index</a></li>
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+ accesskey="N">next</a> |</li>
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+ <a href="gfx9_offset_buf.html" title="soffset"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
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+
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+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
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+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="soffset">
+<span id="amdgpu-synid9-offset-smem-buf"></span><h1>soffset<a class="headerlink" href="#soffset" title="Permalink to this headline">¶</a></h1>
+<p>An unsigned byte offset added to the base address to get memory address.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Assembler currently supports 20-bit offsets only. Use <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-uimm20"><span class="std std-ref">uimm20</span></a> instead of <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-uimm21"><span class="std std-ref">uimm21</span></a>.</p>
+</div>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-uimm21"><span class="std std-ref">uimm21</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_offset_smem_plain.html" title="soffset"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_offset_buf.html" title="soffset"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_plain.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_plain.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_plain.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_offset_smem_plain.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,103 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>soffset — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="srsrc" href="gfx9_rsrc_buf.html" />
+ <link rel="prev" title="soffset" href="gfx9_offset_smem_buf.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_rsrc_buf.html" title="srsrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_offset_smem_buf.html" title="soffset"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="soffset">
+<span id="amdgpu-synid9-offset-smem-plain"></span><h1>soffset<a class="headerlink" href="#soffset" title="Permalink to this headline">¶</a></h1>
+<p>An offset added to the base address to get memory address.</p>
+<ul class="simple">
+<li>If offset is specified as a register, it supplies an unsigned byte offset.</li>
+<li>If offset is specified as a 21-bit immediate, it supplies a signed byte offset.</li>
+</ul>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Assembler currently supports 20-bit unsigned offsets only. Use <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-uimm20"><span class="std std-ref">uimm20</span></a> instead of <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-simm21"><span class="std std-ref">simm21</span></a>.</p>
+</div>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-simm21"><span class="std std-ref">simm21</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_rsrc_buf.html" title="srsrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_offset_smem_buf.html" title="soffset"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_opt.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_opt.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_opt.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_opt.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>opt — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="dst" href="gfx9_ret.html" />
+ <link rel="prev" title="m" href="gfx9_mod_vop3_abs_neg.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ret.html" title="dst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_mod_vop3_abs_neg.html" title="m"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="opt">
+<span id="amdgpu-synid9-opt"></span><h1>opt<a class="headerlink" href="#opt" title="Permalink to this headline">¶</a></h1>
+<p>This is an optional operand. It must be used if and only if <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-glc"><span class="std std-ref">glc</span></a> is specified.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ret.html" title="dst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_mod_vop3_abs_neg.html" title="m"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_param.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_param.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_param.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_param.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,117 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>param — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="imm3" href="gfx9_perm_smem.html" />
+ <link rel="prev" title="msg" href="gfx9_msg.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_perm_smem.html" title="imm3"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_msg.html" title="msg"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="param">
+<span id="amdgpu-synid9-param"></span><h1>param<a class="headerlink" href="#param" title="Permalink to this headline">¶</a></h1>
+<p>Interpolation parameter to read:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="26%" />
+<col width="74%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>p0</td>
+<td>Parameter <em>P0</em>.</td>
+</tr>
+<tr class="row-odd"><td>p10</td>
+<td>Parameter <em>P10</em>.</td>
+</tr>
+<tr class="row-even"><td>p20</td>
+<td>Parameter <em>P20</em>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_perm_smem.html" title="imm3"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_msg.html" title="msg"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_perm_smem.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_perm_smem.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_perm_smem.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_perm_smem.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,118 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>imm3 — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="imm16" href="gfx9_simm16.html" />
+ <link rel="prev" title="param" href="gfx9_param.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_simm16.html" title="imm16"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_param.html" title="param"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="imm3">
+<span id="amdgpu-synid9-perm-smem"></span><h1>imm3<a class="headerlink" href="#imm3" title="Permalink to this headline">¶</a></h1>
+<p>A bit mask which indicates request permissions.</p>
+<p>This operand must be specified as an <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>. The value is truncated to 7 bits, but only 3 low bits are significant.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="29%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bit Number</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Request <em>read</em> permission.</td>
+</tr>
+<tr class="row-odd"><td>1</td>
+<td>Request <em>write</em> permission.</td>
+</tr>
+<tr class="row-even"><td>2</td>
+<td>Request <em>execute</em> permission.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_simm16.html" title="imm16"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_param.html" title="param"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ret.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ret.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ret.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ret.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>dst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="Type deviation" href="gfx9_type_dev.html" />
+ <link rel="prev" title="opt" href="gfx9_opt.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_type_dev.html" title="Type deviation"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_opt.html" title="opt"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="dst">
+<span id="amdgpu-synid9-ret"></span><h1>dst<a class="headerlink" href="#dst" title="Permalink to this headline">¶</a></h1>
+<p>This is an input operand. It may optionally serve as a destination if <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-glc"><span class="std std-ref">glc</span></a> is specified.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_type_dev.html" title="Type deviation"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_opt.html" title="opt"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_buf.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_buf.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_buf.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_buf.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>srsrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="srsrc" href="gfx9_rsrc_mimg.html" />
+ <link rel="prev" title="soffset" href="gfx9_offset_smem_plain.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_rsrc_mimg.html" title="srsrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_offset_smem_plain.html" title="soffset"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="srsrc">
+<span id="amdgpu-synid9-rsrc-buf"></span><h1>srsrc<a class="headerlink" href="#srsrc" title="Permalink to this headline">¶</a></h1>
+<p>Buffer resource constant which defines the address and characteristics of the buffer in memory.</p>
+<p><em>Size:</em> 4 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_rsrc_mimg.html" title="srsrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_offset_smem_plain.html" title="soffset"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_mimg.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_mimg.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_mimg.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_rsrc_mimg.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>srsrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="saddr" href="gfx9_saddr_flat_global.html" />
+ <link rel="prev" title="srsrc" href="gfx9_rsrc_buf.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_global.html" title="saddr"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_rsrc_buf.html" title="srsrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="srsrc">
+<span id="amdgpu-synid9-rsrc-mimg"></span><h1>srsrc<a class="headerlink" href="#srsrc" title="Permalink to this headline">¶</a></h1>
+<p>Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.</p>
+<p><em>Size:</em> 8 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_global.html" title="saddr"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_rsrc_buf.html" title="srsrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_global.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_global.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_global.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_global.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,96 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>saddr — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="saddr" href="gfx9_saddr_flat_scratch.html" />
+ <link rel="prev" title="srsrc" href="gfx9_rsrc_mimg.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_scratch.html" title="saddr"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_rsrc_mimg.html" title="srsrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="saddr">
+<span id="amdgpu-synid9-saddr-flat-global"></span><h1>saddr<a class="headerlink" href="#saddr" title="Permalink to this headline">¶</a></h1>
+<p>An optional 64-bit flat global address. Must be specified as <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a> if not used.</p>
+<p>See <a class="reference internal" href="gfx9_vaddr_flat_global.html#amdgpu-synid9-vaddr-flat-global"><span class="std std-ref">vaddr</span></a> for description of available addressing modes.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_scratch.html" title="saddr"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_rsrc_mimg.html" title="srsrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_scratch.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_scratch.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_scratch.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_saddr_flat_scratch.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,96 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>saddr — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssamp" href="gfx9_samp_mimg.html" />
+ <link rel="prev" title="saddr" href="gfx9_saddr_flat_global.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_samp_mimg.html" title="ssamp"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_global.html" title="saddr"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="saddr">
+<span id="amdgpu-synid9-saddr-flat-scratch"></span><h1>saddr<a class="headerlink" href="#saddr" title="Permalink to this headline">¶</a></h1>
+<p>An optional 32-bit flat scratch offset. Must be specified as <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a> if not used.</p>
+<p>Either this operand or <a class="reference internal" href="gfx9_vaddr_flat_scratch.html#amdgpu-synid9-vaddr-flat-scratch"><span class="std std-ref">vaddr</span></a> must be set to <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a>.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_samp_mimg.html" title="ssamp"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_global.html" title="saddr"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_samp_mimg.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_samp_mimg.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_samp_mimg.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_samp_mimg.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssamp — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdata" href="gfx9_sdata128_0.html" />
+ <link rel="prev" title="saddr" href="gfx9_saddr_flat_scratch.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdata128_0.html" title="sdata"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_scratch.html" title="saddr"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssamp">
+<span id="amdgpu-synid9-samp-mimg"></span><h1>ssamp<a class="headerlink" href="#ssamp" title="Permalink to this headline">¶</a></h1>
+<p>Sampler constant used to specify filtering options applied to the image data after it is read.</p>
+<p><em>Size:</em> 4 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdata128_0.html" title="sdata"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_saddr_flat_scratch.html" title="saddr"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata128_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata128_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata128_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata128_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdata — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdata" href="gfx9_sdata32_0.html" />
+ <link rel="prev" title="ssamp" href="gfx9_samp_mimg.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdata32_0.html" title="sdata"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_samp_mimg.html" title="ssamp"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdata">
+<span id="amdgpu-synid9-sdata128-0"></span><h1>sdata<a class="headerlink" href="#sdata" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 4 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdata32_0.html" title="sdata"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_samp_mimg.html" title="ssamp"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata32_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata32_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata32_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata32_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdata — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdata" href="gfx9_sdata64_0.html" />
+ <link rel="prev" title="sdata" href="gfx9_sdata128_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdata64_0.html" title="sdata"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdata128_0.html" title="sdata"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdata">
+<span id="amdgpu-synid9-sdata32-0"></span><h1>sdata<a class="headerlink" href="#sdata" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdata64_0.html" title="sdata"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdata128_0.html" title="sdata"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata64_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata64_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata64_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdata64_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdata — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst128_0.html" />
+ <link rel="prev" title="sdata" href="gfx9_sdata32_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst128_0.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdata32_0.html" title="sdata"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdata">
+<span id="amdgpu-synid9-sdata64-0"></span><h1>sdata<a class="headerlink" href="#sdata" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst128_0.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdata32_0.html" title="sdata"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst128_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst128_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst128_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst128_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst256_0.html" />
+ <link rel="prev" title="sdata" href="gfx9_sdata64_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst256_0.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdata64_0.html" title="sdata"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst128-0"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 4 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst256_0.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdata64_0.html" title="sdata"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst256_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst256_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst256_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst256_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst32_0.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst128_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst32_0.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst128_0.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst256-0"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 8 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst32_0.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst128_0.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst32_1.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst256_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst32_1.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst256_0.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst32-0"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst32_1.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst256_0.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_1.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_1.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_1.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_1.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst32_2.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst32_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst32_2.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst32_0.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst32-1"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst32_2.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst32_0.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_2.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_2.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_2.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst32_2.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst512_0.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst32_1.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst512_0.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst32_1.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst32-2"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst512_0.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst32_1.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst512_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst512_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst512_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst512_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst64_0.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst32_2.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst64_0.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst32_2.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst512-0"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 16 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst64_0.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst32_2.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="sdst" href="gfx9_sdst64_1.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst512_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst64_1.html" title="sdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst512_0.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst64-0"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_sdst64_1.html" title="sdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst512_0.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_1.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_1.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_1.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_sdst64_1.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>sdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="src" href="gfx9_src32_0.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst64_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_src32_0.html" title="src"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst64_0.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="sdst">
+<span id="amdgpu-synid9-sdst64-1"></span><h1>sdst<a class="headerlink" href="#sdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_src32_0.html" title="src"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst64_0.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_simm16.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_simm16.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_simm16.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_simm16.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>imm16 — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="tgt" href="gfx9_tgt.html" />
+ <link rel="prev" title="imm3" href="gfx9_perm_smem.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_tgt.html" title="tgt"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_perm_smem.html" title="imm3"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="imm16">
+<span id="amdgpu-synid9-simm16"></span><h1>imm16<a class="headerlink" href="#imm16" title="Permalink to this headline">¶</a></h1>
+<p>An <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>. The value is truncated to 16 bits and then sign-extended to 32 bits.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_tgt.html" title="tgt"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_perm_smem.html" title="imm3"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>src — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="src" href="gfx9_src32_1.html" />
+ <link rel="prev" title="sdst" href="gfx9_sdst64_1.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_src32_1.html" title="src"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst64_1.html" title="sdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="src">
+<span id="amdgpu-synid9-src32-0"></span><h1>src<a class="headerlink" href="#src" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-literal"><span class="std std-ref">literal</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_src32_1.html" title="src"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_sdst64_1.html" title="sdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_1.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_1.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_1.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src32_1.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>src — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="src" href="gfx9_src64_0.html" />
+ <link rel="prev" title="src" href="gfx9_src32_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_src64_0.html" title="src"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src32_0.html" title="src"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="src">
+<span id="amdgpu-synid9-src32-1"></span><h1>src<a class="headerlink" href="#src" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_src64_0.html" title="src"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src32_0.html" title="src"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>src — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="src" href="gfx9_src64_1.html" />
+ <link rel="prev" title="src" href="gfx9_src32_1.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_src64_1.html" title="src"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src32_1.html" title="src"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="src">
+<span id="amdgpu-synid9-src64-0"></span><h1>src<a class="headerlink" href="#src" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-literal"><span class="std std-ref">literal</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_src64_1.html" title="src"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src32_1.html" title="src"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_1.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_1.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_1.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src64_1.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>src — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vsrc" href="gfx9_src_exp.html" />
+ <link rel="prev" title="src" href="gfx9_src64_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_src_exp.html" title="vsrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src64_0.html" title="src"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="src">
+<span id="amdgpu-synid9-src64-1"></span><h1>src<a class="headerlink" href="#src" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_src_exp.html" title="vsrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src64_0.html" title="src"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src_exp.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src_exp.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src_exp.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_src_exp.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,104 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vsrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc32_0.html" />
+ <link rel="prev" title="src" href="gfx9_src64_1.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_0.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src64_1.html" title="src"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vsrc">
+<span id="amdgpu-synid9-src-exp"></span><h1>vsrc<a class="headerlink" href="#vsrc" title="Permalink to this headline">¶</a></h1>
+<p>Data to copy to export buffers. This is an optional operand. Must be specified as <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a> if not used.</p>
+<p><a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-compr"><span class="std std-ref">compr</span></a> modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:</p>
+<ul class="simple">
+<li>src0 and src1 must specify the first register (or <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a>).</li>
+<li>src2 and src3 must specify the second register (or <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a>).</li>
+</ul>
+<p>An example:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">exp</span> <span class="n">mrtz</span> <span class="n">v3</span><span class="p">,</span> <span class="n">v3</span><span class="p">,</span> <span class="n">off</span><span class="p">,</span> <span class="n">off</span> <span class="n">compr</span>
+</pre></div>
+</div>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_0.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src64_1.html" title="src"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc32_1.html" />
+ <link rel="prev" title="vsrc" href="gfx9_src_exp.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_1.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src_exp.html" title="vsrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc32-0"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-literal"><span class="std std-ref">literal</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_1.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_src_exp.html" title="vsrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_1.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_1.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_1.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_1.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc32_2.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc32_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_2.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_0.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc32-1"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_2.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_0.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_2.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_2.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_2.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_2.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc32_3.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc32_1.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_3.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_1.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc32-2"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_3.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_1.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_3.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_3.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_3.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_3.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc32_4.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc32_2.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_4.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_2.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc32-3"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-iconst"><span class="std std-ref">iconst</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_4.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_2.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_4.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_4.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_4.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc32_4.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc64_0.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc32_3.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_0.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_3.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc32-4"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-m0"><span class="std std-ref">m0</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_0.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_3.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc64_1.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc32_4.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_1.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_4.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc64-0"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-literal"><span class="std std-ref">literal</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_1.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc32_4.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_1.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_1.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_1.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_1.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc64_2.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc64_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_2.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_0.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc64-1"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_2.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_0.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_2.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_2.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_2.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_2.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="ssrc" href="gfx9_ssrc64_3.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc64_1.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_3.html" title="ssrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_1.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc64-2"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-constant"><span class="std std-ref">constant</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_3.html" title="ssrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_1.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_3.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_3.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_3.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_ssrc64_3.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>ssrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vaddr" href="gfx9_vaddr_flat_global.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc64_2.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vaddr_flat_global.html" title="vaddr"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_2.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="ssrc">
+<span id="amdgpu-synid9-ssrc64-3"></span><h1>ssrc<a class="headerlink" href="#ssrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-s"><span class="std std-ref">s</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-flat-scratch"><span class="std std-ref">flat_scratch</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-xnack"><span class="std std-ref">xnack</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vaddr_flat_global.html" title="vaddr"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_2.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_tgt.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_tgt.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_tgt.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_tgt.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,123 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>tgt — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="imm16" href="gfx9_uimm16.html" />
+ <link rel="prev" title="imm16" href="gfx9_simm16.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_uimm16.html" title="imm16"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_simm16.html" title="imm16"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="tgt">
+<span id="amdgpu-synid9-tgt"></span><h1>tgt<a class="headerlink" href="#tgt" title="Permalink to this headline">¶</a></h1>
+<p>An export target:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="29%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>pos{0..3}</td>
+<td>Copy vertex position 0..3.</td>
+</tr>
+<tr class="row-odd"><td>param{0..31}</td>
+<td>Copy vertex parameter 0..31.</td>
+</tr>
+<tr class="row-even"><td>mrt{0..7}</td>
+<td>Copy pixel color to the MRTs 0..7.</td>
+</tr>
+<tr class="row-odd"><td>mrtz</td>
+<td>Copy pixel depth (Z) data.</td>
+</tr>
+<tr class="row-even"><td>null</td>
+<td>Copy nothing.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_uimm16.html" title="imm16"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_simm16.html" title="imm16"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_type_dev.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_type_dev.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_type_dev.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_type_dev.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>Type deviation — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="Syntax of AMDGPU Instruction Modifiers" href="../AMDGPUModifierSyntax.html" />
+ <link rel="prev" title="dst" href="gfx9_ret.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="../AMDGPUModifierSyntax.html" title="Syntax of AMDGPU Instruction Modifiers"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ret.html" title="dst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="type-deviation">
+<span id="amdgpu-synid9-type-dev"></span><h1>Type deviation<a class="headerlink" href="#type-deviation" title="Permalink to this headline">¶</a></h1>
+<p><em>Type</em> of this operand differs from <em>type</em> <a class="reference internal" href="../AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">implied by the opcode</span></a>. This tag specifies actual operand <em>type</em>.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="../AMDGPUModifierSyntax.html" title="Syntax of AMDGPU Instruction Modifiers"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ret.html" title="dst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_uimm16.html
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==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_uimm16.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_uimm16.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,93 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>imm16 — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="waitcnt" href="gfx9_waitcnt.html" />
+ <link rel="prev" title="tgt" href="gfx9_tgt.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_waitcnt.html" title="waitcnt"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_tgt.html" title="tgt"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="imm16">
+<span id="amdgpu-synid9-uimm16"></span><h1>imm16<a class="headerlink" href="#imm16" title="Permalink to this headline">¶</a></h1>
+<p>An <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>. The value is truncated to 16 bits and then zero-extended to 32 bits.</p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_waitcnt.html" title="waitcnt"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_tgt.html" title="tgt"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vaddr_flat_global.html
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==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vaddr_flat_global.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vaddr_flat_global.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,103 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vaddr — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
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+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vaddr" href="gfx9_vaddr_flat_scratch.html" />
+ <link rel="prev" title="ssrc" href="gfx9_ssrc64_3.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
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+ <h3>Navigation</h3>
+ <ul>
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+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vaddr_flat_scratch.html" title="vaddr"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_3.html" title="ssrc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vaddr">
+<span id="amdgpu-synid9-vaddr-flat-global"></span><h1>vaddr<a class="headerlink" href="#vaddr" title="Permalink to this headline">¶</a></h1>
+<p>A 64-bit flat global address or a 32-bit offset depending on addressing mode:</p>
+<ul class="simple">
+<li>Address = <a class="reference internal" href="#amdgpu-synid9-vaddr-flat-global"><span class="std std-ref">vaddr</span></a> + <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-flat-offset13s"><span class="std std-ref">offset13s</span></a>. <a class="reference internal" href="#amdgpu-synid9-vaddr-flat-global"><span class="std std-ref">vaddr</span></a> is a 64-bit address. This mode is indicated by <a class="reference internal" href="gfx9_saddr_flat_global.html#amdgpu-synid9-saddr-flat-global"><span class="std std-ref">saddr</span></a> set to <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a>.</li>
+<li>Address = <a class="reference internal" href="gfx9_saddr_flat_global.html#amdgpu-synid9-saddr-flat-global"><span class="std std-ref">saddr</span></a> + <a class="reference internal" href="#amdgpu-synid9-vaddr-flat-global"><span class="std std-ref">vaddr</span></a> + <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-flat-offset13s"><span class="std std-ref">offset13s</span></a>. <a class="reference internal" href="#amdgpu-synid9-vaddr-flat-global"><span class="std std-ref">vaddr</span></a> is a 32-bit offset. This mode is used when <a class="reference internal" href="gfx9_saddr_flat_global.html#amdgpu-synid9-saddr-flat-global"><span class="std std-ref">saddr</span></a> is not <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a>.</li>
+</ul>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Assembler currently expects a 64-bit <em>vaddr</em> regardless of addressing mode. This have to be fixed.</p>
+</div>
+<p><em>Size:</em> 1 or 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vaddr_flat_scratch.html" title="vaddr"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_ssrc64_3.html" title="ssrc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vaddr_flat_scratch.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vaddr_flat_scratch.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vaddr_flat_scratch.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vaddr_flat_scratch.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,96 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vaddr — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
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+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vcc" href="gfx9_vcc_64.html" />
+ <link rel="prev" title="vaddr" href="gfx9_vaddr_flat_global.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vcc_64.html" title="vcc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vaddr_flat_global.html" title="vaddr"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vaddr">
+<span id="amdgpu-synid9-vaddr-flat-scratch"></span><h1>vaddr<a class="headerlink" href="#vaddr" title="Permalink to this headline">¶</a></h1>
+<p>An optional 32-bit flat scratch offset. Must be specified as <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a> if not used.</p>
+<p>Either this operand or <a class="reference internal" href="gfx9_saddr_flat_scratch.html#amdgpu-synid9-saddr-flat-scratch"><span class="std std-ref">saddr</span></a> must be set to <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a>.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a>, <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-off"><span class="std std-ref">off</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vcc_64.html" title="vcc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vaddr_flat_global.html" title="vaddr"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vcc_64.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vcc_64.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vcc_64.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vcc_64.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vcc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
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+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdata" href="gfx9_vdata128_0.html" />
+ <link rel="prev" title="vaddr" href="gfx9_vaddr_flat_scratch.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
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+ <a href="gfx9_vdata128_0.html" title="vdata"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
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+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vcc">
+<span id="amdgpu-synid9-vcc-64"></span><h1>vcc<a class="headerlink" href="#vcc" title="Permalink to this headline">¶</a></h1>
+<p>Vector condition code.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdata128_0.html" title="vdata"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vaddr_flat_scratch.html" title="vaddr"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata128_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata128_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata128_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata128_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdata — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdata" href="gfx9_vdata32_0.html" />
+ <link rel="prev" title="vcc" href="gfx9_vcc_64.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdata32_0.html" title="vdata"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vcc_64.html" title="vcc"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdata">
+<span id="amdgpu-synid9-vdata128-0"></span><h1>vdata<a class="headerlink" href="#vdata" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 4 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdata32_0.html" title="vdata"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vcc_64.html" title="vcc"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata32_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata32_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata32_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata32_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdata — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdata" href="gfx9_vdata64_0.html" />
+ <link rel="prev" title="vdata" href="gfx9_vdata128_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdata64_0.html" title="vdata"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata128_0.html" title="vdata"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdata">
+<span id="amdgpu-synid9-vdata32-0"></span><h1>vdata<a class="headerlink" href="#vdata" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdata64_0.html" title="vdata"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata128_0.html" title="vdata"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata64_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata64_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata64_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata64_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdata — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdata" href="gfx9_vdata96_0.html" />
+ <link rel="prev" title="vdata" href="gfx9_vdata32_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdata96_0.html" title="vdata"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata32_0.html" title="vdata"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdata">
+<span id="amdgpu-synid9-vdata64-0"></span><h1>vdata<a class="headerlink" href="#vdata" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdata96_0.html" title="vdata"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata32_0.html" title="vdata"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata96_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata96_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata96_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdata96_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdata — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_vdst128_0.html" />
+ <link rel="prev" title="vdata" href="gfx9_vdata64_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst128_0.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata64_0.html" title="vdata"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdata">
+<span id="amdgpu-synid9-vdata96-0"></span><h1>vdata<a class="headerlink" href="#vdata" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 3 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst128_0.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata64_0.html" title="vdata"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst128_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst128_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst128_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst128_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_vdst32_0.html" />
+ <link rel="prev" title="vdata" href="gfx9_vdata96_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst32_0.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata96_0.html" title="vdata"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-vdst128-0"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 4 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst32_0.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdata96_0.html" title="vdata"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst32_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst32_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst32_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst32_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_vdst64_0.html" />
+ <link rel="prev" title="vdst" href="gfx9_vdst128_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst64_0.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst128_0.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-vdst32-0"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst64_0.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst128_0.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst64_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst64_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst64_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst64_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vdst" href="gfx9_vdst96_0.html" />
+ <link rel="prev" title="vdst" href="gfx9_vdst32_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst96_0.html" title="vdst"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst32_0.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-vdst64-0"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vdst96_0.html" title="vdst"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst32_0.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst96_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst96_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst96_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vdst96_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vdst — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vsrc" href="gfx9_vsrc128_0.html" />
+ <link rel="prev" title="vdst" href="gfx9_vdst64_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vsrc128_0.html" title="vsrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst64_0.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vdst">
+<span id="amdgpu-synid9-vdst96-0"></span><h1>vdst<a class="headerlink" href="#vdst" title="Permalink to this headline">¶</a></h1>
+<p>Instruction output.</p>
+<p><em>Size:</em> 3 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vsrc128_0.html" title="vsrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst64_0.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc128_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc128_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc128_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc128_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+ <title>vsrc — LLVM 8 documentation</title>
+ <link rel="stylesheet" href="../_static/llvm-theme.css" type="text/css" />
+ <link rel="stylesheet" href="../_static/pygments.css" type="text/css" />
+ <script type="text/javascript" id="documentation_options" data-url_root="../" src="../_static/documentation_options.js"></script>
+ <script type="text/javascript" src="../_static/jquery.js"></script>
+ <script type="text/javascript" src="../_static/underscore.js"></script>
+ <script type="text/javascript" src="../_static/doctools.js"></script>
+ <link rel="index" title="Index" href="../genindex.html" />
+ <link rel="search" title="Search" href="../search.html" />
+ <link rel="next" title="vsrc" href="gfx9_vsrc32_0.html" />
+ <link rel="prev" title="vdst" href="gfx9_vdst96_0.html" />
+<style type="text/css">
+ table.right { float: right; margin-left: 20px; }
+ table.right td { border: 1px solid #ccc; }
+</style>
+
+ </head><body>
+<div class="logo">
+ <a href="../index.html">
+ <img src="../_static/logo.png"
+ alt="LLVM Logo" width="250" height="88"/></a>
+</div>
+
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="gfx9_vsrc32_0.html" title="vsrc"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst96_0.html" title="vdst"
+ accesskey="P">previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" accesskey="U">Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+
+
+ <div class="document">
+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="vsrc">
+<span id="amdgpu-synid9-vsrc128-0"></span><h1>vsrc<a class="headerlink" href="#vsrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 4 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="../genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="gfx9_vsrc32_0.html" title="vsrc"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="gfx9_vdst96_0.html" title="vdst"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="../index.html">Documentation</a>»</li>
+
+ <li class="nav-item nav-item-1"><a href="../AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
+ <li class="nav-item nav-item-2"><a href="AMDGPUAsmGFX9.html" >Syntax of GFX9 Instructions</a> »</li>
+ </ul>
+ </div>
+ <div class="footer" role="contentinfo">
+ © Copyright 2003-2019, LLVM Project.
+ Last updated on 2019-03-18.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.7.5.
+ </div>
+ </body>
+</html>
\ No newline at end of file
Added: www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc32_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc32_0.html?rev=356539&view=auto
==============================================================================
--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc32_0.html (added)
+++ www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_vsrc32_0.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,95 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
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+<span id="amdgpu-synid9-vsrc32-0"></span><h1>vsrc<a class="headerlink" href="#vsrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 1 dword.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
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+<span id="amdgpu-synid9-vsrc64-0"></span><h1>vsrc<a class="headerlink" href="#vsrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
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--- www-releases/trunk/8.0.0/docs/AMDGPU/gfx9_waitcnt.html (added)
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+ <title>waitcnt — LLVM 8 documentation</title>
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+
+ <div class="section" id="waitcnt">
+<span id="amdgpu-synid9-waitcnt"></span><h1>waitcnt<a class="headerlink" href="#waitcnt" title="Permalink to this headline">¶</a></h1>
+<p>Counts of outstanding instructions to wait for.</p>
+<p>The bits of this operand have the following meaning:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>3:0</td>
+<td>VM_CNT: vector memory operations count, lower bits.</td>
+</tr>
+<tr class="row-odd"><td>6:4</td>
+<td>EXP_CNT: export count.</td>
+</tr>
+<tr class="row-even"><td>11:8</td>
+<td>LGKM_CNT: LDS, GDS, Constant and Message count.</td>
+</tr>
+<tr class="row-odd"><td>15:14</td>
+<td>VM_CNT: vector memory operations count, upper bits.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>This operand may be specified as a positive 16-bit <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>
+or as a combination of the following symbolic helpers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vmcnt(<<em>N</em>>)</td>
+<td>VM_CNT value. <em>N</em> must not exceed the largest VM_CNT value.</td>
+</tr>
+<tr class="row-odd"><td>expcnt(<<em>N</em>>)</td>
+<td>EXP_CNT value. <em>N</em> must not exceed the largest EXP_CNT value.</td>
+</tr>
+<tr class="row-even"><td>lgkmcnt(<<em>N</em>>)</td>
+<td>LGKM_CNT value. <em>N</em> must not exceed the largest LGKM_CNT value.</td>
+</tr>
+<tr class="row-odd"><td>vmcnt_sat(<<em>N</em>>)</td>
+<td>VM_CNT value computed as min(<em>N</em>, the largest VM_CNT value).</td>
+</tr>
+<tr class="row-even"><td>expcnt_sat(<<em>N</em>>)</td>
+<td>EXP_CNT value computed as min(<em>N</em>, the largest EXP_CNT value).</td>
+</tr>
+<tr class="row-odd"><td>lgkmcnt_sat(<<em>N</em>>)</td>
+<td>LGKM_CNT value computed as min(<em>N</em>, the largest LGKM_CNT value).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>These helpers may be specified in any order. Ampersands and commas may be used as optional separators.</p>
+<p><em>N</em> is either an
+<a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a> or an
+<a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s_waitcnt</span> <span class="mi">0</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">)</span> <span class="n">lgkmcnt</span><span class="p">(</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">)</span> <span class="n">lgkmcnt</span><span class="p">(</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">),</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">),</span> <span class="n">lgkmcnt</span><span class="p">(</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="o">&</span> <span class="n">lgkmcnt_sat</span><span class="p">(</span><span class="mi">100</span><span class="p">)</span> <span class="o">&</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+
+
+ </div>
+ </div>
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+ accesskey="I">index</a></li>
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+ accesskey="N">next</a> |</li>
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+ accesskey="P">previous</a> |</li>
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+
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+
+ <div class="section" id="amdgpu-instructions-notation">
+<h1>AMDGPU Instructions Notation<a class="headerlink" href="#amdgpu-instructions-notation" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id4">Introduction</a></li>
+<li><a class="reference internal" href="#instructions" id="id5">Instructions</a><ul>
+<li><a class="reference internal" href="#notation" id="id6">Notation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#opcode" id="id7">Opcode</a><ul>
+<li><a class="reference internal" href="#id1" id="id8">Notation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#operands" id="id9">Operands</a><ul>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-operand-notation" id="id10">Notation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#modifiers" id="id11">Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-modifier-notation" id="id12">Notation</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<span id="amdgpu-syn-instruction-notation"></span><h2><a class="toc-backref" href="#id4">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.</p>
+<p>This notation mimics the <a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instructions"><span class="std std-ref">syntax of assembler instructions</span></a>
+except that instead of real operands and modifiers it provides references to their description.</p>
+</div>
+<div class="section" id="instructions">
+<h2><a class="toc-backref" href="#id5">Instructions</a><a class="headerlink" href="#instructions" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="notation">
+<h3><a class="toc-backref" href="#id6">Notation</a><a class="headerlink" href="#notation" title="Permalink to this headline">¶</a></h3>
+<p>This is the notation used to describe AMDGPU instructions:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-opcode-notation"><span class="std std-ref">opcode description</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-operands-notation"><span class="std std-ref">operands description</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-modifiers-notation"><span class="std std-ref">modifiers description</span></a><code class="docutils literal notranslate"><span class="pre">></span></code></div></blockquote>
+</div>
+</div>
+<div class="section" id="opcode">
+<span id="amdgpu-syn-opcode-notation"></span><h2><a class="toc-backref" href="#id7">Opcode</a><a class="headerlink" href="#opcode" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id1">
+<h3><a class="toc-backref" href="#id8">Notation</a><a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h3>
+<p>TBD</p>
+</div>
+</div>
+<div class="section" id="operands">
+<span id="amdgpu-syn-instruction-operands-notation"></span><h2><a class="toc-backref" href="#id9">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h2>
+<p>An instruction may have zero or more <em>operands</em>. They are comma-separated in the description:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-operand-notation"><span class="std std-ref">description of operand 0</span></a><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-operand-notation"><span class="std std-ref">description of operand 1</span></a><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre">...</span></code></div></blockquote>
+<p>The order of <em>operands</em> is fixed. <em>Operands</em> cannot be omitted
+except for special cases described below.</p>
+<div class="section" id="amdgpu-syn-instruction-operand-notation">
+<span id="id2"></span><h3><a class="toc-backref" href="#id10">Notation</a><a class="headerlink" href="#amdgpu-syn-instruction-operand-notation" title="Permalink to this headline">¶</a></h3>
+<p>An operand is described using the following notation:</p>
+<blockquote>
+<div><em><name><tag0><tag1>â¦</em></div></blockquote>
+<p>Where:</p>
+<ul class="simple">
+<li><em>name</em> is a link to a description of the operand.</li>
+<li><em>tags</em> are optional. They are used to indicate special operand properties:</li>
+</ul>
+<blockquote id="amdgpu-syn-instruction-operand-tags">
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="15%" />
+<col width="85%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Operand tag</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>:opt</td>
+<td>An optional operand.</td>
+</tr>
+<tr class="row-odd"><td>:m</td>
+<td>An operand which may be used with
+<a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-vop3-operand-modifiers"><span class="std std-ref">VOP3 operand modifiers</span></a> or
+<a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-sdwa-operand-modifiers"><span class="std std-ref">SDWA operand modifiers</span></a>.</td>
+</tr>
+<tr class="row-even"><td>:dst</td>
+<td>An input operand which may also serve as a destination
+if <a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-glc"><span class="std std-ref">glc</span></a> modifier is specified.</td>
+</tr>
+<tr class="row-odd"><td>:fx</td>
+<td>This is an <em>f32</em> or <em>f16</em> operand depending on
+<a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-mad-mix-op-sel-hi"><span class="std std-ref">m_op_sel_hi</span></a> modifier.</td>
+</tr>
+<tr class="row-even"><td>:<type></td>
+<td>Operand <em>type</em> differs from <em>type</em>
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">implied by the opcode name</span></a>.
+This tag specifies actual operand <em>type</em>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">src1</span><span class="p">:</span><span class="n">m</span> <span class="o">//</span> <span class="n">src1</span> <span class="n">operand</span> <span class="n">may</span> <span class="n">be</span> <span class="n">used</span> <span class="k">with</span> <span class="n">operand</span> <span class="n">modifiers</span>
+<span class="n">vdata</span><span class="p">:</span><span class="n">dst</span> <span class="o">//</span> <span class="n">vdata</span> <span class="n">operand</span> <span class="n">may</span> <span class="n">be</span> <span class="n">used</span> <span class="k">as</span> <span class="n">both</span> <span class="n">source</span> <span class="ow">and</span> <span class="n">destination</span>
+<span class="n">vdst</span><span class="p">:</span><span class="n">u32</span> <span class="o">//</span> <span class="n">vdst</span> <span class="n">operand</span> <span class="n">has</span> <span class="n">u32</span> <span class="nb">type</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="modifiers">
+<span id="amdgpu-syn-instruction-modifiers-notation"></span><h2><a class="toc-backref" href="#id11">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h2>
+<p>An instruction may have zero or more optional <em>modifiers</em>. They are space-separated in the description:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-modifier-notation"><span class="std std-ref">description of modifier 0</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-modifier-notation"><span class="std std-ref">description of modifier 1</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre">...</span></code></div></blockquote>
+<p>The order of <em>modifiers</em> is fixed.</p>
+<div class="section" id="amdgpu-syn-instruction-modifier-notation">
+<span id="id3"></span><h3><a class="toc-backref" href="#id12">Notation</a><a class="headerlink" href="#amdgpu-syn-instruction-modifier-notation" title="Permalink to this headline">¶</a></h3>
+<p>A <em>modifier</em> is described using the following notation:</p>
+<blockquote>
+<div><em><name></em></div></blockquote>
+<p>Where <em>name</em> is a link to a description of the <em>modifier</em>.</p>
+</div>
+</div>
+</div>
+
+
+ </div>
+ </div>
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+ </div>
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+
+ <div class="section" id="amdgpu-instruction-syntax">
+<h1>AMDGPU Instruction Syntax<a class="headerlink" href="#amdgpu-instruction-syntax" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#instructions" id="id3">Instructions</a><ul>
+<li><a class="reference internal" href="#syntax" id="id4">Syntax</a></li>
+<li><a class="reference internal" href="#opcode-mnemonic" id="id5">Opcode Mnemonic</a></li>
+<li><a class="reference internal" href="#type-and-size-suffices" id="id6">Type and Size Suffices</a></li>
+<li><a class="reference internal" href="#encoding-suffices" id="id7">Encoding Suffices</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#operands" id="id8">Operands</a><ul>
+<li><a class="reference internal" href="#id1" id="id9">Syntax</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#modifiers" id="id10">Modifiers</a><ul>
+<li><a class="reference internal" href="#id2" id="id11">Syntax</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="instructions">
+<span id="amdgpu-syn-instructions"></span><h2><a class="toc-backref" href="#id3">Instructions</a><a class="headerlink" href="#instructions" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="syntax">
+<h3><a class="toc-backref" href="#id4">Syntax</a><a class="headerlink" href="#syntax" title="Permalink to this headline">¶</a></h3>
+<p>An instruction has the following syntax:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><em>opcode mnemonic</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>operand0</em><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre"><</span></code><em>operand1</em><code class="docutils literal notranslate"><span class="pre">>,...</span> <span class="pre"><</span></code><em>modifier0</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>modifier1</em><code class="docutils literal notranslate"><span class="pre">>...</span></code></div></blockquote>
+<p><a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">Operands</span></a> are normally comma-separated while
+<a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">modifiers</span></a> are space-separated.</p>
+<p>The order of <em>operands</em> and <em>modifiers</em> is fixed.
+Most <em>modifiers</em> are optional and may be omitted.</p>
+</div>
+<div class="section" id="opcode-mnemonic">
+<span id="amdgpu-syn-instruction-mnemo"></span><h3><a class="toc-backref" href="#id5">Opcode Mnemonic</a><a class="headerlink" href="#opcode-mnemonic" title="Permalink to this headline">¶</a></h3>
+<p>Opcode mnemonic describes opcode semantics and may include one or more suffices in this order:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-syn-instruction-type"><span class="std std-ref">Destination operand type suffix</span></a>.</li>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-type"><span class="std std-ref">Source operand type suffix</span></a>.</li>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-enc"><span class="std std-ref">Encoding suffix</span></a>.</li>
+</ul>
+</div>
+<div class="section" id="type-and-size-suffices">
+<span id="amdgpu-syn-instruction-type"></span><h3><a class="toc-backref" href="#id6">Type and Size Suffices</a><a class="headerlink" href="#type-and-size-suffices" title="Permalink to this headline">¶</a></h3>
+<p>Instructions which operate with data have an implied type of <em>data</em> operands.
+This data type is specified as a suffix of instruction mnemonic.</p>
+<p>There are instructions which have 2 type suffices:
+the first is the data type of the destination operand,
+the second is the data type of source <em>data</em> operand(s).</p>
+<p>Note that data type specified by an instruction does not apply
+to other kinds of operands such as <em>addresses</em>, <em>offsets</em> and so on.</p>
+<p>The following table enumerates the most frequently used type suffices.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="52%" />
+<col width="27%" />
+<col width="20%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Type Suffices</th>
+<th class="head">Packed instruction?</th>
+<th class="head">Data Type</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>_b512, _b256, _b128, _b64, _b32, _b16, _b8</td>
+<td>No</td>
+<td>Bits.</td>
+</tr>
+<tr class="row-odd"><td>_u64, _u32, _u16, _u8</td>
+<td>No</td>
+<td>Unsigned integer.</td>
+</tr>
+<tr class="row-even"><td>_i64, _i32, _i16, _i8</td>
+<td>No</td>
+<td>Signed integer.</td>
+</tr>
+<tr class="row-odd"><td>_f64, _f32, _f16</td>
+<td>No</td>
+<td>Floating-point.</td>
+</tr>
+<tr class="row-even"><td>_b16, _u16, _i16, _f16</td>
+<td>Yes</td>
+<td>Packed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Instructions which have no type suffices are assumed to operate with typeless data.
+The size of data is specified by size suffices:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="23%" />
+<col width="26%" />
+<col width="51%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Size Suffix</th>
+<th class="head">Implied data type</th>
+<th class="head">Required register size in dwords</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>-</td>
+<td>b32</td>
+<td>1</td>
+</tr>
+<tr class="row-odd"><td>x2</td>
+<td>b64</td>
+<td>2</td>
+</tr>
+<tr class="row-even"><td>x3</td>
+<td>b96</td>
+<td>3</td>
+</tr>
+<tr class="row-odd"><td>x4</td>
+<td>b128</td>
+<td>4</td>
+</tr>
+<tr class="row-even"><td>x8</td>
+<td>b256</td>
+<td>8</td>
+</tr>
+<tr class="row-odd"><td>x16</td>
+<td>b512</td>
+<td>16</td>
+</tr>
+<tr class="row-even"><td>x</td>
+<td>b32</td>
+<td>1</td>
+</tr>
+<tr class="row-odd"><td>xy</td>
+<td>b64</td>
+<td>2</td>
+</tr>
+<tr class="row-even"><td>xyz</td>
+<td>b96</td>
+<td>3</td>
+</tr>
+<tr class="row-odd"><td>xyzw</td>
+<td>b128</td>
+<td>4</td>
+</tr>
+<tr class="row-even"><td>d16_x</td>
+<td>b16</td>
+<td>1</td>
+</tr>
+<tr class="row-odd"><td>d16_xy</td>
+<td>b16x2</td>
+<td>2 for GFX8.0, 1 for GFX8.1 and GFX9</td>
+</tr>
+<tr class="row-even"><td>d16_xyz</td>
+<td>b16x3</td>
+<td>3 for GFX8.0, 2 for GFX8.1 and GFX9</td>
+</tr>
+<tr class="row-odd"><td>d16_xyzw</td>
+<td>b16x4</td>
+<td>4 for GFX8.0, 2 for GFX8.1 and GFX9</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">There are exceptions from rules described above.
+Operands which have type different from type specified by the opcode are
+<a class="reference internal" href="AMDGPUInstructionNotation.html#amdgpu-syn-instruction-operand-tags"><span class="std std-ref">tagged</span></a> in the description.</p>
+</div>
+<p>Examples of instructions with different types of source and destination operands:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s_bcnt0_i32_b64</span>
+<span class="n">v_cvt_f32_u32</span>
+</pre></div>
+</div>
+<p>Examples of instructions with one data type:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">v_max3_f32</span>
+<span class="n">v_max3_i16</span>
+</pre></div>
+</div>
+<p>Examples of instructions which operate with packed data:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">v_pk_add_u16</span>
+<span class="n">v_pk_add_i16</span>
+<span class="n">v_pk_add_f16</span>
+</pre></div>
+</div>
+<p>Examples of typeless instructions which operate on b128 data:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">buffer_store_dwordx4</span>
+<span class="n">flat_load_dwordx4</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="encoding-suffices">
+<span id="amdgpu-syn-instruction-enc"></span><h3><a class="toc-backref" href="#id7">Encoding Suffices</a><a class="headerlink" href="#encoding-suffices" title="Permalink to this headline">¶</a></h3>
+<p>Most <em>VOP1</em>, <em>VOP2</em> and <em>VOPC</em> instructions have several variants:
+they may also be encoded in <em>VOP3</em>, <em>DPP</em> and <em>SDWA</em> formats.</p>
+<p>The assembler will automatically use optimal encoding based on instruction operands.
+To force specific encoding, one can add a suffix to the opcode of the instruction:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Encoding</th>
+<th class="head">Encoding Suffix</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Native 32-bit encoding (<em>VOP1</em>, <em>VOP2</em> or <em>VOPC</em>)</td>
+<td>_e32</td>
+</tr>
+<tr class="row-odd"><td><em>VOP3</em> (64-bit) encoding</td>
+<td>_e64</td>
+</tr>
+<tr class="row-even"><td><em>DPP</em> encoding</td>
+<td>_dpp</td>
+</tr>
+<tr class="row-odd"><td><em>SDWA</em> encoding</td>
+<td>_sdwa</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>These suffices are used in this reference to indicate the assumed encoding.
+When no suffix is specified, a native encoding is implied.</p>
+</div>
+</div>
+<div class="section" id="operands">
+<h2><a class="toc-backref" href="#id8">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id1">
+<h3><a class="toc-backref" href="#id9">Syntax</a><a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h3>
+<p>Syntax of most operands is described <a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">in this document</span></a>.</p>
+<p>For detailed information about operands follow <em>operand links</em> in GPU-specific documents:</p>
+<ul class="simple">
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX7.html"><span class="doc">GFX7</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX8.html"><span class="doc">GFX8</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX9.html"><span class="doc">GFX9</span></a></li>
+</ul>
+</div>
+</div>
+<div class="section" id="modifiers">
+<h2><a class="toc-backref" href="#id10">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id2">
+<h3><a class="toc-backref" href="#id11">Syntax</a><a class="headerlink" href="#id2" title="Permalink to this headline">¶</a></h3>
+<p>Syntax of modifiers is described <a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">in this document</span></a>.</p>
+<p>Information about modifiers supported for individual instructions may be found in GPU-specific documents:</p>
+<ul class="simple">
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX7.html"><span class="doc">GFX7</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX8.html"><span class="doc">GFX8</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX9.html"><span class="doc">GFX9</span></a></li>
+</ul>
+</div>
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+ <div class="section" id="syntax-of-amdgpu-instruction-modifiers">
+<h1>Syntax of AMDGPU Instruction Modifiers<a class="headerlink" href="#syntax-of-amdgpu-instruction-modifiers" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#conventions" id="id23">Conventions</a></li>
+<li><a class="reference internal" href="#modifiers" id="id24">Modifiers</a><ul>
+<li><a class="reference internal" href="#ds-modifiers" id="id25">DS Modifiers</a><ul>
+<li><a class="reference internal" href="#offset8" id="id26">offset8</a></li>
+<li><a class="reference internal" href="#offset16" id="id27">offset16</a></li>
+<li><a class="reference internal" href="#pattern" id="id28">pattern</a></li>
+<li><a class="reference internal" href="#gds" id="id29">gds</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#exp-modifiers" id="id30">EXP Modifiers</a><ul>
+<li><a class="reference internal" href="#done" id="id31">done</a></li>
+<li><a class="reference internal" href="#compr" id="id32">compr</a></li>
+<li><a class="reference internal" href="#vm" id="id33">vm</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#flat-modifiers" id="id34">FLAT Modifiers</a><ul>
+<li><a class="reference internal" href="#offset12" id="id35">offset12</a></li>
+<li><a class="reference internal" href="#offset13s" id="id36">offset13s</a></li>
+<li><a class="reference internal" href="#glc" id="id37">glc</a></li>
+<li><a class="reference internal" href="#slc" id="id38">slc</a></li>
+<li><a class="reference internal" href="#tfe" id="id39">tfe</a></li>
+<li><a class="reference internal" href="#nv" id="id40">nv</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#mimg-modifiers" id="id41">MIMG Modifiers</a><ul>
+<li><a class="reference internal" href="#dmask" id="id42">dmask</a></li>
+<li><a class="reference internal" href="#unorm" id="id43">unorm</a></li>
+<li><a class="reference internal" href="#id1" id="id44">glc</a></li>
+<li><a class="reference internal" href="#id2" id="id45">slc</a></li>
+<li><a class="reference internal" href="#r128" id="id46">r128</a></li>
+<li><a class="reference internal" href="#id3" id="id47">tfe</a></li>
+<li><a class="reference internal" href="#lwe" id="id48">lwe</a></li>
+<li><a class="reference internal" href="#da" id="id49">da</a></li>
+<li><a class="reference internal" href="#d16" id="id50">d16</a></li>
+<li><a class="reference internal" href="#a16" id="id51">a16</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#miscellaneous-modifiers" id="id52">Miscellaneous Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-glc" id="id53">glc</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-slc" id="id54">slc</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-tfe" id="id55">tfe</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-nv" id="id56">nv</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#mubuf-mtbuf-modifiers" id="id57">MUBUF/MTBUF Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-idxen" id="id58">idxen</a></li>
+<li><a class="reference internal" href="#offen" id="id59">offen</a></li>
+<li><a class="reference internal" href="#addr64" id="id60">addr64</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-buf-offset12" id="id61">offset12</a></li>
+<li><a class="reference internal" href="#id9" id="id62">glc</a></li>
+<li><a class="reference internal" href="#id10" id="id63">slc</a></li>
+<li><a class="reference internal" href="#lds" id="id64">lds</a></li>
+<li><a class="reference internal" href="#id11" id="id65">tfe</a></li>
+<li><a class="reference internal" href="#dfmt" id="id66">dfmt</a></li>
+<li><a class="reference internal" href="#nfmt" id="id67">nfmt</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#smrd-smem-modifiers" id="id68">SMRD/SMEM Modifiers</a><ul>
+<li><a class="reference internal" href="#id12" id="id69">glc</a></li>
+<li><a class="reference internal" href="#id13" id="id70">nv</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vintrp-modifiers" id="id71">VINTRP Modifiers</a><ul>
+<li><a class="reference internal" href="#high" id="id72">high</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop1-vop2-dpp-modifiers" id="id73">VOP1/VOP2 DPP Modifiers</a><ul>
+<li><a class="reference internal" href="#dpp-ctrl" id="id74">dpp_ctrl</a></li>
+<li><a class="reference internal" href="#row-mask" id="id75">row_mask</a></li>
+<li><a class="reference internal" href="#bank-mask" id="id76">bank_mask</a></li>
+<li><a class="reference internal" href="#bound-ctrl" id="id77">bound_ctrl</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop1-vop2-vopc-sdwa-modifiers" id="id78">VOP1/VOP2/VOPC SDWA Modifiers</a><ul>
+<li><a class="reference internal" href="#clamp" id="id79">clamp</a></li>
+<li><a class="reference internal" href="#omod" id="id80">omod</a></li>
+<li><a class="reference internal" href="#dst-sel" id="id81">dst_sel</a></li>
+<li><a class="reference internal" href="#dst-unused" id="id82">dst_unused</a></li>
+<li><a class="reference internal" href="#src0-sel" id="id83">src0_sel</a></li>
+<li><a class="reference internal" href="#src1-sel" id="id84">src1_sel</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop1-vop2-vopc-sdwa-operand-modifiers" id="id85">VOP1/VOP2/VOPC SDWA Operand Modifiers</a><ul>
+<li><a class="reference internal" href="#abs" id="id86">abs</a></li>
+<li><a class="reference internal" href="#neg" id="id87">neg</a></li>
+<li><a class="reference internal" href="#sext" id="id88">sext</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3-modifiers" id="id89">VOP3 Modifiers</a><ul>
+<li><a class="reference internal" href="#op-sel" id="id90">op_sel</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-clamp" id="id91">clamp</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-omod" id="id92">omod</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3-operand-modifiers" id="id93">VOP3 Operand Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-abs" id="id94">abs</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-neg" id="id95">neg</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3p-modifiers" id="id96">VOP3P Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-op-sel" id="id97">op_sel</a></li>
+<li><a class="reference internal" href="#op-sel-hi" id="id98">op_sel_hi</a></li>
+<li><a class="reference internal" href="#neg-lo" id="id99">neg_lo</a></li>
+<li><a class="reference internal" href="#neg-hi" id="id100">neg_hi</a></li>
+<li><a class="reference internal" href="#id19" id="id101">clamp</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3p-v-mad-mix-modifiers" id="id102">VOP3P V_MAD_MIX Modifiers</a><ul>
+<li><a class="reference internal" href="#m-op-sel" id="id103">m_op_sel</a></li>
+<li><a class="reference internal" href="#m-op-sel-hi" id="id104">m_op_sel_hi</a></li>
+<li><a class="reference internal" href="#id20" id="id105">abs</a></li>
+<li><a class="reference internal" href="#id21" id="id106">neg</a></li>
+<li><a class="reference internal" href="#id22" id="id107">clamp</a></li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="conventions">
+<h2><a class="toc-backref" href="#id23">Conventions</a><a class="headerlink" href="#conventions" title="Permalink to this headline">¶</a></h2>
+<p>The following notation is used throughout this document:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Notation</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>{0..N}</td>
+<td>Any integer value in the range from 0 to N (inclusive).</td>
+</tr>
+<tr class="row-odd"><td><x></td>
+<td>Syntax and meaning of <em>x</em> is explained elsewhere.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="modifiers">
+<span id="amdgpu-syn-modifiers"></span><h2><a class="toc-backref" href="#id24">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="ds-modifiers">
+<h3><a class="toc-backref" href="#id25">DS Modifiers</a><a class="headerlink" href="#ds-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="offset8">
+<span id="amdgpu-synid-ds-offset8"></span><h4><a class="toc-backref" href="#id26">offset8</a><a class="headerlink" href="#offset8" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0.</p>
+<p>Used with DS instructions which have 2 addresses.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="26%" />
+<col width="74%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFF}</td>
+<td>Specifies an unsigned 8-bit offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">255</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xff</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="offset16">
+<span id="amdgpu-synid-ds-offset16"></span><h4><a class="toc-backref" href="#id27">offset16</a><a class="headerlink" href="#offset16" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0.</p>
+<p>Used with DS instructions which have 1 address.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="27%" />
+<col width="73%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFFFF}</td>
+<td>Specifies an unsigned 16-bit offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">65535</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xffff</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="pattern">
+<span id="amdgpu-synid-sw-offset16"></span><h4><a class="toc-backref" href="#id28">pattern</a><a class="headerlink" href="#pattern" title="Permalink to this headline">¶</a></h4>
+<p>This is a special modifier which may be used with <em>ds_swizzle_b32</em> instruction only.
+It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.</p>
+<p>See AMD documentation for more information.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="48%" />
+<col width="52%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFFFF}</td>
+<td>Specifies a 16-bit swizzle pattern.</td>
+</tr>
+<tr class="row-odd"><td>offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3})</td>
+<td><p class="first">Specifies a quad permute mode pattern</p>
+<p class="last">Each number is a lane <em>id</em>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>offset:swizzle(BITMASK_PERM, â<mask>â)</td>
+<td><p class="first">Specifies a bitmask permute mode pattern.</p>
+<p>The pattern converts a 5-bit lane <em>id</em> to another
+lane <em>id</em> with which the lane interacts.</p>
+<p><em>mask</em> is a 5 character sequence which
+specifies how to transform the bits of the
+lane <em>id</em>.</p>
+<p>The following characters are allowed:</p>
+<ul class="last simple">
+<li>â0â - set bit to 0.</li>
+<li>â1â - set bit to 1.</li>
+<li>âpâ - preserve bit.</li>
+<li>âiâ - inverse bit.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>offset:swizzle(BROADCAST,{2..32},{0..N})</td>
+<td><p class="first">Specifies a broadcast mode.</p>
+<p>Broadcasts the value of any particular lane to
+all lanes in its group.</p>
+<p>The first numeric parameter is a group
+size and must be equal to 2, 4, 8, 16 or 32.</p>
+<p>The second numeric parameter is an index of the
+lane being broadcasted.</p>
+<p class="last">The index must not exceed group size.</p>
+</td>
+</tr>
+<tr class="row-even"><td>offset:swizzle(SWAP,{1..16})</td>
+<td><p class="first">Specifies a swap mode.</p>
+<p class="last">Swaps the neighboring groups of
+1, 2, 4, 8 or 16 lanes.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>offset:swizzle(REVERSE,{2..32})</td>
+<td><p class="first">Specifies a reverse mode.</p>
+<p class="last">Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Numeric parameters may be specified as either <a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a> or
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">255</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xffff</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">QUAD_PERM</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">2</span> <span class="p">,</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">BITMASK_PERM</span><span class="p">,</span> <span class="s2">"01pi0"</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">BROADCAST</span><span class="p">,</span> <span class="mi">2</span><span class="p">,</span> <span class="mi">0</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">SWAP</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">REVERSE</span><span class="p">,</span> <span class="mi">30</span> <span class="o">+</span> <span class="mi">2</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="gds">
+<span id="amdgpu-synid-gds"></span><h4><a class="toc-backref" href="#id29">gds</a><a class="headerlink" href="#gds" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether to use GDS or LDS memory (LDS is the default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>gds</td>
+<td>Use GDS memory.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="exp-modifiers">
+<h3><a class="toc-backref" href="#id30">EXP Modifiers</a><a class="headerlink" href="#exp-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="done">
+<span id="amdgpu-synid-done"></span><h4><a class="toc-backref" href="#id31">done</a><a class="headerlink" href="#done" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if this is the last export from the shader to the target. By default, current
+instruction does not finish an export sequence.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>done</td>
+<td>Indicates the last export operation.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="compr">
+<span id="amdgpu-synid-compr"></span><h4><a class="toc-backref" href="#id32">compr</a><a class="headerlink" href="#compr" title="Permalink to this headline">¶</a></h4>
+<p>Indicates if the data are compressed (data are not compressed by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>compr</td>
+<td>Data are compressed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="vm">
+<span id="amdgpu-synid-vm"></span><h4><a class="toc-backref" href="#id33">vm</a><a class="headerlink" href="#vm" title="Permalink to this headline">¶</a></h4>
+<p>Specifies valid mask flag state (off by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vm</td>
+<td>Set valid mask flag.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="flat-modifiers">
+<h3><a class="toc-backref" href="#id34">FLAT Modifiers</a><a class="headerlink" href="#flat-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="offset12">
+<span id="amdgpu-synid-flat-offset12"></span><h4><a class="toc-backref" href="#id35">offset12</a><a class="headerlink" href="#offset12" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.</p>
+<p>Cannot be used with <em>global/scratch</em> opcodes. GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..4095}</td>
+<td>Specifies a 12-bit unsigned offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">4095</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xff</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="offset13s">
+<span id="amdgpu-synid-flat-offset13s"></span><h4><a class="toc-backref" href="#id36">offset13s</a><a class="headerlink" href="#offset13s" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.</p>
+<p>Can be used with <em>global/scratch</em> opcodes only. GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="34%" />
+<col width="66%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{-4096..4095}</td>
+<td>Specifies a 13-bit signed offset as an
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="o">-</span><span class="mi">4000</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0x10</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="glc">
+<h4><a class="toc-backref" href="#id37">glc</a><a class="headerlink" href="#glc" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="slc">
+<h4><a class="toc-backref" href="#id38">slc</a><a class="headerlink" href="#slc" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-slc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="tfe">
+<h4><a class="toc-backref" href="#id39">tfe</a><a class="headerlink" href="#tfe" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-tfe"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="nv">
+<h4><a class="toc-backref" href="#id40">nv</a><a class="headerlink" href="#nv" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-nv"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+<div class="section" id="mimg-modifiers">
+<h3><a class="toc-backref" href="#id41">MIMG Modifiers</a><a class="headerlink" href="#mimg-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="dmask">
+<span id="amdgpu-synid-dmask"></span><h4><a class="toc-backref" href="#id42">dmask</a><a class="headerlink" href="#dmask" title="Permalink to this headline">¶</a></h4>
+<p>Specifies which channels (image components) are used by the operation. By default, no channels
+are used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="22%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dmask:{0..15}</td>
+<td><p class="first">Specifies image channels as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<p>Each bit corresponds to one of 4 image
+components (RGBA).</p>
+<p class="last">If the specified bit value
+is 0, the component is not used, value 1 means
+that the component is used.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>This modifier has some limitations depending on instruction kind:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="68%" />
+<col width="32%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Instruction Kind</th>
+<th class="head">Valid dmask Values</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>32-bit atomic <em>cmpswap</em></td>
+<td>0x3</td>
+</tr>
+<tr class="row-odd"><td>32-bit atomic instructions except for <em>cmpswap</em></td>
+<td>0x1</td>
+</tr>
+<tr class="row-even"><td>64-bit atomic <em>cmpswap</em></td>
+<td>0xF</td>
+</tr>
+<tr class="row-odd"><td>64-bit atomic instructions except for <em>cmpswap</em></td>
+<td>0x3</td>
+</tr>
+<tr class="row-even"><td><em>gather4</em></td>
+<td>0x1, 0x2, 0x4, 0x8</td>
+</tr>
+<tr class="row-odd"><td>Other instructions</td>
+<td>any value</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">dmask</span><span class="p">:</span><span class="mh">0xf</span>
+<span class="n">dmask</span><span class="p">:</span><span class="mb">0b1111</span>
+<span class="n">dmask</span><span class="p">:</span><span class="mi">3</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="unorm">
+<span id="amdgpu-synid-unorm"></span><h4><a class="toc-backref" href="#id43">unorm</a><a class="headerlink" href="#unorm" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether the address is normalized or not (the address is normalized by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="38%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>unorm</td>
+<td>Force the address to be unnormalized.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="id1">
+<h4><a class="toc-backref" href="#id44">glc</a><a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id2">
+<h4><a class="toc-backref" href="#id45">slc</a><a class="headerlink" href="#id2" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-slc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="r128">
+<span id="amdgpu-synid-r128"></span><h4><a class="toc-backref" href="#id46">r128</a><a class="headerlink" href="#r128" title="Permalink to this headline">¶</a></h4>
+<p>Specifies texture resource size. The default size is 256 bits.</p>
+<p>GFX7 and GFX8 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="28%" />
+<col width="72%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>r128</td>
+<td>Specifies 128 bits texture resource size.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Using this modifier should descrease <em>rsrc</em> operand size from 8 to 4 dwords, but assembler does not currently support this feature.</p>
+</div>
+</div>
+<div class="section" id="id3">
+<h4><a class="toc-backref" href="#id47">tfe</a><a class="headerlink" href="#id3" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-tfe"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="lwe">
+<span id="amdgpu-synid-lwe"></span><h4><a class="toc-backref" href="#id48">lwe</a><a class="headerlink" href="#lwe" title="Permalink to this headline">¶</a></h4>
+<p>Specifies LOD warning status (LOD warning is disabled by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>lwe</td>
+<td>Enables LOD warning.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="da">
+<span id="amdgpu-synid-da"></span><h4><a class="toc-backref" href="#id49">da</a><a class="headerlink" href="#da" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if an array index must be sent to TA. By default, array index is not sent.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>da</td>
+<td>Send an array-index to TA.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="d16">
+<span id="amdgpu-synid-d16"></span><h4><a class="toc-backref" href="#id50">d16</a><a class="headerlink" href="#d16" title="Permalink to this headline">¶</a></h4>
+<p>Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>d16</td>
+<td><p class="first">Enables 16-bits data mode.</p>
+<p>On loads, convert data in memory to 16-bit
+format before storing it in VGPRs.</p>
+<p>For stores, convert 16-bit data in VGPRs to
+32 bits before going to memory.</p>
+<p>Note that GFX8.0 does not support data packing.
+Each 16-bit data element occupies 1 VGPR.</p>
+<p class="last">GFX8.1 and GFX9 support data packing.
+Each pair of 16-bit data elements
+occupies 1 VGPR.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="a16">
+<span id="amdgpu-synid-a16"></span><h4><a class="toc-backref" href="#id51">a16</a><a class="headerlink" href="#a16" title="Permalink to this headline">¶</a></h4>
+<p>Specifies size of image address components: 16 or 32 bits (32 bits by default). GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>a16</td>
+<td>Enables 16-bits image address components.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="miscellaneous-modifiers">
+<h3><a class="toc-backref" href="#id52">Miscellaneous Modifiers</a><a class="headerlink" href="#miscellaneous-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="amdgpu-synid-glc">
+<span id="id4"></span><h4><a class="toc-backref" href="#id53">glc</a><a class="headerlink" href="#amdgpu-synid-glc" title="Permalink to this headline">¶</a></h4>
+<p>This modifier has different meaning for loads, stores, and atomic operations.
+The default value is off (0).</p>
+<p>See AMD documentation for details.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>glc</td>
+<td>Set glc bit to 1.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-slc">
+<span id="id5"></span><h4><a class="toc-backref" href="#id54">slc</a><a class="headerlink" href="#amdgpu-synid-slc" title="Permalink to this headline">¶</a></h4>
+<p>Specifies cache policy. The default value is off (0).</p>
+<p>See AMD documentation for details.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>slc</td>
+<td>Set slc bit to 1.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-tfe">
+<span id="id6"></span><h4><a class="toc-backref" href="#id55">tfe</a><a class="headerlink" href="#amdgpu-synid-tfe" title="Permalink to this headline">¶</a></h4>
+<p>Controls access to partially resident textures. The default value is off (0).</p>
+<p>See AMD documentation for details.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tfe</td>
+<td>Set tfe bit to 1.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-nv">
+<span id="id7"></span><h4><a class="toc-backref" href="#id56">nv</a><a class="headerlink" href="#amdgpu-synid-nv" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.</p>
+<p>GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>nv</td>
+<td>Indicates that instruction operates on
+non-volatile memory.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="mubuf-mtbuf-modifiers">
+<h3><a class="toc-backref" href="#id57">MUBUF/MTBUF Modifiers</a><a class="headerlink" href="#mubuf-mtbuf-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="amdgpu-synid-idxen">
+<span id="idxen"></span><h4><a class="toc-backref" href="#id58">idxen</a><a class="headerlink" href="#amdgpu-synid-idxen" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether address components include an index. By default, no components are used.</p>
+<p>Can be used together with <a class="reference internal" href="#amdgpu-synid-offen"><span class="std std-ref">offen</span></a>.</p>
+<p>Cannot be used with <a class="reference internal" href="#amdgpu-synid-addr64"><span class="std std-ref">addr64</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>idxen</td>
+<td>Address components include an index.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="offen">
+<span id="amdgpu-synid-offen"></span><h4><a class="toc-backref" href="#id59">offen</a><a class="headerlink" href="#offen" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether address components include an offset. By default, no components are used.</p>
+<p>Can be used together with <a class="reference internal" href="#amdgpu-synid-idxen"><span class="std std-ref">idxen</span></a>.</p>
+<p>Cannot be used with <a class="reference internal" href="#amdgpu-synid-addr64"><span class="std std-ref">addr64</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offen</td>
+<td>Address components include an offset.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="addr64">
+<span id="amdgpu-synid-addr64"></span><h4><a class="toc-backref" href="#id60">addr64</a><a class="headerlink" href="#addr64" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether a 64-bit address is used. By default, no address is used.</p>
+<p>GFX7 only. Cannot be used with <a class="reference internal" href="#amdgpu-synid-offen"><span class="std std-ref">offen</span></a> and
+<a class="reference internal" href="#amdgpu-synid-idxen"><span class="std std-ref">idxen</span></a> modifiers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>addr64</td>
+<td>A 64-bit address is used.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-buf-offset12">
+<span id="id8"></span><h4><a class="toc-backref" href="#id61">offset12</a><a class="headerlink" href="#amdgpu-synid-buf-offset12" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFFF}</td>
+<td>Specifies a 12-bit unsigned offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">0</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0x10</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="id9">
+<h4><a class="toc-backref" href="#id62">glc</a><a class="headerlink" href="#id9" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id10">
+<h4><a class="toc-backref" href="#id63">slc</a><a class="headerlink" href="#id10" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-slc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="lds">
+<span id="amdgpu-synid-lds"></span><h4><a class="toc-backref" href="#id64">lds</a><a class="headerlink" href="#lds" title="Permalink to this headline">¶</a></h4>
+<p>Specifies where to store the result: VGPRs or LDS (VGPRs by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="60%" />
+<col width="40%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>lds</td>
+<td>Store result in LDS.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="id11">
+<h4><a class="toc-backref" href="#id65">tfe</a><a class="headerlink" href="#id11" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-tfe"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="dfmt">
+<span id="amdgpu-synid-dfmt"></span><h4><a class="toc-backref" href="#id66">dfmt</a><a class="headerlink" href="#dfmt" title="Permalink to this headline">¶</a></h4>
+<p>TBD</p>
+</div>
+<div class="section" id="nfmt">
+<span id="amdgpu-synid-nfmt"></span><h4><a class="toc-backref" href="#id67">nfmt</a><a class="headerlink" href="#nfmt" title="Permalink to this headline">¶</a></h4>
+<p>TBD</p>
+</div>
+</div>
+<div class="section" id="smrd-smem-modifiers">
+<h3><a class="toc-backref" href="#id68">SMRD/SMEM Modifiers</a><a class="headerlink" href="#smrd-smem-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="id12">
+<h4><a class="toc-backref" href="#id69">glc</a><a class="headerlink" href="#id12" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id13">
+<h4><a class="toc-backref" href="#id70">nv</a><a class="headerlink" href="#id13" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-nv"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+<div class="section" id="vintrp-modifiers">
+<h3><a class="toc-backref" href="#id71">VINTRP Modifiers</a><a class="headerlink" href="#vintrp-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="high">
+<span id="amdgpu-synid-high"></span><h4><a class="toc-backref" href="#id72">high</a><a class="headerlink" href="#high" title="Permalink to this headline">¶</a></h4>
+<p>Specifies which half of the LDS word to use. Low half of LDS word is used by default.
+GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="56%" />
+<col width="44%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>high</td>
+<td>Use high half of LDS word.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="vop1-vop2-dpp-modifiers">
+<h3><a class="toc-backref" href="#id73">VOP1/VOP2 DPP Modifiers</a><a class="headerlink" href="#vop1-vop2-dpp-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>GFX8 and GFX9 only.</p>
+<div class="section" id="dpp-ctrl">
+<span id="amdgpu-synid-dpp-ctrl"></span><h4><a class="toc-backref" href="#id74">dpp_ctrl</a><a class="headerlink" href="#dpp-ctrl" title="Permalink to this headline">¶</a></h4>
+<p>Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.</p>
+<p>Note. The lanes of a wavefront are organized in four banks and four rows.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>quad_perm:[{0..3},{0..3},{0..3},{0..3}]</td>
+<td>Full permute of 4 threads.</td>
+</tr>
+<tr class="row-odd"><td>row_mirror</td>
+<td>Mirror threads within row.</td>
+</tr>
+<tr class="row-even"><td>row_half_mirror</td>
+<td>Mirror threads within 1/2 row (8 threads).</td>
+</tr>
+<tr class="row-odd"><td>row_bcast:15</td>
+<td>Broadcast 15th thread of each row to next row.</td>
+</tr>
+<tr class="row-even"><td>row_bcast:31</td>
+<td>Broadcast thread 31 to rows 2 and 3.</td>
+</tr>
+<tr class="row-odd"><td>wave_shl:1</td>
+<td>Wavefront left shift by 1 thread.</td>
+</tr>
+<tr class="row-even"><td>wave_rol:1</td>
+<td>Wavefront left rotate by 1 thread.</td>
+</tr>
+<tr class="row-odd"><td>wave_shr:1</td>
+<td>Wavefront right shift by 1 thread.</td>
+</tr>
+<tr class="row-even"><td>wave_ror:1</td>
+<td>Wavefront right rotate by 1 thread.</td>
+</tr>
+<tr class="row-odd"><td>row_shl:{1..15}</td>
+<td>Row shift left by 1-15 threads.</td>
+</tr>
+<tr class="row-even"><td>row_shr:{1..15}</td>
+<td>Row shift right by 1-15 threads.</td>
+</tr>
+<tr class="row-odd"><td>row_ror:{1..15}</td>
+<td>Row rotate right by 1-15 threads.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note: Numeric parameters may be specified as either
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a> or
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">quad_perm</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">2</span><span class="p">,</span> <span class="mi">3</span><span class="p">]</span>
+<span class="n">row_shl</span><span class="p">:</span><span class="mi">3</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="row-mask">
+<span id="amdgpu-synid-row-mask"></span><h4><a class="toc-backref" href="#id75">row_mask</a><a class="headerlink" href="#row-mask" title="Permalink to this headline">¶</a></h4>
+<p>Controls which rows are enabled for data sharing. By default, all rows are enabled.</p>
+<p>Note. The lanes of a wavefront are organized in four banks and four rows.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="43%" />
+<col width="57%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>row_mask:{0..15}</td>
+<td><p class="first">Specifies a <em>row mask</em> as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<p class="last">Each of 4 bits in the mask controls one
+row (0 - disabled, 1 - enabled).</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">row_mask</span><span class="p">:</span><span class="mh">0xf</span>
+<span class="n">row_mask</span><span class="p">:</span><span class="mb">0b1010</span>
+<span class="n">row_mask</span><span class="p">:</span><span class="mb">0b1111</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="bank-mask">
+<span id="amdgpu-synid-bank-mask"></span><h4><a class="toc-backref" href="#id76">bank_mask</a><a class="headerlink" href="#bank-mask" title="Permalink to this headline">¶</a></h4>
+<p>Controls which banks are enabled for data sharing. By default, all banks are enabled.</p>
+<p>Note. The lanes of a wavefront are organized in four banks and four rows.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="42%" />
+<col width="58%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>bank_mask:{0..15}</td>
+<td><p class="first">Specifies a <em>bank mask</em> as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<p class="last">Each of 4 bits in the mask controls one
+bank (0 - disabled, 1 - enabled).</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">bank_mask</span><span class="p">:</span><span class="mh">0x3</span>
+<span class="n">bank_mask</span><span class="p">:</span><span class="mb">0b0011</span>
+<span class="n">bank_mask</span><span class="p">:</span><span class="mb">0b1111</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="bound-ctrl">
+<span id="amdgpu-synid-bound-ctrl"></span><h4><a class="toc-backref" href="#id77">bound_ctrl</a><a class="headerlink" href="#bound-ctrl" title="Permalink to this headline">¶</a></h4>
+<p>Controls data sharing when accessing an invalid lane. By default, data sharing with
+invalid lanes is disabled.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>bound_ctrl:0</td>
+<td><p class="first">Enables data sharing with invalid lanes.</p>
+<p class="last">Accessing data from an invalid lane will
+return zero.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="vop1-vop2-vopc-sdwa-modifiers">
+<h3><a class="toc-backref" href="#id78">VOP1/VOP2/VOPC SDWA Modifiers</a><a class="headerlink" href="#vop1-vop2-vopc-sdwa-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>GFX8 and GFX9 only.</p>
+<div class="section" id="clamp">
+<h4><a class="toc-backref" href="#id79">clamp</a><a class="headerlink" href="#clamp" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="omod">
+<h4><a class="toc-backref" href="#id80">omod</a><a class="headerlink" href="#omod" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-omod"><span class="std std-ref">here</span></a>.</p>
+<p>GFX9 only.</p>
+</div>
+<div class="section" id="dst-sel">
+<span id="amdgpu-synid-dst-sel"></span><h4><a class="toc-backref" href="#id81">dst_sel</a><a class="headerlink" href="#dst-sel" title="Permalink to this headline">¶</a></h4>
+<p>Selects which bits in the destination are affected. By default, all bits are affected.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dst_sel:DWORD</td>
+<td>Use bits 31:0.</td>
+</tr>
+<tr class="row-odd"><td>dst_sel:BYTE_0</td>
+<td>Use bits 7:0.</td>
+</tr>
+<tr class="row-even"><td>dst_sel:BYTE_1</td>
+<td>Use bits 15:8.</td>
+</tr>
+<tr class="row-odd"><td>dst_sel:BYTE_2</td>
+<td>Use bits 23:16.</td>
+</tr>
+<tr class="row-even"><td>dst_sel:BYTE_3</td>
+<td>Use bits 31:24.</td>
+</tr>
+<tr class="row-odd"><td>dst_sel:WORD_0</td>
+<td>Use bits 15:0.</td>
+</tr>
+<tr class="row-even"><td>dst_sel:WORD_1</td>
+<td>Use bits 31:16.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="dst-unused">
+<span id="amdgpu-synid-dst-unused"></span><h4><a class="toc-backref" href="#id82">dst_unused</a><a class="headerlink" href="#dst-unused" title="Permalink to this headline">¶</a></h4>
+<p>Controls what to do with the bits in the destination which are not selected
+by <a class="reference internal" href="#amdgpu-synid-dst-sel"><span class="std std-ref">dst_sel</span></a>.
+By default, unused bits are preserved.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dst_unused:UNUSED_PAD</td>
+<td>Pad with zeros.</td>
+</tr>
+<tr class="row-odd"><td>dst_unused:UNUSED_SEXT</td>
+<td>Sign-extend upper bits, zero lower bits.</td>
+</tr>
+<tr class="row-even"><td>dst_unused:UNUSED_PRESERVE</td>
+<td>Preserve bits.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="src0-sel">
+<span id="amdgpu-synid-src0-sel"></span><h4><a class="toc-backref" href="#id83">src0_sel</a><a class="headerlink" href="#src0-sel" title="Permalink to this headline">¶</a></h4>
+<p>Controls which bits in the src0 are used. By default, all bits are used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>src0_sel:DWORD</td>
+<td>Use bits 31:0.</td>
+</tr>
+<tr class="row-odd"><td>src0_sel:BYTE_0</td>
+<td>Use bits 7:0.</td>
+</tr>
+<tr class="row-even"><td>src0_sel:BYTE_1</td>
+<td>Use bits 15:8.</td>
+</tr>
+<tr class="row-odd"><td>src0_sel:BYTE_2</td>
+<td>Use bits 23:16.</td>
+</tr>
+<tr class="row-even"><td>src0_sel:BYTE_3</td>
+<td>Use bits 31:24.</td>
+</tr>
+<tr class="row-odd"><td>src0_sel:WORD_0</td>
+<td>Use bits 15:0.</td>
+</tr>
+<tr class="row-even"><td>src0_sel:WORD_1</td>
+<td>Use bits 31:16.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="src1-sel">
+<span id="amdgpu-synid-src1-sel"></span><h4><a class="toc-backref" href="#id84">src1_sel</a><a class="headerlink" href="#src1-sel" title="Permalink to this headline">¶</a></h4>
+<p>Controls which bits in the src1 are used. By default, all bits are used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>src1_sel:DWORD</td>
+<td>Use bits 31:0.</td>
+</tr>
+<tr class="row-odd"><td>src1_sel:BYTE_0</td>
+<td>Use bits 7:0.</td>
+</tr>
+<tr class="row-even"><td>src1_sel:BYTE_1</td>
+<td>Use bits 15:8.</td>
+</tr>
+<tr class="row-odd"><td>src1_sel:BYTE_2</td>
+<td>Use bits 23:16.</td>
+</tr>
+<tr class="row-even"><td>src1_sel:BYTE_3</td>
+<td>Use bits 31:24.</td>
+</tr>
+<tr class="row-odd"><td>src1_sel:WORD_0</td>
+<td>Use bits 15:0.</td>
+</tr>
+<tr class="row-even"><td>src1_sel:WORD_1</td>
+<td>Use bits 31:16.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="vop1-vop2-vopc-sdwa-operand-modifiers">
+<span id="amdgpu-synid-sdwa-operand-modifiers"></span><h3><a class="toc-backref" href="#id85">VOP1/VOP2/VOPC SDWA Operand Modifiers</a><a class="headerlink" href="#vop1-vop2-vopc-sdwa-operand-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>Operand modifiers are not used separately. They are applied to source operands.</p>
+<p>GFX8 and GFX9 only.</p>
+<div class="section" id="abs">
+<h4><a class="toc-backref" href="#id86">abs</a><a class="headerlink" href="#abs" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-abs"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="neg">
+<h4><a class="toc-backref" href="#id87">neg</a><a class="headerlink" href="#neg" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-neg"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="sext">
+<span id="amdgpu-synid-sext"></span><h4><a class="toc-backref" href="#id88">sext</a><a class="headerlink" href="#sext" title="Permalink to this headline">¶</a></h4>
+<p>Sign-extends value of a (sub-dword) operand to fill all 32 bits.
+Has no effect for 32-bit operands.</p>
+<p>Valid for integer operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>sext(<operand>)</td>
+<td>Sign-extend operand value.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">sext</span><span class="p">(</span><span class="n">v4</span><span class="p">)</span>
+<span class="n">sext</span><span class="p">(</span><span class="n">v255</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="vop3-modifiers">
+<h3><a class="toc-backref" href="#id89">VOP3 Modifiers</a><a class="headerlink" href="#vop3-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="op-sel">
+<span id="amdgpu-synid-vop3-op-sel"></span><h4><a class="toc-backref" href="#id90">op_sel</a><a class="headerlink" href="#op-sel" title="Permalink to this headline">¶</a></h4>
+<p>Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
+By default, low bits are used for all operands.</p>
+<p>The number of values specified with the op_sel modifier must match the number of instruction
+operands (both source and destination). First value controls src0, second value controls src1
+and so on, except that the last value controls destination.
+The value 0 selects the low bits, while 1 selects the high bits.</p>
+<p>Note. op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
+by op_sel must be 0.</p>
+<p>GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="40%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel:[{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>op_sel:[{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>op_sel:[{0..1},{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="amdgpu-synid-clamp">
+<span id="id14"></span><h4><a class="toc-backref" href="#id91">clamp</a><a class="headerlink" href="#amdgpu-synid-clamp" title="Permalink to this headline">¶</a></h4>
+<p>Clamp meaning depends on instruction.</p>
+<p>For <em>v_cmp</em> instructions, clamp modifier indicates that the compare signals
+if a floating point exception occurs. By default, signaling is disabled.
+Not supported by GFX7.</p>
+<p>For integer operations, clamp modifier indicates that the result must be clamped
+to the largest and smallest representable value. By default, there is no clamping.
+Integer clamping is not supported by GFX7.</p>
+<p>For floating point operations, clamp modifier indicates that the result must be clamped
+to the range [0.0, 1.0]. By default, there is no clamping.</p>
+<p>Note. Clamp modifier is applied after <a class="reference internal" href="#amdgpu-synid-omod"><span class="std std-ref">output modifiers</span></a> (if any).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>clamp</td>
+<td>Enables clamping (or signaling).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-omod">
+<span id="id15"></span><h4><a class="toc-backref" href="#id92">omod</a><a class="headerlink" href="#amdgpu-synid-omod" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if an output modifier must be applied to the result.
+By default, no output modifiers are applied.</p>
+<p>Note. Output modifiers are applied before <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">clamping</span></a> (if any).</p>
+<p>Output modifiers are valid for f32 and f64 floating point results only.
+They must not be used with f16.</p>
+<p>Note. <em>v_cvt_f16_f32</em> is an exception. This instruction produces f16 result
+but accepts output modifiers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>mul:2</td>
+<td>Multiply the result by 2.</td>
+</tr>
+<tr class="row-odd"><td>mul:4</td>
+<td>Multiply the result by 4.</td>
+</tr>
+<tr class="row-even"><td>div:2</td>
+<td>Multiply the result by 0.5.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="vop3-operand-modifiers">
+<span id="amdgpu-synid-vop3-operand-modifiers"></span><h3><a class="toc-backref" href="#id93">VOP3 Operand Modifiers</a><a class="headerlink" href="#vop3-operand-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>Operand modifiers are not used separately. They are applied to source operands.</p>
+<div class="section" id="amdgpu-synid-abs">
+<span id="id16"></span><h4><a class="toc-backref" href="#id94">abs</a><a class="headerlink" href="#amdgpu-synid-abs" title="Permalink to this headline">¶</a></h4>
+<p>Computes absolute value of its operand. Applied before <a class="reference internal" href="#amdgpu-synid-neg"><span class="std std-ref">neg</span></a> (if any).
+Valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>abs(<operand>)</td>
+<td>Get absolute value of operand.</td>
+</tr>
+<tr class="row-odd"><td>|<operand>|</td>
+<td>The same as above.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<pre class="literal-block">
+abs(v36)
+|v36|
+</pre>
+</div>
+<div class="section" id="amdgpu-synid-neg">
+<span id="id17"></span><h4><a class="toc-backref" href="#id95">neg</a><a class="headerlink" href="#amdgpu-synid-neg" title="Permalink to this headline">¶</a></h4>
+<p>Computes negative value of its operand. Applied after <a class="reference internal" href="#amdgpu-synid-abs"><span class="std std-ref">abs</span></a> (if any).
+Valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>neg(<operand>)</td>
+<td>Get negative value of operand.</td>
+</tr>
+<tr class="row-odd"><td>-<operand></td>
+<td>The same as above.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">neg</span><span class="p">(</span><span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">])</span>
+<span class="o">-</span><span class="n">v4</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="vop3p-modifiers">
+<h3><a class="toc-backref" href="#id96">VOP3P Modifiers</a><a class="headerlink" href="#vop3p-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>This section describes modifiers of <em>regular</em> VOP3P instructions.</p>
+<p><em>v_mad_mix_f32</em>, <em>v_mad_mixhi_f16</em> and <em>v_mad_mixlo_f16</em>
+instructions use these modifiers <a class="reference internal" href="#amdgpu-synid-mad-mix"><span class="std std-ref">in a special manner</span></a>.</p>
+<p>GFX9 only.</p>
+<div class="section" id="amdgpu-synid-op-sel">
+<span id="id18"></span><h4><a class="toc-backref" href="#id97">op_sel</a><a class="headerlink" href="#amdgpu-synid-op-sel" title="Permalink to this headline">¶</a></h4>
+<p>Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the lower-half of the destination.
+By default, low bits are used for all operands.</p>
+<p>The number of values specified by the <em>op_sel</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 selects the low bits, while 1 selects the high bits.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="35%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel:[{0..1}]</td>
+<td>Select operand bits for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>op_sel:[{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>op_sel:[{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="op-sel-hi">
+<span id="amdgpu-synid-op-sel-hi"></span><h4><a class="toc-backref" href="#id98">op_sel_hi</a><a class="headerlink" href="#op-sel-hi" title="Permalink to this headline">¶</a></h4>
+<p>Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the upper-half of the destination.
+By default, high bits are used for all operands.</p>
+<p>The number of values specified by the <em>op_sel_hi</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 selects the low bits, while 1 selects the high bits.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel_hi:[{0..1}]</td>
+<td>Select operand bits for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>op_sel_hi:[{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>op_sel_hi:[{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel_hi</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">op_sel_hi</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="neg-lo">
+<span id="amdgpu-synid-neg-lo"></span><h4><a class="toc-backref" href="#id99">neg_lo</a><a class="headerlink" href="#neg-lo" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether to change sign of operand values selected by
+<a class="reference internal" href="#amdgpu-synid-op-sel"><span class="std std-ref">op_sel</span></a>. These values are then used
+as input to the operation which results in the upper-half of the destination.</p>
+<p>The number of values specified by this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.</p>
+<p>By default, operand values are used unmodified.</p>
+<p>This modifier is valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="33%" />
+<col width="67%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>neg_lo:[{0..1}]</td>
+<td>Select affected operands for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>neg_lo:[{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>neg_lo:[{0..1},{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">neg_lo</span><span class="p">:[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">neg_lo</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="neg-hi">
+<span id="amdgpu-synid-neg-hi"></span><h4><a class="toc-backref" href="#id100">neg_hi</a><a class="headerlink" href="#neg-hi" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether to change sign of operand values selected by
+<a class="reference internal" href="#amdgpu-synid-op-sel-hi"><span class="std std-ref">op_sel_hi</span></a>. These values are then used
+as input to the operation which results in the upper-half of the destination.</p>
+<p>The number of values specified by this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.</p>
+<p>By default, operand values are used unmodified.</p>
+<p>This modifier is valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="32%" />
+<col width="68%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>neg_hi:[{0..1}]</td>
+<td>Select affected operands for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>neg_hi:[{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>neg_hi:[{0..1},{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">neg_hi</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">neg_hi</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="id19">
+<h4><a class="toc-backref" href="#id101">clamp</a><a class="headerlink" href="#id19" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+<div class="section" id="vop3p-v-mad-mix-modifiers">
+<span id="amdgpu-synid-mad-mix"></span><h3><a class="toc-backref" href="#id102">VOP3P V_MAD_MIX Modifiers</a><a class="headerlink" href="#vop3p-v-mad-mix-modifiers" title="Permalink to this headline">¶</a></h3>
+<p><em>v_mad_mix_f32</em>, <em>v_mad_mixhi_f16</em> and <em>v_mad_mixlo_f16</em> instructions
+use <em>op_sel</em> and <em>op_sel_hi</em> modifiers
+in a manner different from <em>regular</em> VOP3P instructions.</p>
+<p>See a description below.</p>
+<p>GFX9 only.</p>
+<div class="section" id="m-op-sel">
+<span id="amdgpu-synid-mad-mix-op-sel"></span><h4><a class="toc-backref" href="#id103">m_op_sel</a><a class="headerlink" href="#m-op-sel" title="Permalink to this headline">¶</a></h4>
+<p>This operand has meaning only for 16-bit source operands as indicated by
+<a class="reference internal" href="#amdgpu-synid-mad-mix-op-sel-hi"><span class="std std-ref">m_op_sel_hi</span></a>.
+It specifies to select either the low [15:0] or high [31:16] operand bits
+as input to the operation.</p>
+<p>The number of values specified by the <em>op_sel</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates the low bits, the value 1 indicates the high 16 bits.</p>
+<p>By default, low bits are used for all operands.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="39%" />
+<col width="61%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel:[{0..1},{0..1},{0..1}]</td>
+<td>Select location of each 16-bit source operand.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="m-op-sel-hi">
+<span id="amdgpu-synid-mad-mix-op-sel-hi"></span><h4><a class="toc-backref" href="#id104">m_op_sel_hi</a><a class="headerlink" href="#m-op-sel-hi" title="Permalink to this headline">¶</a></h4>
+<p>Selects the size of source operands: either 32 bits or 16 bits.
+By default, 32 bits are used for all source operands.</p>
+<p>The number of values specified by the <em>op_sel_hi</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates 32 bits, the value 1 indicates 16 bits.</p>
+<p>The location of 16 bits in the operand may be specified by
+<a class="reference internal" href="#amdgpu-synid-mad-mix-op-sel"><span class="std std-ref">m_op_sel</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="53%" />
+<col width="47%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel_hi:[{0..1},{0..1},{0..1}]</td>
+<td>Select size of each source operand.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel_hi</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="id20">
+<h4><a class="toc-backref" href="#id105">abs</a><a class="headerlink" href="#id20" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-abs"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id21">
+<h4><a class="toc-backref" href="#id106">neg</a><a class="headerlink" href="#id21" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-neg"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id22">
+<h4><a class="toc-backref" href="#id107">clamp</a><a class="headerlink" href="#id22" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+</div>
+</div>
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+ <div class="section" id="syntax-of-amdgpu-instruction-operands">
+<h1>Syntax of AMDGPU Instruction Operands<a class="headerlink" href="#syntax-of-amdgpu-instruction-operands" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#conventions" id="id2">Conventions</a></li>
+<li><a class="reference internal" href="#operands" id="id3">Operands</a><ul>
+<li><a class="reference internal" href="#v" id="id4">v</a></li>
+<li><a class="reference internal" href="#s" id="id5">s</a></li>
+<li><a class="reference internal" href="#trap" id="id6">trap</a></li>
+<li><a class="reference internal" href="#ttmp" id="id7">ttmp</a></li>
+<li><a class="reference internal" href="#tba" id="id8">tba</a></li>
+<li><a class="reference internal" href="#tma" id="id9">tma</a></li>
+<li><a class="reference internal" href="#flat-scratch" id="id10">flat_scratch</a></li>
+<li><a class="reference internal" href="#xnack" id="id11">xnack</a></li>
+<li><a class="reference internal" href="#vcc" id="id12">vcc</a></li>
+<li><a class="reference internal" href="#m0" id="id13">m0</a></li>
+<li><a class="reference internal" href="#exec" id="id14">exec</a></li>
+<li><a class="reference internal" href="#vccz" id="id15">vccz</a></li>
+<li><a class="reference internal" href="#execz" id="id16">execz</a></li>
+<li><a class="reference internal" href="#scc" id="id17">scc</a></li>
+<li><a class="reference internal" href="#lds-direct" id="id18">lds_direct</a></li>
+<li><a class="reference internal" href="#constant" id="id19">constant</a></li>
+<li><a class="reference internal" href="#iconst" id="id20">iconst</a></li>
+<li><a class="reference internal" href="#fconst" id="id21">fconst</a></li>
+<li><a class="reference internal" href="#literal" id="id22">literal</a></li>
+<li><a class="reference internal" href="#uimm8" id="id23">uimm8</a></li>
+<li><a class="reference internal" href="#uimm32" id="id24">uimm32</a></li>
+<li><a class="reference internal" href="#uimm20" id="id25">uimm20</a></li>
+<li><a class="reference internal" href="#uimm21" id="id26">uimm21</a></li>
+<li><a class="reference internal" href="#simm21" id="id27">simm21</a></li>
+<li><a class="reference internal" href="#off" id="id28">off</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#numbers" id="id29">Numbers</a><ul>
+<li><a class="reference internal" href="#integer-numbers" id="id30">Integer Numbers</a></li>
+<li><a class="reference internal" href="#floating-point-numbers" id="id31">Floating-Point Numbers</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#expressions" id="id32">Expressions</a><ul>
+<li><a class="reference internal" href="#absolute-expressions" id="id33">Absolute Expressions</a></li>
+<li><a class="reference internal" href="#relocatable-expressions" id="id34">Relocatable Expressions</a></li>
+<li><a class="reference internal" href="#expression-data-type" id="id35">Expression Data Type</a></li>
+<li><a class="reference internal" href="#syntax" id="id36">Syntax</a></li>
+<li><a class="reference internal" href="#binary-operators" id="id37">Binary Operators</a></li>
+<li><a class="reference internal" href="#unary-operators" id="id38">Unary Operators</a></li>
+<li><a class="reference internal" href="#symbols" id="id39">Symbols</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#conversions" id="id40">Conversions</a><ul>
+<li><a class="reference internal" href="#inline-constants" id="id41">Inline Constants</a><ul>
+<li><a class="reference internal" href="#integer-inline-constants" id="id42">Integer Inline Constants</a></li>
+<li><a class="reference internal" href="#floating-point-inline-constants" id="id43">Floating-Point Inline Constants</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#literals" id="id44">Literals</a><ul>
+<li><a class="reference internal" href="#integer-literals" id="id45">Integer Literals</a></li>
+<li><a class="reference internal" href="#floating-point-literals" id="id46">Floating-Point Literals</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-exp-conv" id="id47">Expressions</a></li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="conventions">
+<h2><a class="toc-backref" href="#id2">Conventions</a><a class="headerlink" href="#conventions" title="Permalink to this headline">¶</a></h2>
+<p>The following notation is used throughout this document:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="20%" />
+<col width="80%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Notation</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>{0..N}</td>
+<td>Any integer value in the range from 0 to N (inclusive).</td>
+</tr>
+<tr class="row-odd"><td><x></td>
+<td>Syntax and meaning of <em>x</em> is explained elsewhere.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="operands">
+<span id="amdgpu-syn-operands"></span><h2><a class="toc-backref" href="#id3">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="v">
+<span id="amdgpu-synid-v"></span><h3><a class="toc-backref" href="#id4">v</a><a class="headerlink" href="#v" title="Permalink to this headline">¶</a></h3>
+<p>Vector registers. There are 256 32-bit vector registers.</p>
+<p>A sequence of <em>vector</em> registers may be used to operate with more than 32 bits of data.</p>
+<p>Assembler currently supports sequences of 1, 2, 3, 4, 8 and 16 <em>vector</em> registers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="43%" />
+<col width="57%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><strong>v</strong><N></td>
+<td><p class="first">A single 32-bit <em>vector</em> register.</p>
+<p class="last"><em>N</em> must be a decimal integer number.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>v[</strong><N><strong>]</strong></td>
+<td><p class="first">A single 32-bit <em>vector</em> register.</p>
+<p class="last"><em>N</em> may be specified as an
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+</td>
+</tr>
+<tr class="row-even"><td><strong>v[</strong><N>:<K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>vector</em> registers.</p>
+<p class="last"><em>N</em> and <em>K</em> may be specified as
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
+or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>[v</strong><N>, <strong>v</strong><N+1>, ⦠<strong>v</strong><K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>vector</em> registers.</p>
+<p class="last">Register indices must be specified as decimal integer numbers.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note. <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
+<ul class="simple">
+<li><em>N</em> <= <em>K</em>.</li>
+<li>0 <= <em>N</em> <= 255.</li>
+<li>0 <= <em>K</em> <= 255.</li>
+<li><em>K-N+1</em> must be equal to 1, 2, 3, 4, 8 or 16.</li>
+</ul>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">v255</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
+<span class="p">[</span><span class="n">v252</span><span class="p">]</span>
+<span class="p">[</span><span class="n">v252</span><span class="p">,</span><span class="n">v253</span><span class="p">,</span><span class="n">v254</span><span class="p">,</span><span class="n">v255</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="s">
+<span id="amdgpu-synid-s"></span><h3><a class="toc-backref" href="#id5">s</a><a class="headerlink" href="#s" title="Permalink to this headline">¶</a></h3>
+<p>Scalar 32-bit registers. The number of available <em>scalar</em> registers depends on GPU:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="20%" />
+<col width="80%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">GPU</th>
+<th class="head">Number of <em>scalar</em> registers</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>GFX7</td>
+<td>104</td>
+</tr>
+<tr class="row-odd"><td>GFX8</td>
+<td>102</td>
+</tr>
+<tr class="row-even"><td>GFX9</td>
+<td>102</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>A sequence of <em>scalar</em> registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 <em>scalar</em> registers.</p>
+<p>Pairs of <em>scalar</em> registers must be even-aligned (the first register must be even).
+Sequences of 4 and more <em>scalar</em> registers must be quad-aligned.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><strong>s</strong><N></td>
+<td><p class="first">A single 32-bit <em>scalar</em> register.</p>
+<p class="last"><em>N</em> must be a decimal integer number.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>s[</strong><N><strong>]</strong></td>
+<td><p class="first">A single 32-bit <em>scalar</em> register.</p>
+<p class="last"><em>N</em> may be specified as an
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+</td>
+</tr>
+<tr class="row-even"><td><strong>s[</strong><N>:<K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>scalar</em> registers.</p>
+<p class="last"><em>N</em> and <em>K</em> may be specified as
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
+or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>[s</strong><N>, <strong>s</strong><N+1>, ⦠<strong>s</strong><K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>scalar</em> registers.</p>
+<p class="last">Register indices must be specified as decimal integer numbers.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note. <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
+<ul class="simple">
+<li><em>N</em> must be properly aligned based on sequence size.</li>
+<li><em>N</em> <= <em>K</em>.</li>
+<li>0 <= <em>N</em> < <em>SMAX</em>, where <em>SMAX</em> is the number of available <em>scalar</em> registers.</li>
+<li>0 <= <em>K</em> < <em>SMAX</em>, where <em>SMAX</em> is the number of available <em>scalar</em> registers.</li>
+<li><em>K-N+1</em> must be equal to 1, 2, 4, 8 or 16.</li>
+</ul>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s0</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
+<span class="p">[</span><span class="n">s4</span><span class="p">]</span>
+<span class="p">[</span><span class="n">s4</span><span class="p">,</span><span class="n">s5</span><span class="p">,</span><span class="n">s6</span><span class="p">,</span><span class="n">s7</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>Examples of <em>scalar</em> registers with an invalid alignment:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="trap">
+<span id="amdgpu-synid-trap"></span><h3><a class="toc-backref" href="#id6">trap</a><a class="headerlink" href="#trap" title="Permalink to this headline">¶</a></h3>
+<p>A set of trap handler registers:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></li>
+<li><a class="reference internal" href="#amdgpu-synid-tba"><span class="std std-ref">tba</span></a></li>
+<li><a class="reference internal" href="#amdgpu-synid-tma"><span class="std std-ref">tma</span></a></li>
+</ul>
+</div>
+<div class="section" id="ttmp">
+<span id="amdgpu-synid-ttmp"></span><h3><a class="toc-backref" href="#id7">ttmp</a><a class="headerlink" href="#ttmp" title="Permalink to this headline">¶</a></h3>
+<p>Trap handler temporary scalar registers, 32-bits wide.
+The number of available <em>ttmp</em> registers depends on GPU:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="21%" />
+<col width="79%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">GPU</th>
+<th class="head">Number of <em>ttmp</em> registers</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>GFX7</td>
+<td>12</td>
+</tr>
+<tr class="row-odd"><td>GFX8</td>
+<td>12</td>
+</tr>
+<tr class="row-even"><td>GFX9</td>
+<td>16</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>A sequence of <em>ttmp</em> registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 <em>ttmp</em> registers.</p>
+<p>Pairs of <em>ttmp</em> registers must be even-aligned (the first register must be even).
+Sequences of 4 and more <em>ttmp</em> registers must be quad-aligned.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="47%" />
+<col width="53%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><strong>ttmp</strong><N></td>
+<td><p class="first">A single 32-bit <em>ttmp</em> register.</p>
+<p class="last"><em>N</em> must be a decimal integer number.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>ttmp[</strong><N><strong>]</strong></td>
+<td><p class="first">A single 32-bit <em>ttmp</em> register.</p>
+<p class="last"><em>N</em> may be specified as an
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+</td>
+</tr>
+<tr class="row-even"><td><strong>ttmp[</strong><N>:<K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>ttmp</em> registers.</p>
+<p class="last"><em>N</em> and <em>K</em> may be specified as
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
+or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>[ttmp</strong><N>, <strong>ttmp</strong><N+1>, ⦠<strong>ttmp</strong><K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>ttmp</em> registers.</p>
+<p class="last">Register indices must be specified as decimal integer numbers.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note. <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
+<ul class="simple">
+<li><em>N</em> must be properly aligned based on sequence size.</li>
+<li><em>N</em> <= <em>K</em>.</li>
+<li>0 <= <em>N</em> < <em>TMAX</em>, where <em>TMAX</em> is the number of available <em>ttmp</em> registers.</li>
+<li>0 <= <em>K</em> < <em>TMAX</em>, where <em>TMAX</em> is the number of available <em>ttmp</em> registers.</li>
+<li><em>K-N+1</em> must be equal to 1, 2, 4, 8 or 16.</li>
+</ul>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">ttmp0</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
+<span class="p">[</span><span class="n">ttmp4</span><span class="p">]</span>
+<span class="p">[</span><span class="n">ttmp4</span><span class="p">,</span><span class="n">ttmp5</span><span class="p">,</span><span class="n">ttmp6</span><span class="p">,</span><span class="n">ttmp7</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>Examples of <em>ttmp</em> registers with an invalid alignment:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="tba">
+<span id="amdgpu-synid-tba"></span><h3><a class="toc-backref" href="#id8">tba</a><a class="headerlink" href="#tba" title="Permalink to this headline">¶</a></h3>
+<p>Trap base address, 64-bits wide. Holds the pointer to the current trap handler program.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="70%" />
+<col width="13%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tba</td>
+<td>64-bit <em>trap base address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tba]</td>
+<td>64-bit <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tba_lo,tba_hi]</td>
+<td>64-bit <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>trap base address</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="70%" />
+<col width="13%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tba_lo</td>
+<td>Low 32 bits of <em>trap base address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>tba_hi</td>
+<td>High 32 bits of <em>trap base address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tba_lo]</td>
+<td>Low 32 bits of <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tba_hi]</td>
+<td>High 32 bits of <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note that <em>tba</em>, <em>tba_lo</em> and <em>tba_hi</em> are not accessible as assembler registers in GFX9,
+but <em>tba</em> is readable/writable with the help of <em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
+</div>
+<div class="section" id="tma">
+<span id="amdgpu-synid-tma"></span><h3><a class="toc-backref" href="#id9">tma</a><a class="headerlink" href="#tma" title="Permalink to this headline">¶</a></h3>
+<p>Trap memory address, 64-bits wide.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="16%" />
+<col width="67%" />
+<col width="17%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tma</td>
+<td>64-bit <em>trap memory address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tma]</td>
+<td>64-bit <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tma_lo,tma_hi]</td>
+<td>64-bit <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>trap memory address</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="16%" />
+<col width="67%" />
+<col width="17%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tma_lo</td>
+<td>Low 32 bits of <em>trap memory address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>tma_hi</td>
+<td>High 32 bits of <em>trap memory address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tma_lo]</td>
+<td>Low 32 bits of <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tma_hi]</td>
+<td>High 32 bits of <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note that <em>tma</em>, <em>tma_lo</em> and <em>tma_hi</em> are not accessible as assembler registers in GFX9,
+but <em>tma</em> is readable/writable with the help of <em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
+</div>
+<div class="section" id="flat-scratch">
+<span id="amdgpu-synid-flat-scratch"></span><h3><a class="toc-backref" href="#id10">flat_scratch</a><a class="headerlink" href="#flat-scratch" title="Permalink to this headline">¶</a></h3>
+<p>Flat scratch address, 64-bits wide. Holds the base address of scratch memory.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="35%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>flat_scratch</td>
+<td>64-bit <em>flat scratch</em> address register.</td>
+</tr>
+<tr class="row-odd"><td>[flat_scratch]</td>
+<td>64-bit <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[flat_scratch_lo,flat_scratch_hi]</td>
+<td>64-bit <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>flat scratch</em> address may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="26%" />
+<col width="74%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>flat_scratch_lo</td>
+<td>Low 32 bits of <em>flat scratch</em> address register.</td>
+</tr>
+<tr class="row-odd"><td>flat_scratch_hi</td>
+<td>High 32 bits of <em>flat scratch</em> address register.</td>
+</tr>
+<tr class="row-even"><td>[flat_scratch_lo]</td>
+<td>Low 32 bits of <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[flat_scratch_hi]</td>
+<td>High 32 bits of <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="xnack">
+<span id="amdgpu-synid-xnack"></span><h3><a class="toc-backref" href="#id11">xnack</a><a class="headerlink" href="#xnack" title="Permalink to this headline">¶</a></h3>
+<p>Xnack mask, 64-bits wide. Holds a 64-bit mask of which threads
+received an <em>XNACK</em> due to a vector memory operation.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">GFX7 does not support <em>xnack</em> feature. Not all GFX8 and GFX9 <a class="reference internal" href="AMDGPUUsage.html#amdgpu-processors"><span class="std std-ref">processors</span></a> support <em>xnack</em> feature.</p>
+</div>
+<p></p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>xnack_mask</td>
+<td>64-bit <em>xnack mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[xnack_mask]</td>
+<td>64-bit <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[xnack_mask_lo,xnack_mask_hi]</td>
+<td>64-bit <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>xnack mask</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="25%" />
+<col width="75%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>xnack_mask_lo</td>
+<td>Low 32 bits of <em>xnack mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>xnack_mask_hi</td>
+<td>High 32 bits of <em>xnack mask</em> register.</td>
+</tr>
+<tr class="row-even"><td>[xnack_mask_lo]</td>
+<td>Low 32 bits of <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[xnack_mask_hi]</td>
+<td>High 32 bits of <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="vcc">
+<span id="amdgpu-synid-vcc"></span><h3><a class="toc-backref" href="#id12">vcc</a><a class="headerlink" href="#vcc" title="Permalink to this headline">¶</a></h3>
+<p>Vector condition code, 64-bits wide. A bit mask with one bit per thread;
+it holds the result of a vector compare operation.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vcc</td>
+<td>64-bit <em>vector condition code</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[vcc]</td>
+<td>64-bit <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[vcc_lo,vcc_hi]</td>
+<td>64-bit <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>vector condition code</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vcc_lo</td>
+<td>Low 32 bits of <em>vector condition code</em> register.</td>
+</tr>
+<tr class="row-odd"><td>vcc_hi</td>
+<td>High 32 bits of <em>vector condition code</em> register.</td>
+</tr>
+<tr class="row-even"><td>[vcc_lo]</td>
+<td>Low 32 bits of <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[vcc_hi]</td>
+<td>High 32 bits of <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="m0">
+<span id="amdgpu-synid-m0"></span><h3><a class="toc-backref" href="#id13">m0</a><a class="headerlink" href="#m0" title="Permalink to this headline">¶</a></h3>
+<p>A 32-bit memory register. It has various uses,
+including register indexing and bounds checking.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>m0</td>
+<td>A 32-bit <em>memory</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[m0]</td>
+<td>A 32-bit <em>memory</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="exec">
+<span id="amdgpu-synid-exec"></span><h3><a class="toc-backref" href="#id14">exec</a><a class="headerlink" href="#exec" title="Permalink to this headline">¶</a></h3>
+<p>Execute mask, 64-bits wide. A bit mask with one bit per thread,
+which is applied to vector instructions and controls which threads execute
+and which ignore the instruction.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>exec</td>
+<td>64-bit <em>execute mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[exec]</td>
+<td>64-bit <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[exec_lo,exec_hi]</td>
+<td>64-bit <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>execute mask</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>exec_lo</td>
+<td>Low 32 bits of <em>execute mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>exec_hi</td>
+<td>High 32 bits of <em>execute mask</em> register.</td>
+</tr>
+<tr class="row-even"><td>[exec_lo]</td>
+<td>Low 32 bits of <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[exec_hi]</td>
+<td>High 32 bits of <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="vccz">
+<span id="amdgpu-synid-vccz"></span><h3><a class="toc-backref" href="#id15">vccz</a><a class="headerlink" href="#vccz" title="Permalink to this headline">¶</a></h3>
+<p>A single bit-flag indicating that the <a class="reference internal" href="#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a> is all zeros.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">This operand is not currently supported by AMDGPU assembler.</p>
+</div>
+</div>
+<div class="section" id="execz">
+<span id="amdgpu-synid-execz"></span><h3><a class="toc-backref" href="#id16">execz</a><a class="headerlink" href="#execz" title="Permalink to this headline">¶</a></h3>
+<p>A single bit flag indicating that the <a class="reference internal" href="#amdgpu-synid-exec"><span class="std std-ref">exec</span></a> is all zeros.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">This operand is not currently supported by AMDGPU assembler.</p>
+</div>
+</div>
+<div class="section" id="scc">
+<span id="amdgpu-synid-scc"></span><h3><a class="toc-backref" href="#id17">scc</a><a class="headerlink" href="#scc" title="Permalink to this headline">¶</a></h3>
+<p>A single bit flag indicating the result of a scalar compare operation.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">This operand is not currently supported by AMDGPU assembler.</p>
+</div>
+</div>
+<div class="section" id="lds-direct">
+<h3><a class="toc-backref" href="#id18">lds_direct</a><a class="headerlink" href="#lds-direct" title="Permalink to this headline">¶</a></h3>
+<p>A special operand which supplies a 32-bit value
+fetched from <em>LDS</em> memory using <a class="reference internal" href="#amdgpu-synid-m0"><span class="std std-ref">m0</span></a> as an address.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">This operand is not currently supported by AMDGPU assembler.</p>
+</div>
+</div>
+<div class="section" id="constant">
+<span id="amdgpu-synid-constant"></span><h3><a class="toc-backref" href="#id19">constant</a><a class="headerlink" href="#constant" title="Permalink to this headline">¶</a></h3>
+<p>A set of integer and floating-point <em>inline constants</em>:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-synid-iconst"><span class="std std-ref">iconst</span></a></li>
+<li><a class="reference internal" href="#amdgpu-synid-fconst"><span class="std std-ref">fconst</span></a></li>
+</ul>
+<p>These operands are encoded as a part of instruction.</p>
+<p>If a number may be encoded as either
+a <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literal</span></a> or
+an <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constant</span></a>,
+assembler selects the latter encoding as more efficient.</p>
+</div>
+<div class="section" id="iconst">
+<span id="amdgpu-synid-iconst"></span><h3><a class="toc-backref" href="#id20">iconst</a><a class="headerlink" href="#iconst" title="Permalink to this headline">¶</a></h3>
+<p>An <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+encoded as an <em>inline constant</em>.</p>
+<p>Only a small fraction of integer numbers may be encoded as <em>inline constants</em>.
+They are enumerated in the table below.
+Other integer numbers have to be encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
+<p>Integer <em>inline constants</em> are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
+as described <a class="reference internal" href="#amdgpu-synid-int-const-conv"><span class="std std-ref">here</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="49%" />
+<col width="51%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Value</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>{0..64}</td>
+<td>Positive integer inline constants.</td>
+</tr>
+<tr class="row-odd"><td>{-16..-1}</td>
+<td>Negative integer inline constants.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">GFX7 does not support inline constants for <em>f16</em> operands.</p>
+</div>
+<p>There are also symbolic inline constants which provide read-only access to H/W registers.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">These inline constants are not currently supported by AMDGPU assembler.</p>
+</div>
+<p></p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="28%" />
+<col width="56%" />
+<col width="15%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Note</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>shared_base</td>
+<td>Base address of shared memory region.</td>
+<td>GFX9</td>
+</tr>
+<tr class="row-odd"><td>shared_limit</td>
+<td>Address of the end of shared memory region.</td>
+<td>GFX9</td>
+</tr>
+<tr class="row-even"><td>private_base</td>
+<td>Base address of private memory region.</td>
+<td>GFX9</td>
+</tr>
+<tr class="row-odd"><td>private_limit</td>
+<td>Address of the end of private memory region.</td>
+<td>GFX9</td>
+</tr>
+<tr class="row-even"><td>pops_exiting_wave_id</td>
+<td>A dedicated counter for POPS.</td>
+<td>GFX9</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="fconst">
+<span id="amdgpu-synid-fconst"></span><h3><a class="toc-backref" href="#id21">fconst</a><a class="headerlink" href="#fconst" title="Permalink to this headline">¶</a></h3>
+<p>A <a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point number</span></a>
+encoded as an <em>inline constant</em>.</p>
+<p>Only a small fraction of floating-point numbers may be encoded as <em>inline constants</em>.
+They are enumerated in the table below.
+Other floating-point numbers have to be encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
+<p>Floating-point <em>inline constants</em> are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
+as described <a class="reference internal" href="#amdgpu-synid-fp-const-conv"><span class="std std-ref">here</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="32%" />
+<col width="50%" />
+<col width="17%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Value</th>
+<th class="head">Note</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0.0</td>
+<td>The same as integer constant 0.</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>0.5</td>
+<td>Floating-point constant 0.5</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>1.0</td>
+<td>Floating-point constant 1.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>2.0</td>
+<td>Floating-point constant 2.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>4.0</td>
+<td>Floating-point constant 4.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>-0.5</td>
+<td>Floating-point constant -0.5</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>-1.0</td>
+<td>Floating-point constant -1.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>-2.0</td>
+<td>Floating-point constant -2.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>-4.0</td>
+<td>Floating-point constant -4.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>0.1592</td>
+<td>1.0/(2.0*pi). Use only for 16-bit operands.</td>
+<td>GFX8, GFX9</td>
+</tr>
+<tr class="row-even"><td>0.15915494</td>
+<td>1.0/(2.0*pi). Use only for 16- and 32-bit operands.</td>
+<td>GFX8, GFX9</td>
+</tr>
+<tr class="row-odd"><td>0.159154943091895317852646485335</td>
+<td>1.0/(2.0*pi).</td>
+<td>GFX8, GFX9</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">GFX7 does not support inline constants for <em>f16</em> operands.</p>
+</div>
+</div>
+<div class="section" id="literal">
+<span id="amdgpu-synid-literal"></span><h3><a class="toc-backref" href="#id22">literal</a><a class="headerlink" href="#literal" title="Permalink to this headline">¶</a></h3>
+<p>A literal is a 64-bit value which is encoded as a separate 32-bit dword in the instruction stream.</p>
+<p>If a number may be encoded as either
+a <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literal</span></a> or
+an <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constant</span></a>,
+assembler selects the latter encoding as more efficient.</p>
+<p>Literals may be specified as <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>,
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a> or
+<a class="reference internal" href="#amdgpu-synid-expression"><span class="std std-ref">expressions</span></a>
+(expressions are currently supported for 32-bit operands only).</p>
+<p>A 64-bit literal value is converted by assembler
+to an <a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
+as described <a class="reference internal" href="#amdgpu-synid-lit-conv"><span class="std std-ref">here</span></a>.</p>
+<p>An instruction may use only one literal but several operands may refer the same literal.</p>
+</div>
+<div class="section" id="uimm8">
+<span id="amdgpu-synid-uimm8"></span><h3><a class="toc-backref" href="#id23">uimm8</a><a class="headerlink" href="#uimm8" title="Permalink to this headline">¶</a></h3>
+<p>A 8-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.
+The value is encoded as part of the opcode so it is free to use.</p>
+</div>
+<div class="section" id="uimm32">
+<span id="amdgpu-synid-uimm32"></span><h3><a class="toc-backref" href="#id24">uimm32</a><a class="headerlink" href="#uimm32" title="Permalink to this headline">¶</a></h3>
+<p>A 32-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.
+The value is stored as a separate 32-bit dword in the instruction stream.</p>
+</div>
+<div class="section" id="uimm20">
+<span id="amdgpu-synid-uimm20"></span><h3><a class="toc-backref" href="#id25">uimm20</a><a class="headerlink" href="#uimm20" title="Permalink to this headline">¶</a></h3>
+<p>A 20-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+</div>
+<div class="section" id="uimm21">
+<span id="amdgpu-synid-uimm21"></span><h3><a class="toc-backref" href="#id26">uimm21</a><a class="headerlink" href="#uimm21" title="Permalink to this headline">¶</a></h3>
+<p>A 21-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Assembler currently supports 20-bit offsets only. Use <a class="reference internal" href="#amdgpu-synid-uimm20"><span class="std std-ref">uimm20</span></a> as a replacement.</p>
+</div>
+</div>
+<div class="section" id="simm21">
+<span id="amdgpu-synid-simm21"></span><h3><a class="toc-backref" href="#id27">simm21</a><a class="headerlink" href="#simm21" title="Permalink to this headline">¶</a></h3>
+<p>A 21-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Assembler currently supports 20-bit unsigned offsets only .Use <a class="reference internal" href="#amdgpu-synid-uimm20"><span class="std std-ref">uimm20</span></a> as a replacement.</p>
+</div>
+</div>
+<div class="section" id="off">
+<span id="amdgpu-synid-off"></span><h3><a class="toc-backref" href="#id28">off</a><a class="headerlink" href="#off" title="Permalink to this headline">¶</a></h3>
+<p>A special entity which indicates that the value of this operand is not used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="40%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>off</td>
+<td>Indicates an unused operand.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="numbers">
+<span id="amdgpu-synid-number"></span><h2><a class="toc-backref" href="#id29">Numbers</a><a class="headerlink" href="#numbers" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="integer-numbers">
+<span id="amdgpu-synid-integer-number"></span><h3><a class="toc-backref" href="#id30">Integer Numbers</a><a class="headerlink" href="#integer-numbers" title="Permalink to this headline">¶</a></h3>
+<p>Integer numbers are 64 bits wide.
+They may be specified in binary, octal, hexadecimal and decimal formats:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="28%" />
+<col width="72%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Format</th>
+<th class="head">Syntax</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Decimal</td>
+<td>[-]?[1-9][0-9]*</td>
+</tr>
+<tr class="row-odd"><td>Binary</td>
+<td>[-]?0b[01]+</td>
+</tr>
+<tr class="row-even"><td>Octal</td>
+<td>[-]?0[0-7]+</td>
+</tr>
+<tr class="row-odd"><td>Hexadecimal</td>
+<td>[-]?0x[0-9a-fA-F]+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td>[-]?[0x]?[0-9][0-9a-fA-F]*[hH]</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">-</span><span class="mi">1234</span>
+<span class="mb">0b1010</span>
+<span class="mi">010</span>
+<span class="mh">0xff</span>
+<span class="mi">0</span><span class="n">ffh</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="floating-point-numbers">
+<span id="amdgpu-synid-floating-point-number"></span><h3><a class="toc-backref" href="#id31">Floating-Point Numbers</a><a class="headerlink" href="#floating-point-numbers" title="Permalink to this headline">¶</a></h3>
+<p>All floating-point numbers are handled as double (64 bits wide).</p>
+<p>Floating-point numbers may be specified in hexadecimal and decimal formats:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="11%" />
+<col width="44%" />
+<col width="44%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Format</th>
+<th class="head">Syntax</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Decimal</td>
+<td>[-]?[0-9]*[.][0-9]*([eE][+-]?[0-9]*)?</td>
+<td>Must include either a decimal separator or an exponent.</td>
+</tr>
+<tr class="row-odd"><td>Hexadecimal</td>
+<td>[-]0x[0-9a-fA-F]*(.[0-9a-fA-F]*)?[pP][+-]?[0-9a-fA-F]+</td>
+<td> </td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">-</span><span class="mf">1.234</span>
+<span class="mf">234e2</span>
+<span class="o">-</span><span class="mh">0x1af</span><span class="n">p</span><span class="o">-</span><span class="mi">10</span>
+<span class="mi">0</span><span class="n">x</span><span class="o">.</span><span class="mi">1</span><span class="n">afp10</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="expressions">
+<span id="amdgpu-synid-expression"></span><h2><a class="toc-backref" href="#id32">Expressions</a><a class="headerlink" href="#expressions" title="Permalink to this headline">¶</a></h2>
+<p>An expression specifies an address or a numeric value.
+There are two kinds of expressions:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">Absolute</span></a>.</li>
+<li><a class="reference internal" href="#amdgpu-synid-relocatable-expression"><span class="std std-ref">Relocatable</span></a>.</li>
+</ul>
+<div class="section" id="absolute-expressions">
+<span id="amdgpu-synid-absolute-expression"></span><h3><a class="toc-backref" href="#id33">Absolute Expressions</a><a class="headerlink" href="#absolute-expressions" title="Permalink to this headline">¶</a></h3>
+<p>The value of an absolute expression remains the same after program relocation.
+Absolute expressions must not include unassigned and relocatable values
+such as labels.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">x</span> <span class="o">=</span> <span class="o">-</span><span class="mi">1</span>
+<span class="n">y</span> <span class="o">=</span> <span class="n">x</span> <span class="o">+</span> <span class="mi">10</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="relocatable-expressions">
+<span id="amdgpu-synid-relocatable-expression"></span><h3><a class="toc-backref" href="#id34">Relocatable Expressions</a><a class="headerlink" href="#relocatable-expressions" title="Permalink to this headline">¶</a></h3>
+<p>The value of a relocatable expression depends on program relocation.</p>
+<p>Note that use of relocatable expressions is limited with branch targets
+and 32-bit <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
+<p>Addition information about relocation may be found <a class="reference internal" href="AMDGPUUsage.html#amdgpu-relocation-records"><span class="std std-ref">here</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">y</span> <span class="o">=</span> <span class="n">x</span> <span class="o">+</span> <span class="mi">10</span> <span class="o">//</span> <span class="n">x</span> <span class="ow">is</span> <span class="ow">not</span> <span class="n">yet</span> <span class="n">defined</span><span class="o">.</span> <span class="n">Undefined</span> <span class="n">symbols</span> <span class="n">are</span> <span class="n">assumed</span> <span class="n">to</span> <span class="n">be</span> <span class="n">PC</span><span class="o">-</span><span class="n">relative</span><span class="o">.</span>
+<span class="n">z</span> <span class="o">=</span> <span class="o">.</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="expression-data-type">
+<h3><a class="toc-backref" href="#id35">Expression Data Type</a><a class="headerlink" href="#expression-data-type" title="Permalink to this headline">¶</a></h3>
+<p>Expressions and operands of expressions are interpreted as 64-bit integers.</p>
+<p>Expressions may include 64-bit <a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a> (double).
+However these operands are also handled as 64-bit integers
+using binary representation of specified floating-point numbers.
+No conversion from floating-point to integer is performed.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>x = 0.1 // x is assigned an integer 4591870180066957722 which is a binary representation of 0.1.
+y = x + x // y is a sum of two integer values; it is not equal to 0.2!
+</pre></div>
+</div>
+</div>
+<div class="section" id="syntax">
+<h3><a class="toc-backref" href="#id36">Syntax</a><a class="headerlink" href="#syntax" title="Permalink to this headline">¶</a></h3>
+<p>Expressions are composed of
+<a class="reference internal" href="#amdgpu-synid-symbol"><span class="std std-ref">symbols</span></a>,
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>,
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>,
+<a class="reference internal" href="#amdgpu-synid-expression-bin-op"><span class="std std-ref">binary operators</span></a>,
+<a class="reference internal" href="#amdgpu-synid-expression-un-op"><span class="std std-ref">unary operators</span></a> and subexpressions.</p>
+<p>Expressions may also use â.â which is a reference to the current PC (program counter).</p>
+<p>The syntax of expressions is shown below:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">expr</span> <span class="p">::</span><span class="o">=</span> <span class="n">expr</span> <span class="n">binop</span> <span class="n">expr</span> <span class="o">|</span> <span class="n">primaryexpr</span> <span class="p">;</span>
+
+<span class="n">primaryexpr</span> <span class="p">::</span><span class="o">=</span> <span class="s1">'('</span> <span class="n">expr</span> <span class="s1">')'</span> <span class="o">|</span> <span class="n">symbol</span> <span class="o">|</span> <span class="n">number</span> <span class="o">|</span> <span class="s1">'.'</span> <span class="o">|</span> <span class="n">unop</span> <span class="n">primaryexpr</span> <span class="p">;</span>
+
+<span class="n">binop</span> <span class="p">::</span><span class="o">=</span> <span class="s1">'&&'</span>
+ <span class="o">|</span> <span class="s1">'||'</span>
+ <span class="o">|</span> <span class="s1">'|'</span>
+ <span class="o">|</span> <span class="s1">'^'</span>
+ <span class="o">|</span> <span class="s1">'&'</span>
+ <span class="o">|</span> <span class="s1">'!'</span>
+ <span class="o">|</span> <span class="s1">'=='</span>
+ <span class="o">|</span> <span class="s1">'!='</span>
+ <span class="o">|</span> <span class="s1">'<>'</span>
+ <span class="o">|</span> <span class="s1">'<'</span>
+ <span class="o">|</span> <span class="s1">'<='</span>
+ <span class="o">|</span> <span class="s1">'>'</span>
+ <span class="o">|</span> <span class="s1">'>='</span>
+ <span class="o">|</span> <span class="s1">'<<'</span>
+ <span class="o">|</span> <span class="s1">'>>'</span>
+ <span class="o">|</span> <span class="s1">'+'</span>
+ <span class="o">|</span> <span class="s1">'-'</span>
+ <span class="o">|</span> <span class="s1">'*'</span>
+ <span class="o">|</span> <span class="s1">'/'</span>
+ <span class="o">|</span> <span class="s1">'%'</span> <span class="p">;</span>
+
+<span class="n">unop</span> <span class="p">::</span><span class="o">=</span> <span class="s1">'~'</span>
+ <span class="o">|</span> <span class="s1">'+'</span>
+ <span class="o">|</span> <span class="s1">'-'</span>
+ <span class="o">|</span> <span class="s1">'!'</span> <span class="p">;</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="binary-operators">
+<span id="amdgpu-synid-expression-bin-op"></span><h3><a class="toc-backref" href="#id37">Binary Operators</a><a class="headerlink" href="#binary-operators" title="Permalink to this headline">¶</a></h3>
+<p>Binary operators are described in the following table.
+They operate on and produce 64-bit integers.
+Operators with higher priority are performed first.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="15%" />
+<col width="14%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Operator</th>
+<th class="head">Priority</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>*</td>
+<td>5</td>
+<td>Integer multiplication.</td>
+</tr>
+<tr class="row-odd"><td>/</td>
+<td>5</td>
+<td>Integer division.</td>
+</tr>
+<tr class="row-even"><td>%</td>
+<td>5</td>
+<td>Integer signed remainder.</td>
+</tr>
+<tr class="row-odd"><td>+</td>
+<td>4</td>
+<td>Integer addition.</td>
+</tr>
+<tr class="row-even"><td>-</td>
+<td>4</td>
+<td>Integer subtraction.</td>
+</tr>
+<tr class="row-odd"><td><<</td>
+<td>3</td>
+<td>Integer shift left.</td>
+</tr>
+<tr class="row-even"><td>>></td>
+<td>3</td>
+<td>Logical shift right.</td>
+</tr>
+<tr class="row-odd"><td>==</td>
+<td>2</td>
+<td>Equality comparison.</td>
+</tr>
+<tr class="row-even"><td>!=</td>
+<td>2</td>
+<td>Inequality comparison.</td>
+</tr>
+<tr class="row-odd"><td><></td>
+<td>2</td>
+<td>Inequality comparison.</td>
+</tr>
+<tr class="row-even"><td><</td>
+<td>2</td>
+<td>Signed less than comparison.</td>
+</tr>
+<tr class="row-odd"><td><=</td>
+<td>2</td>
+<td>Signed less than or equal comparison.</td>
+</tr>
+<tr class="row-even"><td>></td>
+<td>2</td>
+<td>Signed greater than comparison.</td>
+</tr>
+<tr class="row-odd"><td>>=</td>
+<td>2</td>
+<td>Signed greater than or equal comparison.</td>
+</tr>
+<tr class="row-even"><td>|</td>
+<td>1</td>
+<td>Bitwise or.</td>
+</tr>
+<tr class="row-odd"><td>^</td>
+<td>1</td>
+<td>Bitwise xor.</td>
+</tr>
+<tr class="row-even"><td>&</td>
+<td>1</td>
+<td>Bitwise and.</td>
+</tr>
+<tr class="row-odd"><td>&&</td>
+<td>0</td>
+<td>Logical and.</td>
+</tr>
+<tr class="row-even"><td>||</td>
+<td>0</td>
+<td>Logical or.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="unary-operators">
+<span id="amdgpu-synid-expression-un-op"></span><h3><a class="toc-backref" href="#id38">Unary Operators</a><a class="headerlink" href="#unary-operators" title="Permalink to this headline">¶</a></h3>
+<p>Unary operators are described in the following table.
+They operate on and produce 64-bit integers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Operator</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>!</td>
+<td>Logical negation.</td>
+</tr>
+<tr class="row-odd"><td>~</td>
+<td>Bitwise negation.</td>
+</tr>
+<tr class="row-even"><td>+</td>
+<td>Integer unary plus.</td>
+</tr>
+<tr class="row-odd"><td>-</td>
+<td>Integer unary minus.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="symbols">
+<span id="amdgpu-synid-symbol"></span><h3><a class="toc-backref" href="#id39">Symbols</a><a class="headerlink" href="#symbols" title="Permalink to this headline">¶</a></h3>
+<p>A symbol is a named 64-bit value, representing a relocatable
+address or an absolute (non-relocatable) number.</p>
+<dl class="docutils">
+<dt>Symbol names have the following syntax:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">[a-zA-Z_.][a-zA-Z0-9_$.@]*</span></code></dd>
+</dl>
+<p>The table below provides several examples of syntax used for symbol definition.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="22%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>.globl <S></td>
+<td>Declares a global symbol S without assigning it a value.</td>
+</tr>
+<tr class="row-odd"><td>.set <S>, <E></td>
+<td>Assigns the value of an expression E to a symbol S.</td>
+</tr>
+<tr class="row-even"><td><S> = <E></td>
+<td>Assigns the value of an expression E to a symbol S.</td>
+</tr>
+<tr class="row-odd"><td><S>:</td>
+<td>Declares a label S and assigns it the current PC value.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>A symbol may be used before it is declared or assigned;
+unassigned symbols are assumed to be PC-relative.</p>
+<p>Addition information about symbols may be found <a class="reference internal" href="AMDGPUUsage.html#amdgpu-symbols"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+<div class="section" id="conversions">
+<span id="amdgpu-synid-conv"></span><h2><a class="toc-backref" href="#id40">Conversions</a><a class="headerlink" href="#conversions" title="Permalink to this headline">¶</a></h2>
+<p>This section describes what happens when a 64-bit
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>, a
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a> or a
+<a class="reference internal" href="#amdgpu-synid-symbol"><span class="std std-ref">symbol</span></a>
+is used for an operand which has a different type or size.</p>
+<p>Depending on operand kind, this conversion is performed by either assembler or AMDGPU H/W:</p>
+<ul class="simple">
+<li>Values encoded as <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constants</span></a> are handled by H/W.</li>
+<li>Values encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a> are converted by assembler.</li>
+</ul>
+<div class="section" id="inline-constants">
+<span id="amdgpu-synid-const-conv"></span><h3><a class="toc-backref" href="#id41">Inline Constants</a><a class="headerlink" href="#inline-constants" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="integer-inline-constants">
+<span id="amdgpu-synid-int-const-conv"></span><h4><a class="toc-backref" href="#id42">Integer Inline Constants</a><a class="headerlink" href="#integer-inline-constants" title="Permalink to this headline">¶</a></h4>
+<p>Integer <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constants</span></a>
+may be thought of as 64-bit
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>;
+when used as operands they are truncated to the size of
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>.
+No data type conversions are performed.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFF</span>
+<span class="n">v_add_f16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFF</span> <span class="p">(</span><span class="n">NaN</span><span class="p">)</span>
+
+<span class="n">v_add_u32</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFFFFFF</span>
+<span class="n">v_add_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFFFFFF</span> <span class="p">(</span><span class="n">NaN</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="floating-point-inline-constants">
+<span id="amdgpu-synid-fp-const-conv"></span><h4><a class="toc-backref" href="#id43">Floating-Point Inline Constants</a><a class="headerlink" href="#floating-point-inline-constants" title="Permalink to this headline">¶</a></h4>
+<p>Floating-point <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constants</span></a>
+may be thought of as 64-bit
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>;
+when used as operands they are converted to a floating-point number of
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand size</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_f16</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3C00</span> <span class="p">(</span><span class="mf">1.0</span><span class="p">)</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3C00</span>
+
+<span class="n">v_add_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3F800000</span> <span class="p">(</span><span class="mf">1.0</span><span class="p">)</span>
+<span class="n">v_add_u32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3F800000</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="literals">
+<span id="amdgpu-synid-lit-conv"></span><h3><a class="toc-backref" href="#id44">Literals</a><a class="headerlink" href="#literals" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="integer-literals">
+<span id="amdgpu-synid-int-lit-conv"></span><h4><a class="toc-backref" href="#id45">Integer Literals</a><a class="headerlink" href="#integer-literals" title="Permalink to this headline">¶</a></h4>
+<p>Integer <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>
+are specified as 64-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
+<p>When used as operands they are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a> as described below.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="13%" />
+<col width="13%" />
+<col width="14%" />
+<col width="61%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Expected type</th>
+<th class="head">Condition</th>
+<th class="head">Result</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>i16, u16, b16</td>
+<td>cond(num,16)</td>
+<td>num.u16</td>
+<td>Truncate to 16 bits.</td>
+</tr>
+<tr class="row-odd"><td>i32, u32, b32</td>
+<td>cond(num,32)</td>
+<td>num.u32</td>
+<td>Truncate to 32 bits.</td>
+</tr>
+<tr class="row-even"><td>i64</td>
+<td>cond(num,32)</td>
+<td>{-1,num.i32}</td>
+<td>Truncate to 32 bits and then sign-extend the result to 64 bits.</td>
+</tr>
+<tr class="row-odd"><td>u64, b64</td>
+<td>cond(num,32)</td>
+<td>{ 0,num.u32}</td>
+<td>Truncate to 32 bits and then zero-extend the result to 64 bits.</td>
+</tr>
+<tr class="row-even"><td>f16</td>
+<td>cond(num,16)</td>
+<td>num.u16</td>
+<td>Use low 16 bits as an f16 value.</td>
+</tr>
+<tr class="row-odd"><td>f32</td>
+<td>cond(num,32)</td>
+<td>num.u32</td>
+<td>Use low 32 bits as an f32 value.</td>
+</tr>
+<tr class="row-even"><td>f64</td>
+<td>cond(num,32)</td>
+<td>{num.u32,0}</td>
+<td>Use low 32 bits of the number as high 32 bits
+of the result; low 32 bits of the result are zeroed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The condition <em>cond(X,S)</em> indicates if a 64-bit number <em>X</em>
+can be converted to a smaller size <em>S</em> by truncation of upper bits.
+There are two cases when the conversion is possible:</p>
+<ul class="simple">
+<li>The truncated bits are all 0.</li>
+<li>The truncated bits are all 1 and the value after truncation has its MSB bit set.</li>
+</ul>
+<p>Examples of valid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+ <span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">after</span> <span class="n">conversion</span><span class="p">:</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="mh">0xff00</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xffffffffffffff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="mh">0xff00</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">256</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="mh">0xff00</span>
+ <span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">after</span> <span class="n">conversion</span><span class="p">:</span>
+<span class="n">s_bfe_i64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="mh">0xffffffffffefffff</span>
+<span class="n">s_bfe_u64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="mh">0x00000000ffefffff</span>
+<span class="n">v_ceil_f64_e32</span> <span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span> <span class="o">//</span> <span class="mh">0xffefffff00000000</span> <span class="p">(</span><span class="o">-</span><span class="mf">1.7976922776554302e308</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>Examples of invalid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0x1ff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">truncated</span> <span class="n">bits</span> <span class="n">are</span> <span class="ow">not</span> <span class="nb">all</span> <span class="mi">0</span> <span class="ow">or</span> <span class="mi">1</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xffffffffffff00ff</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">truncated</span> <span class="n">bits</span> <span class="n">do</span> <span class="ow">not</span> <span class="n">match</span> <span class="n">MSB</span> <span class="n">of</span> <span class="n">the</span> <span class="n">result</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="floating-point-literals">
+<span id="amdgpu-synid-fp-lit-conv"></span><h4><a class="toc-backref" href="#id46">Floating-Point Literals</a><a class="headerlink" href="#floating-point-literals" title="Permalink to this headline">¶</a></h4>
+<p>Floating-point <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a> are specified as 64-bit
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>.</p>
+<p>When used as operands they are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a> as described below.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="13%" />
+<col width="13%" />
+<col width="15%" />
+<col width="59%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Expected type</th>
+<th class="head">Condition</th>
+<th class="head">Result</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>i16, u16, b16</td>
+<td>cond(num,16)</td>
+<td>f16(num)</td>
+<td>Convert to f16 and use bits of the result as an integer value.</td>
+</tr>
+<tr class="row-odd"><td>i32, u32, b32</td>
+<td>cond(num,32)</td>
+<td>f32(num)</td>
+<td>Convert to f32 and use bits of the result as an integer value.</td>
+</tr>
+<tr class="row-even"><td>i64, u64, b64</td>
+<td>false</td>
+<td>-</td>
+<td>Conversion disabled because of an unclear semantics.</td>
+</tr>
+<tr class="row-odd"><td>f16</td>
+<td>cond(num,16)</td>
+<td>f16(num)</td>
+<td>Convert to f16.</td>
+</tr>
+<tr class="row-even"><td>f32</td>
+<td>cond(num,32)</td>
+<td>f32(num)</td>
+<td>Convert to f32.</td>
+</tr>
+<tr class="row-odd"><td>f64</td>
+<td>true</td>
+<td>{num.u32.hi,0}</td>
+<td><p class="first">Use high 32 bits of the number as high 32 bits of the result;
+zero-fill low 32 bits of the result.</p>
+<p class="last">Note that the result may differ from the original number.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The condition <em>cond(X,S)</em> indicates if an f64 number <em>X</em> can be converted
+to a smaller <em>S</em>-bit floating-point type without overflow or underflow.
+Precision lost is allowed.</p>
+<p>Examples of valid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_f16</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65500.0</span><span class="p">,</span> <span class="n">v2</span>
+<span class="n">v_add_f32</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65600.0</span><span class="p">,</span> <span class="n">v2</span>
+
+<span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">before</span> <span class="n">conversion</span><span class="p">:</span> <span class="mf">1.7976931348623157e308</span> <span class="p">(</span><span class="mh">0x7fefffffffffffff</span><span class="p">)</span>
+<span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">after</span> <span class="n">conversion</span><span class="p">:</span> <span class="mf">1.7976922776554302e308</span> <span class="p">(</span><span class="mh">0x7fefffff00000000</span><span class="p">)</span>
+<span class="n">v_ceil_f64</span> <span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mf">1.7976931348623157e308</span>
+</pre></div>
+</div>
+<p>Examples of invalid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_f16</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65600.0</span><span class="p">,</span> <span class="n">v2</span> <span class="o">//</span> <span class="n">overflow</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="amdgpu-synid-exp-conv">
+<span id="id1"></span><h4><a class="toc-backref" href="#id47">Expressions</a><a class="headerlink" href="#amdgpu-synid-exp-conv" title="Permalink to this headline">¶</a></h4>
+<p>Expressions operate with and result in 64-bit integers.</p>
+<p>When used as operands they are truncated to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand size</span></a>.
+No data type conversions are performed.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">x</span> <span class="o">=</span> <span class="mf">0.1</span>
+<span class="n">v_sqrt_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="n">x</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="p">[</span><span class="n">low</span> <span class="mi">32</span> <span class="n">bits</span> <span class="n">of</span> <span class="mf">0.1</span> <span class="p">(</span><span class="n">double</span><span class="p">)]</span>
+<span class="n">v_sqrt_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="p">(</span><span class="mf">0.1</span> <span class="o">+</span> <span class="mi">0</span><span class="p">)</span> <span class="o">//</span> <span class="n">the</span> <span class="n">same</span> <span class="k">as</span> <span class="n">above</span>
+<span class="n">v_sqrt_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">0.1</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="p">[</span><span class="mf">0.1</span> <span class="p">(</span><span class="n">double</span><span class="p">)</span> <span class="n">converted</span> <span class="n">to</span> <span class="nb">float</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+</div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
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+ >index</a></li>
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+
+ <div class="section" id="user-guide-for-amdgpu-backend">
+<h1>User Guide for AMDGPU Backend<a class="headerlink" href="#user-guide-for-amdgpu-backend" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id46">Introduction</a></li>
+<li><a class="reference internal" href="#llvm" id="id47">LLVM</a><ul>
+<li><a class="reference internal" href="#target-triples" id="id48">Target Triples</a></li>
+<li><a class="reference internal" href="#processors" id="id49">Processors</a></li>
+<li><a class="reference internal" href="#target-features" id="id50">Target Features</a></li>
+<li><a class="reference internal" href="#address-spaces" id="id51">Address Spaces</a></li>
+<li><a class="reference internal" href="#memory-scopes" id="id52">Memory Scopes</a></li>
+<li><a class="reference internal" href="#amdgpu-intrinsics" id="id53">AMDGPU Intrinsics</a></li>
+<li><a class="reference internal" href="#amdgpu-attributes" id="id54">AMDGPU Attributes</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object" id="id55">Code Object</a><ul>
+<li><a class="reference internal" href="#header" id="id56">Header</a></li>
+<li><a class="reference internal" href="#sections" id="id57">Sections</a></li>
+<li><a class="reference internal" href="#note-records" id="id58">Note Records</a><ul>
+<li><a class="reference internal" href="#code-object-v2-note-records-mattr-code-object-v3" id="id59">Code Object V2 Note Records (-mattr=-code-object-v3)</a></li>
+<li><a class="reference internal" href="#code-object-v3-note-records-mattr-code-object-v3" id="id60">Code Object V3 Note Records (-mattr=+code-object-v3)</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#symbols" id="id61">Symbols</a></li>
+<li><a class="reference internal" href="#relocation-records" id="id62">Relocation Records</a></li>
+<li><a class="reference internal" href="#dwarf" id="id63">DWARF</a><ul>
+<li><a class="reference internal" href="#address-space-mapping" id="id64">Address Space Mapping</a></li>
+<li><a class="reference internal" href="#register-mapping" id="id65">Register Mapping</a></li>
+<li><a class="reference internal" href="#source-text" id="id66">Source Text</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-conventions" id="id67">Code Conventions</a><ul>
+<li><a class="reference internal" href="#amdhsa" id="id68">AMDHSA</a><ul>
+<li><a class="reference internal" href="#code-object-target-identification" id="id69">Code Object Target Identification</a></li>
+<li><a class="reference internal" href="#code-object-metadata" id="id70">Code Object Metadata</a><ul>
+<li><a class="reference internal" href="#code-object-v2-metadata-mattr-code-object-v3" id="id71">Code Object V2 Metadata (-mattr=-code-object-v3)</a></li>
+<li><a class="reference internal" href="#code-object-v3-metadata-mattr-code-object-v3" id="id72">Code Object V3 Metadata (-mattr=+code-object-v3)</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#kernel-dispatch" id="id73">Kernel Dispatch</a></li>
+<li><a class="reference internal" href="#memory-spaces" id="id74">Memory Spaces</a></li>
+<li><a class="reference internal" href="#image-and-samplers" id="id75">Image and Samplers</a></li>
+<li><a class="reference internal" href="#hsa-signals" id="id76">HSA Signals</a></li>
+<li><a class="reference internal" href="#hsa-aql-queue" id="id77">HSA AQL Queue</a></li>
+<li><a class="reference internal" href="#kernel-descriptor" id="id78">Kernel Descriptor</a><ul>
+<li><a class="reference internal" href="#kernel-descriptor-for-gfx6-gfx9" id="id79">Kernel Descriptor for GFX6-GFX9</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#initial-kernel-execution-state" id="id80">Initial Kernel Execution State</a></li>
+<li><a class="reference internal" href="#kernel-prolog" id="id81">Kernel Prolog</a><ul>
+<li><a class="reference internal" href="#m0" id="id82">M0</a></li>
+<li><a class="reference internal" href="#flat-scratch" id="id83">Flat Scratch</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#memory-model" id="id84">Memory Model</a></li>
+<li><a class="reference internal" href="#trap-handler-abi" id="id85">Trap Handler ABI</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#amdpal" id="id86">AMDPAL</a><ul>
+<li><a class="reference internal" href="#user-data" id="id87">User Data</a></li>
+<li><a class="reference internal" href="#compute-user-data" id="id88">Compute User Data</a></li>
+<li><a class="reference internal" href="#graphics-user-data" id="id89">Graphics User Data</a></li>
+<li><a class="reference internal" href="#global-internal-table" id="id90">Global Internal Table</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#unspecified-os" id="id91">Unspecified OS</a><ul>
+<li><a class="reference internal" href="#id38" id="id92">Trap Handler ABI</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#source-languages" id="id93">Source Languages</a><ul>
+<li><a class="reference internal" href="#opencl" id="id94">OpenCL</a></li>
+<li><a class="reference internal" href="#hcc" id="id95">HCC</a></li>
+<li><a class="reference internal" href="#assembler" id="id96">Assembler</a><ul>
+<li><a class="reference internal" href="#instructions" id="id97">Instructions</a></li>
+<li><a class="reference internal" href="#operands" id="id98">Operands</a></li>
+<li><a class="reference internal" href="#modifiers" id="id99">Modifiers</a></li>
+<li><a class="reference internal" href="#instruction-examples" id="id100">Instruction Examples</a><ul>
+<li><a class="reference internal" href="#ds" id="id101">DS</a></li>
+<li><a class="reference internal" href="#flat" id="id102">FLAT</a></li>
+<li><a class="reference internal" href="#mubuf" id="id103">MUBUF</a></li>
+<li><a class="reference internal" href="#smrd-smem" id="id104">SMRD/SMEM</a></li>
+<li><a class="reference internal" href="#sop1" id="id105">SOP1</a></li>
+<li><a class="reference internal" href="#sop2" id="id106">SOP2</a></li>
+<li><a class="reference internal" href="#sopc" id="id107">SOPC</a></li>
+<li><a class="reference internal" href="#sopp" id="id108">SOPP</a></li>
+<li><a class="reference internal" href="#valu" id="id109">VALU</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#hsa-code-object-directives" id="id110">HSA Code Object Directives</a><ul>
+<li><a class="reference internal" href="#hsa-code-object-version-major-minor" id="id111">.hsa_code_object_version major, minor</a></li>
+<li><a class="reference internal" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" id="id112">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a></li>
+<li><a class="reference internal" href="#amdgpu-hsa-kernel-name" id="id113">.amdgpu_hsa_kernel (name)</a></li>
+<li><a class="reference internal" href="#amd-kernel-code-t" id="id114">.amd_kernel_code_t</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#predefined-symbols-mattr-code-object-v3" id="id115">Predefined Symbols (-mattr=+code-object-v3)</a><ul>
+<li><a class="reference internal" href="#amdgcn-gfx-generation-number" id="id116">.amdgcn.gfx_generation_number</a></li>
+<li><a class="reference internal" href="#amdgcn-next-free-vgpr" id="id117">.amdgcn.next_free_vgpr</a></li>
+<li><a class="reference internal" href="#amdgcn-next-free-sgpr" id="id118">.amdgcn.next_free_sgpr</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object-directives-mattr-code-object-v3" id="id119">Code Object Directives (-mattr=+code-object-v3)</a><ul>
+<li><a class="reference internal" href="#amdgcn-target-target" id="id120">.amdgcn_target <target></a></li>
+<li><a class="reference internal" href="#amdhsa-kernel-name" id="id121">.amdhsa_kernel <name></a></li>
+<li><a class="reference internal" href="#amdgpu-metadata" id="id122">.amdgpu_metadata</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#example-hsa-source-code-mattr-code-object-v3" id="id123">Example HSA Source Code (-mattr=+code-object-v3)</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#additional-documentation" id="id124">Additional Documentation</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id46">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the
+R600 family up until the current GCN families. It lives in the
+<code class="docutils literal notranslate"><span class="pre">lib/Target/AMDGPU</span></code> directory.</p>
+</div>
+<div class="section" id="llvm">
+<h2><a class="toc-backref" href="#id47">LLVM</a><a class="headerlink" href="#llvm" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="target-triples">
+<span id="amdgpu-target-triples"></span><h3><a class="toc-backref" href="#id48">Target Triples</a><a class="headerlink" href="#target-triples" title="Permalink to this headline">¶</a></h3>
+<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-target</span> <span class="pre"><Architecture>-<Vendor>-<OS>-<Environment></span></code> option to
+specify the target triple:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-architecture-table">
+<caption><span class="caption-text">AMDGPU Architectures</span><a class="headerlink" href="#amdgpu-architecture-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Architecture</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>AMD GPUs GCN GFX6 onwards for graphics and compute shaders.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-vendor-table">
+<caption><span class="caption-text">AMDGPU Vendors</span><a class="headerlink" href="#amdgpu-vendor-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Vendor</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">amd</span></code></td>
+<td>Can be used for all AMD GPU usage.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">mesa3d</span></code></td>
+<td>Can be used if the OS is <code class="docutils literal notranslate"><span class="pre">mesa3d</span></code>.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-os-table">
+<caption><span class="caption-text">AMDGPU Operating Systems</span><a class="headerlink" href="#amdgpu-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="19%" />
+<col width="81%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">OS</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em><empty></em></td>
+<td>Defaults to the <em>unknown</em> OS.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">amdhsa</span></code></td>
+<td>Compute kernels executed on HSA <a class="reference internal" href="#hsa" id="id1">[HSA]</a> compatible runtimes
+such as AMDâs ROCm <a class="reference internal" href="#amd-rocm" id="id2">[AMD-ROCm]</a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">amdpal</span></code></td>
+<td>Graphic shaders and compute kernels executed on AMD PAL
+runtime.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">mesa3d</span></code></td>
+<td>Graphic shaders and compute kernels executed on Mesa 3D
+runtime.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-environment-table">
+<caption><span class="caption-text">AMDGPU Environments</span><a class="headerlink" href="#amdgpu-environment-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Environment</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em><empty></em></td>
+<td>Default.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="processors">
+<span id="amdgpu-processors"></span><h3><a class="toc-backref" href="#id49">Processors</a><a class="headerlink" href="#processors" title="Permalink to this headline">¶</a></h3>
+<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-mcpu</span> <span class="pre"><Processor></span></code> option to specify the AMD GPU processor. The
+names from both the <em>Processor</em> and <em>Alternative Processor</em> can be used.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-processor-table">
+<caption><span class="caption-text">AMDGPU Processors</span><a class="headerlink" href="#amdgpu-processor-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="13%" />
+<col width="18%" />
+<col width="15%" />
+<col width="6%" />
+<col width="12%" />
+<col width="9%" />
+<col width="27%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Processor</th>
+<th class="head">Alternative
+Processor</th>
+<th class="head">Target
+Triple
+Architecture</th>
+<th class="head">dGPU/
+APU</th>
+<th class="head">Target
+Features
+Supported
+[Default]</th>
+<th class="head">ROCm
+Support</th>
+<th class="head">Example
+Products</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="7"><strong>Radeon HD 2000/3000 Series (R600)</strong> <a class="reference internal" href="#amd-radeon-hd-2000-3000" id="id3">[AMD-RADEON-HD-2000-3000]</a></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">r630</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">rs880</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv670</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 4000 Series (R700)</strong> <a class="reference internal" href="#amd-radeon-hd-4000" id="id4">[AMD-RADEON-HD-4000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv710</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">rv730</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv770</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 5000 Series (Evergreen)</strong> <a class="reference internal" href="#amd-radeon-hd-5000" id="id5">[AMD-RADEON-HD-5000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">cedar</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">cypress</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">juniper</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">redwood</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">sumo</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 6000 Series (Northern Islands)</strong> <a class="reference internal" href="#amd-radeon-hd-6000" id="id6">[AMD-RADEON-HD-6000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">barts</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">caicos</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">cayman</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">turks</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td colspan="7"><strong>GCN GFX6 (Southern Islands (SI))</strong> <a class="reference internal" href="#amd-gcn-gfx6" id="id7">[AMD-GCN-GFX6]</a></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx600</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">tahiti</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx601</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">hainan</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">oland</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">pitcairn</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">verde</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX7 (Sea Islands (CI))</strong> <a class="reference internal" href="#amd-gcn-gfx7" id="id8">[AMD-GCN-GFX7]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx700</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">kaveri</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A6-7000</li>
+<li>A6 Pro-7050B</li>
+<li>A8-7100</li>
+<li>A8 Pro-7150B</li>
+<li>A10-7300</li>
+<li>A10 Pro-7350B</li>
+<li>FX-7500</li>
+<li>A8-7200P</li>
+<li>A10-7400P</li>
+<li>FX-7600P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx701</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">hawaii</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>FirePro W8100</li>
+<li>FirePro W9100</li>
+<li>FirePro S9150</li>
+<li>FirePro S9170</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx702</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon R9 290</li>
+<li>Radeon R9 290x</li>
+<li>Radeon R390</li>
+<li>Radeon R390x</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx703</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">kabini</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">mullins</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>E1-2100</li>
+<li>E1-2200</li>
+<li>E1-2500</li>
+<li>E2-3000</li>
+<li>E2-3800</li>
+<li>A4-5000</li>
+<li>A4-5100</li>
+<li>A6-5200</li>
+<li>A4 Pro-3340B</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx704</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">bonaire</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>Radeon HD 7790</li>
+<li>Radeon HD 8770</li>
+<li>R7 260</li>
+<li>R7 260X</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX8 (Volcanic Islands (VI))</strong> <a class="reference internal" href="#amd-gcn-gfx8" id="id9">[AMD-GCN-GFX8]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx801</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">carrizo</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A6-8500P</li>
+<li>Pro A6-8500B</li>
+<li>A8-8600P</li>
+<li>Pro A8-8600B</li>
+<li>FX-8800P</li>
+<li>Pro A12-8800B</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>A10-8700P</li>
+<li>Pro A10-8700B</li>
+<li>A10-8780P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A10-9600P</li>
+<li>A10-9630P</li>
+<li>A12-9700P</li>
+<li>A12-9730P</li>
+<li>FX-9800P</li>
+<li>FX-9830P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>E2-9010</li>
+<li>A6-9210</li>
+<li>A9-9410</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx802</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">iceland</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">tonga</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>FirePro S7150</li>
+<li>FirePro S7100</li>
+<li>FirePro W7100</li>
+<li>Radeon R285</li>
+<li>Radeon R9 380</li>
+<li>Radeon R9 385</li>
+<li>Mobile FirePro
+M7170</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx803</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">fiji</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon R9 Nano</li>
+<li>Radeon R9 Fury</li>
+<li>Radeon R9 FuryX</li>
+<li>Radeon Pro Duo</li>
+<li>FirePro S9300x2</li>
+<li>Radeon Instinct MI8</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">polaris10</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon RX 470</li>
+<li>Radeon RX 480</li>
+<li>Radeon Instinct MI6</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">polaris11</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon RX 460</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx810</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">stoney</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX9</strong> <a class="reference internal" href="#amd-gcn-gfx9" id="id10">[AMD-GCN-GFX9]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx900</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon Vega
+Frontier Edition</li>
+<li>Radeon RX Vega 56</li>
+<li>Radeon RX Vega 64</li>
+<li>Radeon RX Vega 64
+Liquid</li>
+<li>Radeon Instinct MI25</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx902</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>Ryzen 3 2200G</li>
+<li>Ryzen 5 2400G</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx904</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx906</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]
+sram-ecc
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>Radeon Instinct MI50</li>
+<li>Radeon Instinct MI60</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx909</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em> (Raven Ridge 2)</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="target-features">
+<span id="amdgpu-target-features"></span><h3><a class="toc-backref" href="#id50">Target Features</a><a class="headerlink" href="#target-features" title="Permalink to this headline">¶</a></h3>
+<p>Target features control how code is generated to support certain
+processor specific features. Not all target features are supported by
+all processors. The runtime must ensure that the features supported by
+the device used to execute the code match the features enabled when
+generating the code. A mismatch of features may result in incorrect
+execution, or a reduction in performance.</p>
+<p>The target features supported by each processor, and the default value
+used if not specified explicitly, is listed in
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</p>
+<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-m[no-]<TargetFeature></span></code> option to specify the AMD GPU
+target features.</p>
+<p>For example:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">-mxnack</span></code></dt>
+<dd>Enable the <code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">-mno-xnack</span></code></dt>
+<dd><p class="first">Disable the <code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature.</p>
+<table border="1" class="last docutils" id="amdgpu-target-feature-table">
+<caption><span class="caption-text">AMDGPU Target Features</span><a class="headerlink" href="#amdgpu-target-feature-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="23%" />
+<col width="77%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Target Feature</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>-m[no-]xnack</td>
+<td><p class="first">Enable/disable generating code that has
+memory clauses that are compatible with
+having XNACK replay enabled.</p>
+<p class="last">This is used for demand paging and page
+migration. If XNACK replay is enabled in
+the device, then if a page fault occurs
+the code may execute incorrectly if the
+<code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature is not enabled. Executing
+code that has the feature enabled on a
+device that does not have XNACK replay
+enabled will execute correctly, but may
+be less performant than code with the
+feature disabled.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>-m[no-]sram-ecc</td>
+<td>Enable/disable generating code that assumes SRAM
+ECC is enabled/disabled.</td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+</div>
+<div class="section" id="address-spaces">
+<span id="amdgpu-address-spaces"></span><h3><a class="toc-backref" href="#id51">Address Spaces</a><a class="headerlink" href="#address-spaces" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend uses the following address space mappings.</p>
+<p>The memory space names used in the table, aside from the region memory space, is
+from the OpenCL standard.</p>
+<p>LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-address-space-mapping-table">
+<caption><span class="caption-text">Address Space Mapping</span><a class="headerlink" href="#amdgpu-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="51%" />
+<col width="49%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Address Space</th>
+<th class="head">Memory Space</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Generic (Flat)</td>
+</tr>
+<tr class="row-odd"><td>1</td>
+<td>Global</td>
+</tr>
+<tr class="row-even"><td>2</td>
+<td>Region (GDS)</td>
+</tr>
+<tr class="row-odd"><td>3</td>
+<td>Local (group/LDS)</td>
+</tr>
+<tr class="row-even"><td>4</td>
+<td>Constant</td>
+</tr>
+<tr class="row-odd"><td>5</td>
+<td>Private (Scratch)</td>
+</tr>
+<tr class="row-even"><td>6</td>
+<td>Constant 32-bit</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="memory-scopes">
+<span id="amdgpu-memory-scopes"></span><h3><a class="toc-backref" href="#id52">Memory Scopes</a><a class="headerlink" href="#memory-scopes" title="Permalink to this headline">¶</a></h3>
+<p>This section provides LLVM memory synchronization scopes supported by the AMDGPU
+backend memory model when the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a> and <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<p>The memory model supported is based on the HSA memory model <a class="reference internal" href="#hsa" id="id11">[HSA]</a> which is
+based in turn on HRF-indirect with scope inclusion <a class="reference internal" href="#hrf" id="id12">[HRF]</a>. The happens-before
+relation is transitive over the synchonizes-with relation independent of scope,
+and synchonizes-with allows the memory scope instances to be inclusive (see
+table <a class="reference internal" href="#amdgpu-amdhsa-llvm-sync-scopes-table"><span class="std std-ref">AMDHSA LLVM Sync Scopes</span></a>).</p>
+<p>This is different to the OpenCL <a class="reference internal" href="#id45" id="id13">[OpenCL]</a> memory model which does not have scope
+inclusion and requires the memory scopes to exactly match. However, this
+is conservatively correct for OpenCL.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-llvm-sync-scopes-table">
+<caption><span class="caption-text">AMDHSA LLVM Sync Scopes</span><a class="headerlink" href="#amdgpu-amdhsa-llvm-sync-scopes-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="22%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Sync Scope</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>none</em></td>
+<td><p class="first">The default: <code class="docutils literal notranslate"><span class="pre">system</span></code>.</p>
+<p>Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code>.</li>
+<li><code class="docutils literal notranslate"><span class="pre">agent</span></code> and executed by a thread on the same agent.</li>
+<li><code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a thread in the same
+workgroup.</li>
+<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the same
+wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">agent</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code> or <code class="docutils literal notranslate"><span class="pre">agent</span></code> and executed by a thread on the
+same agent.</li>
+<li><code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a thread in the same
+workgroup.</li>
+<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the same
+wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">workgroup</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code>, <code class="docutils literal notranslate"><span class="pre">agent</span></code> or <code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a
+thread in the same workgroup.</li>
+<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the same
+wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">wavefront</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code>, <code class="docutils literal notranslate"><span class="pre">agent</span></code>, <code class="docutils literal notranslate"><span class="pre">workgroup</span></code> or <code class="docutils literal notranslate"><span class="pre">wavefront</span></code>
+and executed by a thread in the same wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">singlethread</span></code></td>
+<td>Only synchronizes with, and participates in modification
+and seq_cst total orderings with, other operations (except
+image operations) running in the same thread for all
+address spaces (for example, in signal handlers).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-intrinsics">
+<h3><a class="toc-backref" href="#id53">AMDGPU Intrinsics</a><a class="headerlink" href="#amdgpu-intrinsics" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend implements the following LLVM IR intrinsics.</p>
+<p><em>This section is WIP.</em></p>
+</div>
+<div class="section" id="amdgpu-attributes">
+<h3><a class="toc-backref" href="#id54">AMDGPU Attributes</a><a class="headerlink" href="#amdgpu-attributes" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend supports the following LLVM IR attributes.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-llvm-ir-attributes-table">
+<caption><span class="caption-text">AMDGPU LLVM IR Attributes</span><a class="headerlink" href="#amdgpu-llvm-ir-attributes-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Attribute</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âamdgpu-flat-work-group-sizeâ=âmin,maxâ</td>
+<td>Specify the minimum and maximum flat work group sizes that
+will be specified when the kernel is dispatched. Generated
+by the <code class="docutils literal notranslate"><span class="pre">amdgpu_flat_work_group_size</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id14">[CLANG-ATTR]</a>.</td>
+</tr>
+<tr class="row-odd"><td>âamdgpu-implicitarg-num-bytesâ=ânâ</td>
+<td>Number of kernel argument bytes to add to the kernel
+argument block size for the implicit arguments. This
+varies by OS and language (for OpenCL see
+<a class="reference internal" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table"><span class="std std-ref">OpenCL kernel implicit arguments appended for AMDHSA OS</span></a>).</td>
+</tr>
+<tr class="row-even"><td>âamdgpu-max-work-group-sizeâ=ânâ</td>
+<td>Specify the maximum work-group size that will be specifed
+when the kernel is dispatched.</td>
+</tr>
+<tr class="row-odd"><td>âamdgpu-num-sgprâ=ânâ</td>
+<td>Specifies the number of SGPRs to use. Generated by
+the <code class="docutils literal notranslate"><span class="pre">amdgpu_num_sgpr</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id15">[CLANG-ATTR]</a>.</td>
+</tr>
+<tr class="row-even"><td>âamdgpu-num-vgprâ=ânâ</td>
+<td>Specifies the number of VGPRs to use. Generated by the
+<code class="docutils literal notranslate"><span class="pre">amdgpu_num_vgpr</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id16">[CLANG-ATTR]</a>.</td>
+</tr>
+<tr class="row-odd"><td>âamdgpu-waves-per-euâ=âm,nâ</td>
+<td>Specify the minimum and maximum number of waves per
+execution unit. Generated by the <code class="docutils literal notranslate"><span class="pre">amdgpu_waves_per_eu</span></code>
+CLANG attribute <a class="reference internal" href="#clang-attr" id="id17">[CLANG-ATTR]</a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="code-object">
+<h2><a class="toc-backref" href="#id55">Code Object</a><a class="headerlink" href="#code-object" title="Permalink to this headline">¶</a></h2>
+<p>The AMDGPU backend generates a standard ELF <a class="reference internal" href="#elf" id="id18">[ELF]</a> relocatable code object that
+can be linked by <code class="docutils literal notranslate"><span class="pre">lld</span></code> to produce a standard ELF shared code object which can
+be loaded and executed on an AMDGPU target.</p>
+<div class="section" id="header">
+<h3><a class="toc-backref" href="#id56">Header</a><a class="headerlink" href="#header" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend uses the following ELF header:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-header-table">
+<caption><span class="caption-text">AMDGPU ELF Header</span><a class="headerlink" href="#amdgpu-elf-header-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="38%" />
+<col width="62%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Field</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_CLASS]</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_DATA]</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">ELFDATA2LSB</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_OSABI]</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_ABIVERSION]</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_type</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ET_REL</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_machine</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_entry</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_flags</span></code></td>
+<td>See <a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-header-enumeration-values-table">
+<caption><span class="caption-text">AMDGPU ELF Header Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-header-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code></td>
+<td>224</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></td>
+<td>64</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></td>
+<td>65</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></td>
+<td>66</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></td>
+<td>1</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></td>
+<td>0</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_CLASS]</span></code></dt>
+<dd><p class="first">The ELF class is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFCLASS32</span></code> for <code class="docutils literal notranslate"><span class="pre">r600</span></code> architecture.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code> for <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architecture which only supports 64
+bit applications.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_DATA]</span></code></dt>
+<dd>All AMDGPU targets use <code class="docutils literal notranslate"><span class="pre">ELFDATA2LSB</span></code> for little-endian byte ordering.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_OSABI]</span></code></dt>
+<dd><p class="first">One of the following AMD GPU architecture specific OS ABIs
+(see <a class="reference internal" href="#amdgpu-os-table"><span class="std std-ref">AMDGPU Operating Systems</span></a>):</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code> for <em>unknown</em> OS.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code> for <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code> for <code class="docutils literal notranslate"><span class="pre">amdpal</span></code> OS.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code> for <code class="docutils literal notranslate"><span class="pre">mesa3D</span></code> OS.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_ABIVERSION]</span></code></dt>
+<dd><p class="first">The ABI version of the AMD GPU architecture specific OS ABI to which the code
+object conforms:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code> is used to specify the version of AMD HSA
+runtime ABI.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code> is used to specify the version of AMD PAL
+runtime ABI.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code> is used to specify the version of AMD MESA
+3D runtime ABI.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_type</span></code></dt>
+<dd><p class="first">Can be one of the following values:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">ET_REL</span></code></dt>
+<dd>The type produced by the AMD GPU backend compiler as it is relocatable code
+object.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code></dt>
+<dd>The type produced by the linker as it is a shared code object.</dd>
+</dl>
+<p class="last">The AMD HSA runtime loader requires a <code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code> code object.</p>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_machine</span></code></dt>
+<dd>The value <code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code> is used for the machine for all processors supported
+by the <code class="docutils literal notranslate"><span class="pre">r600</span></code> and <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architectures (see
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>). The specific processor is specified in the
+<code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code> bit field of the <code class="docutils literal notranslate"><span class="pre">e_flags</span></code> (see
+<a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a>).</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_entry</span></code></dt>
+<dd>The entry point is 0 as the entry points for individual kernels must be
+selected in order to invoke them through AQL packets.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_flags</span></code></dt>
+<dd><p class="first">The AMDGPU backend uses the following ELF header flags:</p>
+<table border="1" class="docutils" id="amdgpu-elf-header-e-flags-table">
+<caption><span class="caption-text">AMDGPU ELF Header <code class="docutils literal notranslate"><span class="pre">e_flags</span></code></span><a class="headerlink" href="#amdgpu-elf-header-e-flags-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="42%" />
+<col width="13%" />
+<col width="45%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="2"><strong>AMDGPU Processor Flag</strong></td>
+<td>See <a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code></td>
+<td>0x000000ff</td>
+<td>AMDGPU processor selection
+mask for
+<code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_xxx</span></code> values
+defined in
+<a class="reference internal" href="#amdgpu-ef-amdgpu-mach-table"><span class="std std-ref">AMDGPU EF_AMDGPU_MACH Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_XNACK</span></code></td>
+<td>0x00000100</td>
+<td>Indicates if the <code class="docutils literal notranslate"><span class="pre">xnack</span></code>
+target feature is
+enabled for all code
+contained in the code object.
+If the processor
+does not support the
+<code class="docutils literal notranslate"><span class="pre">xnack</span></code> target
+feature then must
+be 0.
+See
+<a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_SRAM_ECC</span></code></td>
+<td>0x00000200</td>
+<td>Indicates if the <code class="docutils literal notranslate"><span class="pre">sram-ecc</span></code>
+target feature is
+enabled for all code
+contained in the code object.
+If the processor
+does not support the
+<code class="docutils literal notranslate"><span class="pre">sram-ecc</span></code> target
+feature then must
+be 0.
+See
+<a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="last docutils" id="amdgpu-ef-amdgpu-mach-table">
+<caption><span class="caption-text">AMDGPU <code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code> Values</span><a class="headerlink" href="#amdgpu-ef-amdgpu-mach-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="45%" />
+<col width="14%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+<th class="head">Description (see
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>)</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_NONE</span></code></td>
+<td>0x000</td>
+<td><em>not specified</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_R600</span></code></td>
+<td>0x001</td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_R630</span></code></td>
+<td>0x002</td>
+<td><code class="docutils literal notranslate"><span class="pre">r630</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RS880</span></code></td>
+<td>0x003</td>
+<td><code class="docutils literal notranslate"><span class="pre">rs880</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV670</span></code></td>
+<td>0x004</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv670</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV710</span></code></td>
+<td>0x005</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv710</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV730</span></code></td>
+<td>0x006</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv730</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV770</span></code></td>
+<td>0x007</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv770</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CEDAR</span></code></td>
+<td>0x008</td>
+<td><code class="docutils literal notranslate"><span class="pre">cedar</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CYPRESS</span></code></td>
+<td>0x009</td>
+<td><code class="docutils literal notranslate"><span class="pre">cypress</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_JUNIPER</span></code></td>
+<td>0x00a</td>
+<td><code class="docutils literal notranslate"><span class="pre">juniper</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_REDWOOD</span></code></td>
+<td>0x00b</td>
+<td><code class="docutils literal notranslate"><span class="pre">redwood</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_SUMO</span></code></td>
+<td>0x00c</td>
+<td><code class="docutils literal notranslate"><span class="pre">sumo</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_BARTS</span></code></td>
+<td>0x00d</td>
+<td><code class="docutils literal notranslate"><span class="pre">barts</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CAICOS</span></code></td>
+<td>0x00e</td>
+<td><code class="docutils literal notranslate"><span class="pre">caicos</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CAYMAN</span></code></td>
+<td>0x00f</td>
+<td><code class="docutils literal notranslate"><span class="pre">cayman</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_TURKS</span></code></td>
+<td>0x010</td>
+<td><code class="docutils literal notranslate"><span class="pre">turks</span></code></td>
+</tr>
+<tr class="row-odd"><td><em>reserved</em></td>
+<td>0x011 -
+0x01f</td>
+<td>Reserved for <code class="docutils literal notranslate"><span class="pre">r600</span></code>
+architecture processors.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX600</span></code></td>
+<td>0x020</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx600</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX601</span></code></td>
+<td>0x021</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx601</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX700</span></code></td>
+<td>0x022</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx700</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX701</span></code></td>
+<td>0x023</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx701</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX702</span></code></td>
+<td>0x024</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx702</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX703</span></code></td>
+<td>0x025</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx703</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX704</span></code></td>
+<td>0x026</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx704</span></code></td>
+</tr>
+<tr class="row-odd"><td><em>reserved</em></td>
+<td>0x027</td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX801</span></code></td>
+<td>0x028</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx801</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX802</span></code></td>
+<td>0x029</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx802</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX803</span></code></td>
+<td>0x02a</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx803</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX810</span></code></td>
+<td>0x02b</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx810</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX900</span></code></td>
+<td>0x02c</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx900</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX902</span></code></td>
+<td>0x02d</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx902</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX904</span></code></td>
+<td>0x02e</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx904</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX906</span></code></td>
+<td>0x02f</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx906</span></code></td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td>0x030</td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX909</span></code></td>
+<td>0x031</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx909</span></code></td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+</div>
+<div class="section" id="sections">
+<h3><a class="toc-backref" href="#id57">Sections</a><a class="headerlink" href="#sections" title="Permalink to this headline">¶</a></h3>
+<p>An AMDGPU target ELF code object has the standard ELF sections which include:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-sections-table">
+<caption><span class="caption-text">AMDGPU ELF Sections</span><a class="headerlink" href="#amdgpu-elf-sections-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="27%" />
+<col width="24%" />
+<col width="49%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Attributes</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.bss</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_NOBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.data</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.debug_</span></code><em>*</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.dynamic</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_DYNAMIC</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.dynstr</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.dynsym</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.got</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.hash</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_HASH</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.note</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_NOTE</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_RELA</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_RELA</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.shstrtab</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_STRTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.strtab</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_STRTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.symtab</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_SYMTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.text</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_EXECINSTR</span></code></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>These sections have their standard meanings (see <a class="reference internal" href="#elf" id="id19">[ELF]</a>) and are only generated
+if needed.</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">.debug</span></code><em>*</em></dt>
+<dd>The standard DWARF sections. See <a class="reference internal" href="#amdgpu-dwarf"><span class="std std-ref">DWARF</span></a> for information on the
+DWARF produced by the AMDGPU backend.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.dynamic</span></code>, <code class="docutils literal notranslate"><span class="pre">.dynstr</span></code>, <code class="docutils literal notranslate"><span class="pre">.dynsym</span></code>, <code class="docutils literal notranslate"><span class="pre">.hash</span></code></dt>
+<dd>The standard sections used by a dynamic loader.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.note</span></code></dt>
+<dd>See <a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a> for the note records supported by the AMDGPU
+backend.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em>, <code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code></dt>
+<dd><p class="first">For relocatable code objects, <em>name</em> is the name of the section that the
+relocation records apply. For example, <code class="docutils literal notranslate"><span class="pre">.rela.text</span></code> is the section name for
+relocation records associated with the <code class="docutils literal notranslate"><span class="pre">.text</span></code> section.</p>
+<p>For linked shared code objects, <code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code> contains all the relocation
+records from each of the relocatable code objectâs <code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em> sections.</p>
+<p class="last">See <a class="reference internal" href="#amdgpu-relocation-records"><span class="std std-ref">Relocation Records</span></a> for the relocation records supported by
+the AMDGPU backend.</p>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.text</span></code></dt>
+<dd>The executable machine code for the kernels and functions they call. Generated
+as position independent code. See <a class="reference internal" href="#amdgpu-code-conventions"><span class="std std-ref">Code Conventions</span></a> for
+information on conventions used in the isa generation.</dd>
+</dl>
+</div>
+<div class="section" id="note-records">
+<span id="amdgpu-note-records"></span><h3><a class="toc-backref" href="#id58">Note Records</a><a class="headerlink" href="#note-records" title="Permalink to this headline">¶</a></h3>
+<p>As required by <code class="docutils literal notranslate"><span class="pre">ELFCLASS32</span></code> and <code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code>, minimal zero byte padding must
+be generated after the <code class="docutils literal notranslate"><span class="pre">name</span></code> field to ensure the <code class="docutils literal notranslate"><span class="pre">desc</span></code> field is 4 byte
+aligned. In addition, minimal zero byte padding must be generated to ensure the
+<code class="docutils literal notranslate"><span class="pre">desc</span></code> field size is a multiple of 4 bytes. The <code class="docutils literal notranslate"><span class="pre">sh_addralign</span></code> field of the
+<code class="docutils literal notranslate"><span class="pre">.note</span></code> section must be at least 4 to indicate at least 8 byte alignment.</p>
+<div class="section" id="code-object-v2-note-records-mattr-code-object-v3">
+<span id="amdgpu-note-records-v2"></span><h4><a class="toc-backref" href="#id59">Code Object V2 Note Records (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-note-records-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>The AMDGPU backend code object uses the following ELF note record in the
+<code class="docutils literal notranslate"><span class="pre">.note</span></code> section.</p>
+<p>Additional note records can be present.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-records-table-v2">
+<caption><span class="caption-text">AMDGPU Code Object V2 ELF Note Records</span><a class="headerlink" href="#amdgpu-elf-note-records-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="7%" />
+<col width="41%" />
+<col width="52%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âAMDâ</td>
+<td><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
+<td><metadata null terminated string></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-record-enumeration-values-table-v2">
+<caption><span class="caption-text">AMDGPU Code Object V2 ELF Note Record Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-note-record-enumeration-values-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>reserved</em></td>
+<td>0-9</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
+<td>10</td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td>11</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></dt>
+<dd>Specifies extensible metadata associated with the code objects executed on HSA
+<a class="reference internal" href="#hsa" id="id20">[HSA]</a> compatible runtimes such as AMDâs ROCm <a class="reference internal" href="#amd-rocm" id="id21">[AMD-ROCm]</a>. It is required when
+the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v2"><span class="std std-ref">Code Object V2 Metadata (-mattr=-code-object-v3)</span></a> for the syntax of the code
+object metadata string.</dd>
+</dl>
+</div>
+<div class="section" id="code-object-v3-note-records-mattr-code-object-v3">
+<span id="amdgpu-note-records-v3"></span><h4><a class="toc-backref" href="#id60">Code Object V3 Note Records (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-note-records-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>The AMDGPU backend code object uses the following ELF note record in the
+<code class="docutils literal notranslate"><span class="pre">.note</span></code> section.</p>
+<p>Additional note records can be present.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-records-table-v3">
+<caption><span class="caption-text">AMDGPU Code Object V3 ELF Note Records</span><a class="headerlink" href="#amdgpu-elf-note-records-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="11%" />
+<col width="39%" />
+<col width="50%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âAMDGPUâ</td>
+<td><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></td>
+<td>Metadata in Message Pack <a class="reference internal" href="#msgpack" id="id22">[MsgPack]</a>
+binary format.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-record-enumeration-values-table-v3">
+<caption><span class="caption-text">AMDGPU Code Object V3 ELF Note Record Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-note-record-enumeration-values-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>reserved</em></td>
+<td>0-31</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></td>
+<td>32</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></dt>
+<dd>Specifies extensible metadata associated with an AMDGPU code
+object. It is encoded as a map in the Message Pack <a class="reference internal" href="#msgpack" id="id23">[MsgPack]</a> binary
+data format. See <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a> for the
+map keys defined for the <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="symbols">
+<span id="amdgpu-symbols"></span><h3><a class="toc-backref" href="#id61">Symbols</a><a class="headerlink" href="#symbols" title="Permalink to this headline">¶</a></h3>
+<p>Symbols include the following:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-symbols-table">
+<caption><span class="caption-text">AMDGPU ELF Symbols</span><a class="headerlink" href="#amdgpu-elf-symbols-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="32%" />
+<col width="21%" />
+<col width="20%" />
+<col width="27%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Section</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>link-name</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">STT_OBJECT</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">.data</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">.bss</span></code></li>
+</ul>
+</td>
+<td>Global variable</td>
+</tr>
+<tr class="row-odd"><td><em>link-name</em><code class="docutils literal notranslate"><span class="pre">.kd</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">STT_OBJECT</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></li>
+</ul>
+</td>
+<td>Kernel descriptor</td>
+</tr>
+<tr class="row-even"><td><em>link-name</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">STT_FUNC</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">.text</span></code></li>
+</ul>
+</td>
+<td>Kernel entry point</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt>Global variable</dt>
+<dd><p class="first">Global variables both used and defined by the compilation unit.</p>
+<p>If the symbol is defined in the compilation unit then it is allocated in the
+appropriate section according to if it has initialized data or is readonly.</p>
+<p>If the symbol is external then its section is <code class="docutils literal notranslate"><span class="pre">STN_UNDEF</span></code> and the loader
+will resolve relocations using the definition provided by another code object
+or explicitly defined by the runtime.</p>
+<p class="last">All global symbols, whether defined in the compilation unit or external, are
+accessed by the machine code indirectly through a GOT table entry. This
+allows them to be preemptable. The GOT table is only supported when the target
+triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+</dd>
+<dt>Kernel descriptor</dt>
+<dd>Every HSA kernel has an associated kernel descriptor. It is the address of the
+kernel descriptor that is used in the AQL dispatch packet used to invoke the
+kernel, not the kernel entry point. The layout of the HSA kernel descriptor is
+defined in <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>.</dd>
+<dt>Kernel entry point</dt>
+<dd>Every HSA kernel also has a symbol for its machine code entry point.</dd>
+</dl>
+</div>
+<div class="section" id="relocation-records">
+<span id="amdgpu-relocation-records"></span><h3><a class="toc-backref" href="#id62">Relocation Records</a><a class="headerlink" href="#relocation-records" title="Permalink to this headline">¶</a></h3>
+<p>AMDGPU backend generates <code class="docutils literal notranslate"><span class="pre">Elf64_Rela</span></code> relocation records. Supported
+relocatable fields are:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">word32</span></code></dt>
+<dd>This specifies a 32-bit field occupying 4 bytes with arbitrary byte
+alignment. These values use the same byte order as other word values in the
+AMD GPU architecture.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">word64</span></code></dt>
+<dd>This specifies a 64-bit field occupying 8 bytes with arbitrary byte
+alignment. These values use the same byte order as other word values in the
+AMD GPU architecture.</dd>
+</dl>
+<p>Following notations are used for specifying relocation calculations:</p>
+<dl class="docutils">
+<dt><strong>A</strong></dt>
+<dd>Represents the addend used to compute the value of the relocatable field.</dd>
+<dt><strong>G</strong></dt>
+<dd>Represents the offset into the global offset table at which the relocation
+entryâs symbol will reside during execution.</dd>
+<dt><strong>GOT</strong></dt>
+<dd>Represents the address of the global offset table.</dd>
+<dt><strong>P</strong></dt>
+<dd>Represents the place (section offset for <code class="docutils literal notranslate"><span class="pre">et_rel</span></code> or address for <code class="docutils literal notranslate"><span class="pre">et_dyn</span></code>)
+of the storage unit being relocated (computed using <code class="docutils literal notranslate"><span class="pre">r_offset</span></code>).</dd>
+<dt><strong>S</strong></dt>
+<dd>Represents the value of the symbol whose index resides in the relocation
+entry. Relocations not using this must specify a symbol index of <code class="docutils literal notranslate"><span class="pre">STN_UNDEF</span></code>.</dd>
+<dt><strong>B</strong></dt>
+<dd>Represents the base address of a loaded executable or shared object which is
+the difference between the ELF address and the actual load address. Relocations
+using this are only valid in executable or shared objects.</dd>
+</dl>
+<p>The following relocation types are supported:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-relocation-records-table">
+<caption><span class="caption-text">AMDGPU ELF Relocation Records</span><a class="headerlink" href="#amdgpu-elf-relocation-records-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="33%" />
+<col width="9%" />
+<col width="6%" />
+<col width="13%" />
+<col width="38%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Relocation Type</th>
+<th class="head">Kind</th>
+<th class="head">Value</th>
+<th class="head">Field</th>
+<th class="head">Calculation</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_NONE</span></code></td>
+<td> </td>
+<td>0</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_LO</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>1</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_HI</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>2</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A) >> 32</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS64</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>3</td>
+<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
+<td>S + A</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32</span></code></td>
+<td>Static</td>
+<td>4</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>S + A - P</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL64</span></code></td>
+<td>Static</td>
+<td>5</td>
+<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
+<td>S + A - P</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>6</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>S + A</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL</span></code></td>
+<td>Static</td>
+<td>7</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>G + GOT + A - P</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL32_LO</span></code></td>
+<td>Static</td>
+<td>8</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(G + GOT + A - P) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL32_HI</span></code></td>
+<td>Static</td>
+<td>9</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(G + GOT + A - P) >> 32</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32_LO</span></code></td>
+<td>Static</td>
+<td>10</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A - P) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32_HI</span></code></td>
+<td>Static</td>
+<td>11</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A - P) >> 32</td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td> </td>
+<td>12</td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_RELATIVE64</span></code></td>
+<td>Dynamic</td>
+<td>13</td>
+<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
+<td>B + A</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_LO</span></code> and <code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_HI</span></code> are only supported by
+the <code class="docutils literal notranslate"><span class="pre">mesa3d</span></code> OS, which does not support <code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS64</span></code>.</p>
+<p>There is no current OS loader support for 32 bit programs and so
+<code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32</span></code> is not used.</p>
+</div>
+<div class="section" id="dwarf">
+<span id="amdgpu-dwarf"></span><h3><a class="toc-backref" href="#id63">DWARF</a><a class="headerlink" href="#dwarf" title="Permalink to this headline">¶</a></h3>
+<p>Standard DWARF <a class="reference internal" href="#id44" id="id24">[DWARF]</a> Version 5 sections can be generated. These contain
+information that maps the code object executable code and data to the source
+language constructs. It can be used by tools such as debuggers and profilers.</p>
+<div class="section" id="address-space-mapping">
+<h4><a class="toc-backref" href="#id64">Address Space Mapping</a><a class="headerlink" href="#address-space-mapping" title="Permalink to this headline">¶</a></h4>
+<p>The following address space mapping is used:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-dwarf-address-space-mapping-table">
+<caption><span class="caption-text">AMDGPU DWARF Address Space Mapping</span><a class="headerlink" href="#amdgpu-dwarf-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="53%" />
+<col width="47%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">DWARF Address Space</th>
+<th class="head">Memory Space</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>1</td>
+<td>Private (Scratch)</td>
+</tr>
+<tr class="row-odd"><td>2</td>
+<td>Local (group/LDS)</td>
+</tr>
+<tr class="row-even"><td><em>omitted</em></td>
+<td>Global</td>
+</tr>
+<tr class="row-odd"><td><em>omitted</em></td>
+<td>Constant</td>
+</tr>
+<tr class="row-even"><td><em>omitted</em></td>
+<td>Generic (Flat)</td>
+</tr>
+<tr class="row-odd"><td><em>not supported</em></td>
+<td>Region (GDS)</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>See <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a> for information on the memory space terminology
+used in the table.</p>
+<p>An <code class="docutils literal notranslate"><span class="pre">address_class</span></code> attribute is generated on pointer type DIEs to specify the
+DWARF address space of the value of the pointer when it is in the <em>private</em> or
+<em>local</em> address space. Otherwise the attribute is omitted.</p>
+<p>An <code class="docutils literal notranslate"><span class="pre">XDEREF</span></code> operation is generated in location list expressions for variables
+that are allocated in the <em>private</em> and <em>local</em> address space. Otherwise no
+<code class="docutils literal notranslate"><span class="pre">XDREF</span></code> is omitted.</p>
+</div>
+<div class="section" id="register-mapping">
+<h4><a class="toc-backref" href="#id65">Register Mapping</a><a class="headerlink" href="#register-mapping" title="Permalink to this headline">¶</a></h4>
+<p><em>This section is WIP.</em></p>
+</div>
+<div class="section" id="source-text">
+<h4><a class="toc-backref" href="#id66">Source Text</a><a class="headerlink" href="#source-text" title="Permalink to this headline">¶</a></h4>
+<p>Source text for online-compiled programs (e.g. those compiled by the OpenCL
+runtime) may be embedded into the DWARF v5 line table using the <code class="docutils literal notranslate"><span class="pre">clang</span>
+<span class="pre">-gembed-source</span></code> option, described in table <a class="reference internal" href="#amdgpu-debug-options"><span class="std std-ref">AMDGPU Debug Options</span></a>.</p>
+<p>For example:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">-gembed-source</span></code></dt>
+<dd>Enable the embedded source DWARF v5 extension.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">-gno-embed-source</span></code></dt>
+<dd><p class="first">Disable the embedded source DWARF v5 extension.</p>
+<table border="1" class="last docutils" id="amdgpu-debug-options">
+<caption><span class="caption-text">AMDGPU Debug Options</span><a class="headerlink" href="#amdgpu-debug-options" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="29%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Debug Flag</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>-g[no-]embed-source</td>
+<td>Enable/disable embedding source text in DWARF
+debug sections. Useful for environments where
+source cannot be written to disk, such as
+when performing online compilation.</td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+<p>This option enables one extended content types in the DWARF v5 Line Number
+Program Header, which is used to encode embedded source.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-dwarf-extended-content-types">
+<caption><span class="caption-text">AMDGPU DWARF Line Number Program Header Extended Content Types</span><a class="headerlink" href="#amdgpu-dwarf-extended-content-types" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="56%" />
+<col width="44%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Content Type</th>
+<th class="head">Form</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">DW_LNCT_LLVM_source</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">DW_FORM_line_strp</span></code></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The source field will contain the UTF-8 encoded, null-terminated source text
+with <code class="docutils literal notranslate"><span class="pre">'\n'</span></code> line endings. When the source field is present, consumers can use
+the embedded source instead of attempting to discover the source on disk. When
+the source field is absent, consumers can access the file to get the source
+text.</p>
+<p>The above content type appears in the <code class="docutils literal notranslate"><span class="pre">file_name_entry_format</span></code> field of the
+line table prologue, and its corresponding value appear in the <code class="docutils literal notranslate"><span class="pre">file_names</span></code>
+field. The current encoding of the content type is documented in table
+<a class="reference internal" href="#amdgpu-dwarf-extended-content-types-encoding"><span class="std std-ref">AMDGPU DWARF Line Number Program Header Extended Content Types Encoding</span></a></p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-dwarf-extended-content-types-encoding">
+<caption><span class="caption-text">AMDGPU DWARF Line Number Program Header Extended Content Types Encoding</span><a class="headerlink" href="#amdgpu-dwarf-extended-content-types-encoding" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="58%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Content Type</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">DW_LNCT_LLVM_source</span></code></td>
+<td>0x2001</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+</div>
+<div class="section" id="code-conventions">
+<span id="amdgpu-code-conventions"></span><h2><a class="toc-backref" href="#id67">Code Conventions</a><a class="headerlink" href="#code-conventions" title="Permalink to this headline">¶</a></h2>
+<p>This section provides code conventions used for each supported target triple OS
+(see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="amdhsa">
+<h3><a class="toc-backref" href="#id68">AMDHSA</a><a class="headerlink" href="#amdhsa" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+<code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="code-object-target-identification">
+<span id="amdgpu-amdhsa-code-object-target-identification"></span><h4><a class="toc-backref" href="#id69">Code Object Target Identification</a><a class="headerlink" href="#code-object-target-identification" title="Permalink to this headline">¶</a></h4>
+<p>The AMDHSA OS uses the following syntax to specify the code object
+target as a single string:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><Architecture>-<Vendor>-<OS>-<Environment>-<Processor><Target</span> <span class="pre">Features></span></code></div></blockquote>
+<p>Where:</p>
+<blockquote>
+<div><ul class="simple">
+<li><code class="docutils literal notranslate"><span class="pre"><Architecture></span></code>, <code class="docutils literal notranslate"><span class="pre"><Vendor></span></code>, <code class="docutils literal notranslate"><span class="pre"><OS></span></code> and <code class="docutils literal notranslate"><span class="pre"><Environment></span></code>
+are the same as the <em>Target Triple</em> (see
+<a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</li>
+<li><code class="docutils literal notranslate"><span class="pre"><Processor></span></code> is the same as the <em>Processor</em> (see
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>).</li>
+<li><code class="docutils literal notranslate"><span class="pre"><Target</span> <span class="pre">Features></span></code> is a list of the enabled <em>Target Features</em>
+(see <a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>), each prefixed by a plus, that
+apply to <em>Processor</em>. The list must be in the same order as listed
+in the table <a class="reference internal" href="#amdgpu-target-feature-table"><span class="std std-ref">AMDGPU Target Features</span></a>. Note that <em>Target
+Features</em> must be included in the list if they are enabled even if
+that is the default for <em>Processor</em>.</li>
+</ul>
+</div></blockquote>
+<p>For example:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre">"amdgcn-amd-amdhsa--gfx902+xnack"</span></code></div></blockquote>
+</div>
+<div class="section" id="code-object-metadata">
+<span id="amdgpu-amdhsa-code-object-metadata"></span><h4><a class="toc-backref" href="#id70">Code Object Metadata</a><a class="headerlink" href="#code-object-metadata" title="Permalink to this headline">¶</a></h4>
+<p>The code object metadata specifies extensible metadata associated with the code
+objects executed on HSA <a class="reference internal" href="#hsa" id="id25">[HSA]</a> compatible runtimes such as AMDâs ROCm
+<a class="reference internal" href="#amd-rocm" id="id26">[AMD-ROCm]</a>. It is specified in a note record (see <a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a>)
+and is required when the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see
+<a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). It must contain the minimum information
+necessary to support the ROCM kernel queries. For example, the segment sizes
+needed in a dispatch packet. In addition, a high level language runtime may
+require other information to be included. For example, the AMD OpenCL runtime
+records kernel argument information.</p>
+<div class="section" id="code-object-v2-metadata-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-code-object-metadata-v2"></span><h5><a class="toc-backref" href="#id71">Code Object V2 Metadata (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-metadata-mattr-code-object-v3" title="Permalink to this headline">¶</a></h5>
+<p>Code object V2 metadata is specified by the <code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_METADATA</span></code> note
+record (see <a class="reference internal" href="#amdgpu-note-records-v2"><span class="std std-ref">Code Object V2 Note Records (-mattr=-code-object-v3)</span></a>).</p>
+<p>The metadata is specified as a YAML formatted string (see <a class="reference internal" href="#yaml" id="id27">[YAML]</a> and
+<a class="reference internal" href="YamlIO.html"><span class="doc">YAML I/O</span></a>).</p>
+<p>The metadata is represented as a single YAML document comprised of the mapping
+defined in table <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Metadata Map</span></a> and
+referenced tables.</p>
+<p>For boolean values, the string values of <code class="docutils literal notranslate"><span class="pre">false</span></code> and <code class="docutils literal notranslate"><span class="pre">true</span></code> are used for
+false and true respectively.</p>
+<p>Additional information can be added to the mappings. To avoid conflicts, any
+non-AMD key names should be prefixed by â<em>vendor-name</em>.â.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="11%" />
+<col width="15%" />
+<col width="10%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âVersionâ</td>
+<td>sequence of
+2 integers</td>
+<td>Required</td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version. Currently 1.</li>
+<li>The second integer is the minor
+version. Currently 0.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âPrintfâ</td>
+<td>sequence of
+strings</td>
+<td> </td>
+<td><p class="first">Each string is encoded information
+about a printf function call. The
+encoded information is organized as
+fields separated by colon (â:â):</p>
+<p><code class="docutils literal notranslate"><span class="pre">ID:N:S[0]:S[1]:...:S[N-1]:FormatString</span></code></p>
+<p>where:</p>
+<dl class="last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">ID</span></code></dt>
+<dd>A 32 bit integer as a unique id for
+each printf function call</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">N</span></code></dt>
+<dd>A 32 bit integer equal to the number
+of arguments of printf function call
+minus 1</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">S[i]</span></code> (where i = 0, 1, ⦠, N-1)</dt>
+<dd>32 bit integers for the size in bytes
+of the i-th FormatString argument of
+the printf function call</dd>
+<dt>FormatString</dt>
+<dd>The format string passed to the
+printf function call.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>âKernelsâ</td>
+<td>sequence of
+mapping</td>
+<td>Required</td>
+<td>Sequence of the mappings for each
+kernel in the code object. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Metadata Map</span></a>
+for the definition of the mapping.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="15%" />
+<col width="12%" />
+<col width="8%" />
+<col width="66%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âNameâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Source name of the kernel.</td>
+</tr>
+<tr class="row-odd"><td>âSymbolNameâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Name of the kernel
+descriptor ELF symbol.</td>
+</tr>
+<tr class="row-even"><td>âLanguageâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Source language of the kernel.
+Values include:</p>
+<ul class="last simple">
+<li>âOpenCL Câ</li>
+<li>âOpenCL C++â</li>
+<li>âHCCâ</li>
+<li>âOpenMPâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âLanguageVersionâ</td>
+<td>sequence of
+2 integers</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version.</li>
+<li>The second integer is the
+minor version.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âAttrsâ</td>
+<td>mapping</td>
+<td> </td>
+<td>Mapping of kernel attributes.
+See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Attribute Metadata Map</span></a>
+for the mapping definition.</td>
+</tr>
+<tr class="row-odd"><td>âArgsâ</td>
+<td>sequence of
+mapping</td>
+<td> </td>
+<td>Sequence of mappings of the
+kernel arguments. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Argument Metadata Map</span></a>
+for the definition of the mapping.</td>
+</tr>
+<tr class="row-even"><td>âCodePropsâ</td>
+<td>mapping</td>
+<td> </td>
+<td>Mapping of properties related to
+the kernel code. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Code Properties Metadata Map</span></a>
+for the mapping definition.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Attribute Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="19%" />
+<col width="13%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âReqdWorkGroupSizeâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">If not 0, 0, 0 then all values
+must be >=1 and the dispatch
+work-group size X, Y, Z must
+correspond to the specified
+values. Defaults to 0, 0, 0.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">reqd_work_group_size</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>âWorkGroupSizeHintâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">The dispatch work-group size
+X, Y, Z is likely to be the
+specified values.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">work_group_size_hint</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-even"><td>âVecTypeHintâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The name of a scalar or vector
+type.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">vec_type_hint</span></code> attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>âRuntimeHandleâ</td>
+<td>string</td>
+<td> </td>
+<td>The external symbol name
+associated with a kernel.
+OpenCL runtime allocates a
+global buffer for the symbol
+and saves the kernelâs address
+to it, which is used for
+device side enqueueing. Only
+available for device side
+enqueued kernels.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Argument Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="22%" />
+<col width="18%" />
+<col width="12%" />
+<col width="49%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âNameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument name.</td>
+</tr>
+<tr class="row-odd"><td>âTypeNameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument type name.</td>
+</tr>
+<tr class="row-even"><td>âSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument size in bytes.</td>
+</tr>
+<tr class="row-odd"><td>âAlignâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument alignment in
+bytes. Must be a power of two.</td>
+</tr>
+<tr class="row-even"><td>âValueKindâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument kind that
+specifies how to set up the
+corresponding argument.
+Values include:</p>
+<dl class="last docutils">
+<dt>âByValueâ</dt>
+<dd>The argument is copied
+directly into the kernarg.</dd>
+<dt>âGlobalBufferâ</dt>
+<dd>A global address space pointer
+to the buffer data is passed
+in the kernarg.</dd>
+<dt>âDynamicSharedPointerâ</dt>
+<dd>A group address space pointer
+to dynamically allocated LDS
+is passed in the kernarg.</dd>
+<dt>âSamplerâ</dt>
+<dd>A global address space
+pointer to a S# is passed in
+the kernarg.</dd>
+<dt>âImageâ</dt>
+<dd>A global address space
+pointer to a T# is passed in
+the kernarg.</dd>
+<dt>âPipeâ</dt>
+<dd>A global address space pointer
+to an OpenCL pipe is passed in
+the kernarg.</dd>
+<dt>âQueueâ</dt>
+<dd>A global address space pointer
+to an OpenCL device enqueue
+queue is passed in the
+kernarg.</dd>
+<dt>âHiddenGlobalOffsetXâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the X
+dimension is passed in the
+kernarg.</dd>
+<dt>âHiddenGlobalOffsetYâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Y
+dimension is passed in the
+kernarg.</dd>
+<dt>âHiddenGlobalOffsetZâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Z
+dimension is passed in the
+kernarg.</dd>
+<dt>âHiddenNoneâ</dt>
+<dd>An argument that is not used
+by the kernel. Space needs to
+be left for it, but it does
+not need to be set up.</dd>
+<dt>âHiddenPrintfBufferâ</dt>
+<dd>A global address space pointer
+to the runtime printf buffer
+is passed in kernarg.</dd>
+<dt>âHiddenDefaultQueueâ</dt>
+<dd>A global address space pointer
+to the OpenCL device enqueue
+queue that should be used by
+the kernel by default is
+passed in the kernarg.</dd>
+<dt>âHiddenCompletionActionâ</dt>
+<dd>A global address space pointer
+to help link enqueued kernels into
+the ancestor tree for determining
+when the parent kernel has finished.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>âValueTypeâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument value type. Only
+present if âValueKindâ is
+âByValueâ. For vector data
+types, the value is for the
+element type. Values include:</p>
+<ul class="last simple">
+<li>âStructâ</li>
+<li>âI8â</li>
+<li>âU8â</li>
+<li>âI16â</li>
+<li>âU16â</li>
+<li>âF16â</li>
+<li>âI32â</li>
+<li>âU32â</li>
+<li>âF32â</li>
+<li>âI64â</li>
+<li>âU64â</li>
+<li>âF64â</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âPointeeAlignâ</td>
+<td>integer</td>
+<td> </td>
+<td>Alignment in bytes of pointee
+type for pointer type kernel
+argument. Must be a power
+of 2. Only present if
+âValueKindâ is
+âDynamicSharedPointerâ.</td>
+</tr>
+<tr class="row-odd"><td>âAddrSpaceQualâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument address space
+qualifier. Only present if
+âValueKindâ is âGlobalBufferâ or
+âDynamicSharedPointerâ. Values
+are:</p>
+<ul class="last simple">
+<li>âPrivateâ</li>
+<li>âGlobalâ</li>
+<li>âConstantâ</li>
+<li>âLocalâ</li>
+<li>âGenericâ</li>
+<li>âRegionâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âAccQualâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument access
+qualifier. Only present if
+âValueKindâ is âImageâ or
+âPipeâ. Values
+are:</p>
+<ul class="last simple">
+<li>âReadOnlyâ</li>
+<li>âWriteOnlyâ</li>
+<li>âReadWriteâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âActualAccQualâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The actual memory accesses
+performed by the kernel on the
+kernel argument. Only present if
+âValueKindâ is âGlobalBufferâ,
+âImageâ, or âPipeâ. This may be
+more restrictive than indicated
+by âAccQualâ to reflect what the
+kernel actual does. If not
+present then the runtime must
+assume what is implied by
+âAccQualâ and âIsConstâ. Values
+are:</p>
+<ul class="last simple">
+<li>âReadOnlyâ</li>
+<li>âWriteOnlyâ</li>
+<li>âReadWriteâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âIsConstâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is const qualified. Only present
+if âValueKindâ is
+âGlobalBufferâ.</td>
+</tr>
+<tr class="row-odd"><td>âIsRestrictâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is restrict qualified. Only
+present if âValueKindâ is
+âGlobalBufferâ.</td>
+</tr>
+<tr class="row-even"><td>âIsVolatileâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is volatile qualified. Only
+present if âValueKindâ is
+âGlobalBufferâ.</td>
+</tr>
+<tr class="row-odd"><td>âIsPipeâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is pipe qualified. Only present
+if âValueKindâ is âPipeâ.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Code Properties Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="39%" />
+<col width="19%" />
+<col width="13%" />
+<col width="29%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âKernargSegmentSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The size in bytes of
+the kernarg segment
+that holds the values
+of the arguments to
+the kernel.</td>
+</tr>
+<tr class="row-odd"><td>âGroupSegmentFixedSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of group
+segment memory
+required by a
+work-group in
+bytes. This does not
+include any
+dynamically allocated
+group segment memory
+that may be added
+when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-even"><td>âPrivateSegmentFixedSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in
+bytes. If the kernel
+uses a dynamic call
+stack then additional
+space must be added
+to this value for the
+call stack.</td>
+</tr>
+<tr class="row-odd"><td>âKernargSegmentAlignâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The maximum byte
+alignment of
+arguments in the
+kernarg segment. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-even"><td>âWavefrontSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Wavefront size. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-odd"><td>âNumSGPRsâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of scalar
+registers used by a
+wavefront for
+GFX6-GFX9. This
+includes the special
+SGPRs for VCC, Flat
+Scratch (GFX7-GFX9)
+and XNACK (for
+GFX8-GFX9). It does
+not include the 16
+SGPR added if a trap
+handler is
+enabled. It is not
+rounded up to the
+allocation
+granularity.</td>
+</tr>
+<tr class="row-even"><td>âNumVGPRsâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of vector
+registers used by
+each work-item for
+GFX6-GFX9</td>
+</tr>
+<tr class="row-odd"><td>âMaxFlatWorkGroupSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Maximum flat
+work-group size
+supported by the
+kernel in work-items.
+Must be >=1 and
+consistent with
+ReqdWorkGroupSize if
+not 0, 0, 0.</td>
+</tr>
+<tr class="row-even"><td>âNumSpilledSGPRsâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a scalar register to
+a register allocator
+created spill
+location.</td>
+</tr>
+<tr class="row-odd"><td>âNumSpilledVGPRsâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a vector register to
+a register allocator
+created spill
+location.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="code-object-v3-metadata-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-code-object-metadata-v3"></span><h5><a class="toc-backref" href="#id72">Code Object V3 Metadata (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-metadata-mattr-code-object-v3" title="Permalink to this headline">¶</a></h5>
+<p>Code object V3 metadata is specified by the <code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code> note record
+(see <a class="reference internal" href="#amdgpu-note-records-v3"><span class="std std-ref">Code Object V3 Note Records (-mattr=+code-object-v3)</span></a>).</p>
+<p>The metadata is represented as Message Pack formatted binary data (see
+<a class="reference internal" href="#msgpack" id="id28">[MsgPack]</a>). The top level is a Message Pack map that includes the
+keys defined in table
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Metadata Map</span></a> and referenced
+tables.</p>
+<p>Additional information can be added to the maps. To avoid conflicts,
+any key names should be prefixed by â<em>vendor-name</em>.â where
+<code class="docutils literal notranslate"><span class="pre">vendor-name</span></code> can be the the name of the vendor and specific vendor
+tool that generates the information. The prefix is abbreviated to
+simply â.â when it appears within a map that has been added by the
+same <em>vendor-name</em>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-metadata-map-table-v3">
+<caption><span class="caption-text">AMDHSA Code Object V3 Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="17%" />
+<col width="14%" />
+<col width="9%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âamdhsa.versionâ</td>
+<td>sequence of
+2 integers</td>
+<td>Required</td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version. Currently 1.</li>
+<li>The second integer is the minor
+version. Currently 0.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âamdhsa.printfâ</td>
+<td>sequence of
+strings</td>
+<td> </td>
+<td><p class="first">Each string is encoded information
+about a printf function call. The
+encoded information is organized as
+fields separated by colon (â:â):</p>
+<p><code class="docutils literal notranslate"><span class="pre">ID:N:S[0]:S[1]:...:S[N-1]:FormatString</span></code></p>
+<p>where:</p>
+<dl class="last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">ID</span></code></dt>
+<dd>A 32 bit integer as a unique id for
+each printf function call</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">N</span></code></dt>
+<dd>A 32 bit integer equal to the number
+of arguments of printf function call
+minus 1</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">S[i]</span></code> (where i = 0, 1, ⦠, N-1)</dt>
+<dd>32 bit integers for the size in bytes
+of the i-th FormatString argument of
+the printf function call</dd>
+<dt>FormatString</dt>
+<dd>The format string passed to the
+printf function call.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>âamdhsa.kernelsâ</td>
+<td>sequence of
+map</td>
+<td>Required</td>
+<td>Sequence of the maps for each
+kernel in the code object. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Kernel Metadata Map</span></a>
+for the definition of the keys included
+in that map.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3">
+<caption><span class="caption-text">AMDHSA Code Object V3 Kernel Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="27%" />
+<col width="11%" />
+<col width="7%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>â.nameâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Source name of the kernel.</td>
+</tr>
+<tr class="row-odd"><td>â.symbolâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Name of the kernel
+descriptor ELF symbol.</td>
+</tr>
+<tr class="row-even"><td>â.languageâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Source language of the kernel.
+Values include:</p>
+<ul class="last simple">
+<li>âOpenCL Câ</li>
+<li>âOpenCL C++â</li>
+<li>âHCCâ</li>
+<li>âHIPâ</li>
+<li>âOpenMPâ</li>
+<li>âAssemblerâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>â.language_versionâ</td>
+<td>sequence of
+2 integers</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version.</li>
+<li>The second integer is the
+minor version.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.argsâ</td>
+<td>sequence of
+map</td>
+<td> </td>
+<td>Sequence of maps of the
+kernel arguments. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Kernel Argument Metadata Map</span></a>
+for the definition of the keys
+included in that map.</td>
+</tr>
+<tr class="row-odd"><td>â.reqd_workgroup_sizeâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">If not 0, 0, 0 then all values
+must be >=1 and the dispatch
+work-group size X, Y, Z must
+correspond to the specified
+values. Defaults to 0, 0, 0.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">reqd_work_group_size</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-even"><td>â.workgroup_size_hintâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">The dispatch work-group size
+X, Y, Z is likely to be the
+specified values.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">work_group_size_hint</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>â.vec_type_hintâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The name of a scalar or vector
+type.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">vec_type_hint</span></code> attribute.</p>
+</td>
+</tr>
+<tr class="row-even"><td>â.device_enqueue_symbolâ</td>
+<td>string</td>
+<td> </td>
+<td>The external symbol name
+associated with a kernel.
+OpenCL runtime allocates a
+global buffer for the symbol
+and saves the kernelâs address
+to it, which is used for
+device side enqueueing. Only
+available for device side
+enqueued kernels.</td>
+</tr>
+<tr class="row-odd"><td>â.kernarg_segment_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The size in bytes of
+the kernarg segment
+that holds the values
+of the arguments to
+the kernel.</td>
+</tr>
+<tr class="row-even"><td>â.group_segment_fixed_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of group
+segment memory
+required by a
+work-group in
+bytes. This does not
+include any
+dynamically allocated
+group segment memory
+that may be added
+when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-odd"><td>â.private_segment_fixed_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in
+bytes. If the kernel
+uses a dynamic call
+stack then additional
+space must be added
+to this value for the
+call stack.</td>
+</tr>
+<tr class="row-even"><td>â.kernarg_segment_alignâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The maximum byte
+alignment of
+arguments in the
+kernarg segment. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-odd"><td>â.wavefront_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Wavefront size. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-even"><td>â.sgpr_countâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of scalar
+registers required by a
+wavefront for
+GFX6-GFX9. A register
+is required if it is
+used explicitly, or
+if a higher numbered
+register is used
+explicitly. This
+includes the special
+SGPRs for VCC, Flat
+Scratch (GFX7-GFX9)
+and XNACK (for
+GFX8-GFX9). It does
+not include the 16
+SGPR added if a trap
+handler is
+enabled. It is not
+rounded up to the
+allocation
+granularity.</td>
+</tr>
+<tr class="row-odd"><td>â.vgpr_countâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of vector
+registers required by
+each work-item for
+GFX6-GFX9. A register
+is required if it is
+used explicitly, or
+if a higher numbered
+register is used
+explicitly.</td>
+</tr>
+<tr class="row-even"><td>â.max_flat_workgroup_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Maximum flat
+work-group size
+supported by the
+kernel in work-items.
+Must be >=1 and
+consistent with
+ReqdWorkGroupSize if
+not 0, 0, 0.</td>
+</tr>
+<tr class="row-odd"><td>â.sgpr_spill_countâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a scalar register to
+a register allocator
+created spill
+location.</td>
+</tr>
+<tr class="row-even"><td>â.vgpr_spill_countâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a vector register to
+a register allocator
+created spill
+location.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3">
+<caption><span class="caption-text">AMDHSA Code Object V3 Kernel Argument Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="17%" />
+<col width="11%" />
+<col width="46%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>â.nameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument name.</td>
+</tr>
+<tr class="row-odd"><td>â.type_nameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument type name.</td>
+</tr>
+<tr class="row-even"><td>â.sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument size in bytes.</td>
+</tr>
+<tr class="row-odd"><td>â.offsetâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument offset in
+bytes. The offset must be a
+multiple of the alignment
+required by the argument.</td>
+</tr>
+<tr class="row-even"><td>â.value_kindâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument kind that
+specifies how to set up the
+corresponding argument.
+Values include:</p>
+<dl class="last docutils">
+<dt>âby_valueâ</dt>
+<dd>The argument is copied
+directly into the kernarg.</dd>
+<dt>âglobal_bufferâ</dt>
+<dd>A global address space pointer
+to the buffer data is passed
+in the kernarg.</dd>
+<dt>âdynamic_shared_pointerâ</dt>
+<dd>A group address space pointer
+to dynamically allocated LDS
+is passed in the kernarg.</dd>
+<dt>âsamplerâ</dt>
+<dd>A global address space
+pointer to a S# is passed in
+the kernarg.</dd>
+<dt>âimageâ</dt>
+<dd>A global address space
+pointer to a T# is passed in
+the kernarg.</dd>
+<dt>âpipeâ</dt>
+<dd>A global address space pointer
+to an OpenCL pipe is passed in
+the kernarg.</dd>
+<dt>âqueueâ</dt>
+<dd>A global address space pointer
+to an OpenCL device enqueue
+queue is passed in the
+kernarg.</dd>
+<dt>âhidden_global_offset_xâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the X
+dimension is passed in the
+kernarg.</dd>
+<dt>âhidden_global_offset_yâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Y
+dimension is passed in the
+kernarg.</dd>
+<dt>âhidden_global_offset_zâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Z
+dimension is passed in the
+kernarg.</dd>
+<dt>âhidden_noneâ</dt>
+<dd>An argument that is not used
+by the kernel. Space needs to
+be left for it, but it does
+not need to be set up.</dd>
+<dt>âhidden_printf_bufferâ</dt>
+<dd>A global address space pointer
+to the runtime printf buffer
+is passed in kernarg.</dd>
+<dt>âhidden_default_queueâ</dt>
+<dd>A global address space pointer
+to the OpenCL device enqueue
+queue that should be used by
+the kernel by default is
+passed in the kernarg.</dd>
+<dt>âhidden_completion_actionâ</dt>
+<dd>A global address space pointer
+to help link enqueued kernels into
+the ancestor tree for determining
+when the parent kernel has finished.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>â.value_typeâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument value type. Only
+present if â.value_kindâ is
+âby_valueâ. For vector data
+types, the value is for the
+element type. Values include:</p>
+<ul class="last simple">
+<li>âstructâ</li>
+<li>âi8â</li>
+<li>âu8â</li>
+<li>âi16â</li>
+<li>âu16â</li>
+<li>âf16â</li>
+<li>âi32â</li>
+<li>âu32â</li>
+<li>âf32â</li>
+<li>âi64â</li>
+<li>âu64â</li>
+<li>âf64â</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.pointee_alignâ</td>
+<td>integer</td>
+<td> </td>
+<td>Alignment in bytes of pointee
+type for pointer type kernel
+argument. Must be a power
+of 2. Only present if
+â.value_kindâ is
+âdynamic_shared_pointerâ.</td>
+</tr>
+<tr class="row-odd"><td>â.address_spaceâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument address space
+qualifier. Only present if
+â.value_kindâ is âglobal_bufferâ or
+âdynamic_shared_pointerâ. Values
+are:</p>
+<ul class="last simple">
+<li>âprivateâ</li>
+<li>âglobalâ</li>
+<li>âconstantâ</li>
+<li>âlocalâ</li>
+<li>âgenericâ</li>
+<li>âregionâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.accessâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument access
+qualifier. Only present if
+â.value_kindâ is âimageâ or
+âpipeâ. Values
+are:</p>
+<ul class="last simple">
+<li>âread_onlyâ</li>
+<li>âwrite_onlyâ</li>
+<li>âread_writeâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>â.actual_accessâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The actual memory accesses
+performed by the kernel on the
+kernel argument. Only present if
+â.value_kindâ is âglobal_bufferâ,
+âimageâ, or âpipeâ. This may be
+more restrictive than indicated
+by â.accessâ to reflect what the
+kernel actual does. If not
+present then the runtime must
+assume what is implied by
+â.accessâ and â.is_constâ . Values
+are:</p>
+<ul class="last simple">
+<li>âread_onlyâ</li>
+<li>âwrite_onlyâ</li>
+<li>âread_writeâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.is_constâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is const qualified. Only present
+if â.value_kindâ is
+âglobal_bufferâ.</td>
+</tr>
+<tr class="row-odd"><td>â.is_restrictâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is restrict qualified. Only
+present if â.value_kindâ is
+âglobal_bufferâ.</td>
+</tr>
+<tr class="row-even"><td>â.is_volatileâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is volatile qualified. Only
+present if â.value_kindâ is
+âglobal_bufferâ.</td>
+</tr>
+<tr class="row-odd"><td>â.is_pipeâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is pipe qualified. Only present
+if â.value_kindâ is âpipeâ.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="kernel-dispatch">
+<h4><a class="toc-backref" href="#id73">Kernel Dispatch</a><a class="headerlink" href="#kernel-dispatch" title="Permalink to this headline">¶</a></h4>
+<p>The HSA architected queuing language (AQL) defines a user space memory interface
+that can be used to control the dispatch of kernels, in an agent independent
+way. An agent can have zero or more AQL queues created for it using the ROCm
+runtime, in which AQL packets (all of which are 64 bytes) can be placed. See the
+<em>HSA Platform System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id29">[HSA]</a> for the AQL queue
+mechanics and packet layouts.</p>
+<p>The packet processor of a kernel agent is responsible for detecting and
+dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the
+packet processor is implemented by the hardware command processor (CP),
+asynchronous dispatch controller (ADC) and shader processor input controller
+(SPI).</p>
+<p>The ROCm runtime can be used to allocate an AQL queue object. It uses the kernel
+mode driver to initialize and register the AQL queue with CP.</p>
+<p>To dispatch a kernel the following actions are performed. This can occur in the
+CPU host program, or from an HSA kernel executing on a GPU.</p>
+<ol class="arabic simple">
+<li>A pointer to an AQL queue for the kernel agent on which the kernel is to be
+executed is obtained.</li>
+<li>A pointer to the kernel descriptor (see
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>) of the kernel to execute is
+obtained. It must be for a kernel that is contained in a code object that that
+was loaded by the ROCm runtime on the kernel agent with which the AQL queue is
+associated.</li>
+<li>Space is allocated for the kernel arguments using the ROCm runtime allocator
+for a memory region with the kernarg property for the kernel agent that will
+execute the kernel. It must be at least 16 byte aligned.</li>
+<li>Kernel argument values are assigned to the kernel argument memory
+allocation. The layout is defined in the <em>HSA Programmerâs Language Reference</em>
+<a class="reference internal" href="#hsa" id="id30">[HSA]</a>. For AMDGPU the kernel execution directly accesses the kernel argument
+memory in the same way constant memory is accessed. (Note that the HSA
+specification allows an implementation to copy the kernel argument contents to
+another location that is accessed by the kernel.)</li>
+<li>An AQL kernel dispatch packet is created on the AQL queue. The ROCm runtime
+api uses 64 bit atomic operations to reserve space in the AQL queue for the
+packet. The packet must be set up, and the final write must use an atomic
+store release to set the packet kind to ensure the packet contents are
+visible to the kernel agent. AQL defines a doorbell signal mechanism to
+notify the kernel agent that the AQL queue has been updated. These rules, and
+the layout of the AQL queue and kernel dispatch packet is defined in the <em>HSA
+System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id31">[HSA]</a>.</li>
+<li>A kernel dispatch packet includes information about the actual dispatch,
+such as grid and work-group size, together with information from the code
+object about the kernel, such as segment sizes. The ROCm runtime queries on
+the kernel symbol can be used to obtain the code object values which are
+recorded in the <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>.</li>
+<li>CP executes micro-code and is responsible for detecting and setting up the
+GPU to execute the wavefronts of a kernel dispatch.</li>
+<li>CP ensures that when the a wavefront starts executing the kernel machine
+code, the scalar general purpose registers (SGPR) and vector general purpose
+registers (VGPR) are set up as required by the machine code. The required
+setup is defined in the <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>. The initial
+register state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>.</li>
+<li>The prolog of the kernel machine code (see
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-prolog"><span class="std std-ref">Kernel Prolog</span></a>) sets up the machine state as necessary
+before continuing executing the machine code that corresponds to the kernel.</li>
+<li>When the kernel dispatch has completed execution, CP signals the completion
+signal specified in the kernel dispatch packet if not 0.</li>
+</ol>
+</div>
+<div class="section" id="memory-spaces">
+<span id="amdgpu-amdhsa-memory-spaces"></span><h4><a class="toc-backref" href="#id74">Memory Spaces</a><a class="headerlink" href="#memory-spaces" title="Permalink to this headline">¶</a></h4>
+<p>The memory space properties are:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-spaces-table">
+<caption><span class="caption-text">AMDHSA Memory Spaces</span><a class="headerlink" href="#amdgpu-amdhsa-memory-spaces-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="28%" />
+<col width="18%" />
+<col width="13%" />
+<col width="11%" />
+<col width="30%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Memory Space Name</th>
+<th class="head">HSA Segment
+Name</th>
+<th class="head">Hardware
+Name</th>
+<th class="head">Address
+Size</th>
+<th class="head">NULL Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Private</td>
+<td>private</td>
+<td>scratch</td>
+<td>32</td>
+<td>0x00000000</td>
+</tr>
+<tr class="row-odd"><td>Local</td>
+<td>group</td>
+<td>LDS</td>
+<td>32</td>
+<td>0xFFFFFFFF</td>
+</tr>
+<tr class="row-even"><td>Global</td>
+<td>global</td>
+<td>global</td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-odd"><td>Constant</td>
+<td>constant</td>
+<td><em>same as
+global</em></td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-even"><td>Generic</td>
+<td>flat</td>
+<td>flat</td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-odd"><td>Region</td>
+<td>N/A</td>
+<td>GDS</td>
+<td>32</td>
+<td><em>not implemented
+for AMDHSA</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The global and constant memory spaces both use global virtual addresses, which
+are the same virtual address space used by the CPU. However, some virtual
+addresses may only be accessible to the CPU, some only accessible by the GPU,
+and some by both.</p>
+<p>Using the constant memory space indicates that the data will not change during
+the execution of the kernel. This allows scalar read instructions to be
+used. The vector and scalar L1 caches are invalidated of volatile data before
+each kernel dispatch execution to allow constant memory to change values between
+kernel dispatches.</p>
+<p>The local memory space uses the hardware Local Data Store (LDS) which is
+automatically allocated when the hardware creates work-groups of wavefronts, and
+freed when all the wavefronts of a work-group have terminated. The data store
+(DS) instructions can be used to access it.</p>
+<p>The private memory space uses the hardware scratch memory support. If the kernel
+uses scratch, then the hardware allocates memory that is accessed using
+wavefront lane dword (4 byte) interleaving. The mapping used from private
+address to physical address is:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre">wavefront-scratch-base</span> <span class="pre">+</span>
+<span class="pre">(private-address</span> <span class="pre">*</span> <span class="pre">wavefront-size</span> <span class="pre">*</span> <span class="pre">4)</span> <span class="pre">+</span>
+<span class="pre">(wavefront-lane-id</span> <span class="pre">*</span> <span class="pre">4)</span></code></div></blockquote>
+<p>There are different ways that the wavefront scratch base address is determined
+by a wavefront (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). This
+memory can be accessed in an interleaved manner using buffer instruction with
+the scratch buffer descriptor and per wavefront scratch offset, by the scratch
+instructions, or by flat instructions. If each lane of a wavefront accesses the
+same private address, the interleaving results in adjacent dwords being accessed
+and hence requires fewer cache lines to be fetched. Multi-dword access is not
+supported except by flat and scratch instructions in GFX9.</p>
+<p>The generic address space uses the hardware flat address support available in
+GFX7-GFX9. This uses two fixed ranges of virtual addresses (the private and
+local appertures), that are outside the range of addressible global memory, to
+map from a flat address to a private or local address.</p>
+<p>FLAT instructions can take a flat address and access global, private (scratch)
+and group (LDS) memory depending in if the address is within one of the
+apperture ranges. Flat access to scratch requires hardware aperture setup and
+setup in the kernel prologue (see <a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>). Flat
+access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup
+(see <a class="reference internal" href="#amdgpu-amdhsa-m0"><span class="std std-ref">M0</span></a>).</p>
+<p>To convert between a segment address and a flat address the base address of the
+appertures address can be used. For GFX7-GFX8 these are available in the
+<a class="reference internal" href="#amdgpu-amdhsa-hsa-aql-queue"><span class="std std-ref">HSA AQL Queue</span></a> the address of which can be obtained with
+Queue Ptr SGPR (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). For
+GFX9 the appature base addresses are directly available as inline constant
+registers <code class="docutils literal notranslate"><span class="pre">SRC_SHARED_BASE/LIMIT</span></code> and <code class="docutils literal notranslate"><span class="pre">SRC_PRIVATE_BASE/LIMIT</span></code>. In 64 bit
+address mode the apperture sizes are 2^32 bytes and the base is aligned to 2^32
+which makes it easier to convert from flat to segment or segment to flat.</p>
+</div>
+<div class="section" id="image-and-samplers">
+<h4><a class="toc-backref" href="#id75">Image and Samplers</a><a class="headerlink" href="#image-and-samplers" title="Permalink to this headline">¶</a></h4>
+<p>Image and sample handles created by the ROCm runtime are 64 bit addresses of a
+hardware 32 byte V# and 48 byte S# object respectively. In order to support the
+HSA <code class="docutils literal notranslate"><span class="pre">query_sampler</span></code> operations two extra dwords are used to store the HSA BRIG
+enumeration values for the queries that are not trivially deducible from the S#
+representation.</p>
+</div>
+<div class="section" id="hsa-signals">
+<h4><a class="toc-backref" href="#id76">HSA Signals</a><a class="headerlink" href="#hsa-signals" title="Permalink to this headline">¶</a></h4>
+<p>HSA signal handles created by the ROCm runtime are 64 bit addresses of a
+structure allocated in memory accessible from both the CPU and GPU. The
+structure is defined by the ROCm runtime and subject to change between releases
+(see <a class="reference internal" href="#amd-rocm-github" id="id32">[AMD-ROCm-github]</a>).</p>
+</div>
+<div class="section" id="hsa-aql-queue">
+<span id="amdgpu-amdhsa-hsa-aql-queue"></span><h4><a class="toc-backref" href="#id77">HSA AQL Queue</a><a class="headerlink" href="#hsa-aql-queue" title="Permalink to this headline">¶</a></h4>
+<p>The HSA AQL queue structure is defined by the ROCm runtime and subject to change
+between releases (see <a class="reference internal" href="#amd-rocm-github" id="id33">[AMD-ROCm-github]</a>). For some processors it contains
+fields needed to implement certain language features such as the flat address
+aperture bases. It also contains fields used by CP such as managing the
+allocation of scratch memory.</p>
+</div>
+<div class="section" id="kernel-descriptor">
+<span id="amdgpu-amdhsa-kernel-descriptor"></span><h4><a class="toc-backref" href="#id78">Kernel Descriptor</a><a class="headerlink" href="#kernel-descriptor" title="Permalink to this headline">¶</a></h4>
+<p>A kernel descriptor consists of the information needed by CP to initiate the
+execution of a kernel, including the entry point address of the machine code
+that implements the kernel.</p>
+<div class="section" id="kernel-descriptor-for-gfx6-gfx9">
+<h5><a class="toc-backref" href="#id79">Kernel Descriptor for GFX6-GFX9</a><a class="headerlink" href="#kernel-descriptor-for-gfx6-gfx9" title="Permalink to this headline">¶</a></h5>
+<p>CP microcode requires the Kernel descriptor to be allocated on 64 byte
+alignment.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table">
+<caption><span class="caption-text">Kernel Descriptor for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="7%" />
+<col width="7%" />
+<col width="31%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>31:0</td>
+<td>4 bytes</td>
+<td>GROUP_SEGMENT_FIXED_SIZE</td>
+<td>The amount of fixed local
+address space memory
+required for a work-group
+in bytes. This does not
+include any dynamically
+allocated local address
+space memory that may be
+added when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-odd"><td>63:32</td>
+<td>4 bytes</td>
+<td>PRIVATE_SEGMENT_FIXED_SIZE</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in bytes. If
+is_dynamic_callstack is 1
+then additional space must
+be added to this value for
+the call stack.</td>
+</tr>
+<tr class="row-even"><td>127:64</td>
+<td>8 bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>191:128</td>
+<td>8 bytes</td>
+<td>KERNEL_CODE_ENTRY_BYTE_OFFSET</td>
+<td>Byte offset (possibly
+negative) from base
+address of kernel
+descriptor to kernelâs
+entry point instruction
+which must be 256 byte
+aligned.</td>
+</tr>
+<tr class="row-even"><td>383:192</td>
+<td>24
+bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>415:384</td>
+<td>4 bytes</td>
+<td>COMPUTE_PGM_RSRC1</td>
+<td>Compute Shader (CS)
+program settings used by
+CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1</span></code>
+configuration
+register. See
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td>447:416</td>
+<td>4 bytes</td>
+<td>COMPUTE_PGM_RSRC2</td>
+<td>Compute Shader (CS)
+program settings used by
+CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2</span></code>
+configuration
+register. See
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td>448</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_PRIVATE_SEGMENT
+_BUFFER</td>
+<td><p class="first">Enable the setup of the
+SGPR user data registers
+(see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">The total number of SGPR
+user data registers
+requested must not exceed
+16 and match value in
+<code class="docutils literal notranslate"><span class="pre">compute_pgm_rsrc2.user_sgpr.user_sgpr_count</span></code>.
+Any requests beyond 16
+will be ignored.</p>
+</td>
+</tr>
+<tr class="row-even"><td>449</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_DISPATCH_PTR</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>450</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_QUEUE_PTR</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>451</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_KERNARG_SEGMENT_PTR</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>452</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_DISPATCH_ID</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>453</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_FLAT_SCRATCH_INIT</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>454</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_PRIVATE_SEGMENT
+_SIZE</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>455</td>
+<td>1 bit</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>511:456</td>
+<td>8 bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-even"><td>512</td>
+<td colspan="3"><strong>Total size 64 bytes.</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table">
+<caption><span class="caption-text">compute_pgm_rsrc1 for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="6%" />
+<col width="6%" />
+<col width="26%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>5:0</td>
+<td>6 bits</td>
+<td>GRANULATED_WORKITEM_VGPR_COUNT</td>
+<td><p class="first">Number of vector register
+blocks used by each work-item;
+granularity is device
+specific:</p>
+<dl class="docutils">
+<dt>GFX6-GFX9</dt>
+<dd><ul class="first last simple">
+<li>vgprs_used 0..256</li>
+<li>max(0, ceil(vgprs_used / 4) - 1)</li>
+</ul>
+</dd>
+</dl>
+<p>Where vgprs_used is defined
+as the highest VGPR number
+explicitly referenced plus
+one.</p>
+<p>Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.VGPRS</span></code>.</p>
+<p class="last">The
+<a class="reference internal" href="#amdgpu-assembler"><span class="std std-ref">Assembler</span></a>
+calculates this
+automatically for the
+selected processor from
+values provided to the
+<cite>.amdhsa_kernel</cite> directive
+by the
+<cite>.amdhsa_next_free_vgpr</cite>
+nested directive (see
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>).</p>
+</td>
+</tr>
+<tr class="row-odd"><td>9:6</td>
+<td>4 bits</td>
+<td>GRANULATED_WAVEFRONT_SGPR_COUNT</td>
+<td><p class="first">Number of scalar register
+blocks used by a wavefront;
+granularity is device
+specific:</p>
+<dl class="docutils">
+<dt>GFX6-GFX8</dt>
+<dd><ul class="first last simple">
+<li>sgprs_used 0..112</li>
+<li>max(0, ceil(sgprs_used / 8) - 1)</li>
+</ul>
+</dd>
+<dt>GFX9</dt>
+<dd><ul class="first last simple">
+<li>sgprs_used 0..112</li>
+<li>2 * max(0, ceil(sgprs_used / 16) - 1)</li>
+</ul>
+</dd>
+</dl>
+<p>Where sgprs_used is
+defined as the highest
+SGPR number explicitly
+referenced plus one, plus
+a target-specific number
+of additional special
+SGPRs for VCC,
+FLAT_SCRATCH (GFX7+) and
+XNACK_MASK (GFX8+), and
+any additional
+target-specific
+limitations. It does not
+include the 16 SGPRs added
+if a trap handler is
+enabled.</p>
+<p>The target-specific
+limitations and special
+SGPR layout are defined in
+the hardware
+documentation, which can
+be found in the
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>
+table.</p>
+<p>Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.SGPRS</span></code>.</p>
+<p class="last">The
+<a class="reference internal" href="#amdgpu-assembler"><span class="std std-ref">Assembler</span></a>
+calculates this
+automatically for the
+selected processor from
+values provided to the
+<cite>.amdhsa_kernel</cite> directive
+by the
+<cite>.amdhsa_next_free_sgpr</cite>
+and <cite>.amdhsa_reserve_*</cite>
+nested directives (see
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>).</p>
+</td>
+</tr>
+<tr class="row-even"><td>11:10</td>
+<td>2 bits</td>
+<td>PRIORITY</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+at the specified priority.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.PRIORITY</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>13:12</td>
+<td>2 bits</td>
+<td>FLOAT_ROUND_MODE_32</td>
+<td><p class="first">Wavefront starts execution
+with specified rounding
+mode for single (32
+bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point rounding
+mode values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>15:14</td>
+<td>2 bits</td>
+<td>FLOAT_ROUND_MODE_16_64</td>
+<td><p class="first">Wavefront starts execution
+with specified rounding
+denorm mode for half/double (16
+and 64 bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point rounding
+mode values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>17:16</td>
+<td>2 bits</td>
+<td>FLOAT_DENORM_MODE_32</td>
+<td><p class="first">Wavefront starts execution
+with specified denorm mode
+for single (32
+bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point denorm mode
+values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>19:18</td>
+<td>2 bits</td>
+<td>FLOAT_DENORM_MODE_16_64</td>
+<td><p class="first">Wavefront starts execution
+with specified denorm mode
+for half/double (16
+and 64 bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point denorm mode
+values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>20</td>
+<td>1 bit</td>
+<td>PRIV</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+in privilege trap handler
+mode.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.PRIV</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>21</td>
+<td>1 bit</td>
+<td>ENABLE_DX10_CLAMP</td>
+<td><p class="first">Wavefront starts execution
+with DX10 clamp mode
+enabled. Used by the vector
+ALU to force DX10 style
+treatment of NaNâs (when
+set, clamp NaN to zero,
+otherwise pass NaN
+through).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.DX10_CLAMP</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>22</td>
+<td>1 bit</td>
+<td>DEBUG_MODE</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+in single step mode.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.DEBUG_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>23</td>
+<td>1 bit</td>
+<td>ENABLE_IEEE_MODE</td>
+<td><p class="first">Wavefront starts execution
+with IEEE mode
+enabled. Floating point
+opcodes that support
+exception flag gathering
+will quiet and propagate
+signaling-NaN inputs per
+IEEE 754-2008. Min_dx10 and
+max_dx10 become IEEE
+754-2008 compliant due to
+signaling-NaN propagation
+and quieting.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.IEEE_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>24</td>
+<td>1 bit</td>
+<td>BULKY</td>
+<td><p class="first">Must be 0.</p>
+<p>Only one work-group allowed
+to execute on a compute
+unit.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.BULKY</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>25</td>
+<td>1 bit</td>
+<td>CDBG_USER</td>
+<td><p class="first">Must be 0.</p>
+<p>Flag that can be used to
+control debugging code.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.CDBG_USER</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>26</td>
+<td>1 bit</td>
+<td>FP16_OVFL</td>
+<td><dl class="first last docutils">
+<dt>GFX6-GFX8</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX9</dt>
+<dd><p class="first">Wavefront starts execution
+with specified fp16 overflow
+mode.</p>
+<ul class="simple">
+<li>If 0, fp16 overflow generates
++/-INF values.</li>
+<li>If 1, fp16 overflow that is the
+result of an +/-INF input value
+or divide by 0 produces a +/-INF,
+otherwise clamps computed
+overflow to +/-MAX_FP16 as
+appropriate.</li>
+</ul>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FP16_OVFL</span></code>.</p>
+</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>31:27</td>
+<td>5 bits</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>32</td>
+<td colspan="3"><strong>Total size 4 bytes</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table">
+<caption><span class="caption-text">compute_pgm_rsrc2 for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="6%" />
+<col width="6%" />
+<col width="26%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_PRIVATE_SEGMENT
+_WAVEFRONT_OFFSET</td>
+<td><p class="first">Enable the setup of the
+SGPR wavefront scratch offset
+system register (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.SCRATCH_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>5:1</td>
+<td>5 bits</td>
+<td>USER_SGPR_COUNT</td>
+<td><p class="first">The total number of SGPR
+user data registers
+requested. This number must
+match the number of user
+data registers enabled.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.USER_SGPR</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>6</td>
+<td>1 bit</td>
+<td>ENABLE_TRAP_HANDLER</td>
+<td><p class="first">Must be 0.</p>
+<p class="last">This bit represents
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TRAP_PRESENT</span></code>,
+which is set by the CP if
+the runtime has installed a
+trap handler.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>7</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_X</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the X
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_X_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>8</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_Y</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the Y
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Y_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>9</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_Z</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the Z
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Z_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>10</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_INFO</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+work-group information (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_SIZE_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>12:11</td>
+<td>2 bits</td>
+<td>ENABLE_VGPR_WORKITEM_ID</td>
+<td><p class="first">Enable the setup of the
+VGPR system registers used
+for the work-item ID.
+<a class="reference internal" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table"><span class="std std-ref">System VGPR Work-Item ID Enumeration Values</span></a>
+defines the values.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TIDIG_CMP_CNT</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>13</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_ADDRESS_WATCH</td>
+<td><p class="first">Must be 0.</p>
+<p>Wavefront starts execution
+with address watch
+exceptions enabled which
+are generated when L1 has
+witnessed a thread access
+an <em>address of
+interest</em>.</p>
+<p class="last">CP is responsible for
+filling in the address
+watch bit in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
+according to what the
+runtime requests.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>14</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_MEMORY</td>
+<td><p class="first">Must be 0.</p>
+<p>Wavefront starts execution
+with memory violation
+exceptions exceptions
+enabled which are generated
+when a memory violation has
+occurred for this wavefront from
+L1 or LDS
+(write-to-read-only-memory,
+mis-aligned atomic, LDS
+address out of range,
+illegal address, etc.).</p>
+<p class="last">CP sets the memory
+violation bit in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
+according to what the
+runtime requests.</p>
+</td>
+</tr>
+<tr class="row-even"><td>23:15</td>
+<td>9 bits</td>
+<td>GRANULATED_LDS_SIZE</td>
+<td><p class="first">Must be 0.</p>
+<p>CP uses the rounded value
+from the dispatch packet,
+not this value, as the
+dispatch may contain
+dynamically allocated group
+segment memory. CP writes
+directly to
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.LDS_SIZE</span></code>.</p>
+<p>Amount of group segment
+(LDS) to allocate for each
+work-group. Granularity is
+device specific:</p>
+<dl class="last docutils">
+<dt>GFX6:</dt>
+<dd>roundup(lds-size / (64 * 4))</dd>
+<dt>GFX7-GFX9:</dt>
+<dd>roundup(lds-size / (128 * 4))</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>24</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_INVALID_OPERATION</td>
+<td><p class="first">Wavefront starts execution
+with specified exceptions
+enabled.</p>
+<p>Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN</span></code>
+(set from bits 0..6).</p>
+<p class="last">IEEE 754 FP Invalid
+Operation</p>
+</td>
+</tr>
+<tr class="row-even"><td>25</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_FP_DENORMAL
+_SOURCE</td>
+<td>FP Denormal one or more
+input operands is a
+denormal number</td>
+</tr>
+<tr class="row-odd"><td>26</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_DIVISION_BY_ZERO</td>
+<td>IEEE 754 FP Division by
+Zero</td>
+</tr>
+<tr class="row-even"><td>27</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_OVERFLOW</td>
+<td>IEEE 754 FP FP Overflow</td>
+</tr>
+<tr class="row-odd"><td>28</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_UNDERFLOW</td>
+<td>IEEE 754 FP Underflow</td>
+</tr>
+<tr class="row-even"><td>29</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_INEXACT</td>
+<td>IEEE 754 FP Inexact</td>
+</tr>
+<tr class="row-odd"><td>30</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_INT_DIVIDE_BY
+_ZERO</td>
+<td>Integer Division by Zero
+(rcp_iflag_f32 instruction
+only)</td>
+</tr>
+<tr class="row-even"><td>31</td>
+<td>1 bit</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>32</td>
+<td colspan="3"><strong>Total size 4 bytes.</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table">
+<caption><span class="caption-text">Floating Point Rounding Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="52%" />
+<col width="7%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>FLOAT_ROUND_MODE_NEAR_EVEN</td>
+<td>0</td>
+<td>Round Ties To Even</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_ROUND_MODE_PLUS_INFINITY</td>
+<td>1</td>
+<td>Round Toward +infinity</td>
+</tr>
+<tr class="row-even"><td>FLOAT_ROUND_MODE_MINUS_INFINITY</td>
+<td>2</td>
+<td>Round Toward -infinity</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_ROUND_MODE_ZERO</td>
+<td>3</td>
+<td>Round Toward 0</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table">
+<caption><span class="caption-text">Floating Point Denorm Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="52%" />
+<col width="7%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>FLOAT_DENORM_MODE_FLUSH_SRC_DST</td>
+<td>0</td>
+<td>Flush Source and Destination
+Denorms</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_DENORM_MODE_FLUSH_DST</td>
+<td>1</td>
+<td>Flush Output Denorms</td>
+</tr>
+<tr class="row-even"><td>FLOAT_DENORM_MODE_FLUSH_SRC</td>
+<td>2</td>
+<td>Flush Source Denorms</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_DENORM_MODE_FLUSH_NONE</td>
+<td>3</td>
+<td>No Flush</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table">
+<caption><span class="caption-text">System VGPR Work-Item ID Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="55%" />
+<col width="7%" />
+<col width="38%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>SYSTEM_VGPR_WORKITEM_ID_X</td>
+<td>0</td>
+<td>Set work-item X dimension
+ID.</td>
+</tr>
+<tr class="row-odd"><td>SYSTEM_VGPR_WORKITEM_ID_X_Y</td>
+<td>1</td>
+<td>Set work-item X and Y
+dimensions ID.</td>
+</tr>
+<tr class="row-even"><td>SYSTEM_VGPR_WORKITEM_ID_X_Y_Z</td>
+<td>2</td>
+<td>Set work-item X, Y and Z
+dimensions ID.</td>
+</tr>
+<tr class="row-odd"><td>SYSTEM_VGPR_WORKITEM_ID_UNDEFINED</td>
+<td>3</td>
+<td>Undefined.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="initial-kernel-execution-state">
+<span id="amdgpu-amdhsa-initial-kernel-execution-state"></span><h4><a class="toc-backref" href="#id80">Initial Kernel Execution State</a><a class="headerlink" href="#initial-kernel-execution-state" title="Permalink to this headline">¶</a></h4>
+<p>This section defines the register state that will be set up by the packet
+processor prior to the start of execution of every wavefront. This is limited by
+the constraints of the hardware controllers of CP/ADC/SPI.</p>
+<p>The order of the SGPR registers is defined, but the compiler can specify which
+ones are actually setup in the kernel descriptor using the <code class="docutils literal notranslate"><span class="pre">enable_sgpr_*</span></code> bit
+fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
+for enabled registers are dense starting at SGPR0: the first enabled register is
+SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have
+an SGPR number.</p>
+<p>The initial SGPRs comprise up to 16 User SRGPs that are set by CP and apply to
+all wavefronts of the grid. It is possible to specify more than 16 User SGPRs using
+the <code class="docutils literal notranslate"><span class="pre">enable_sgpr_*</span></code> bit fields, in which case only the first 16 are actually
+initialized. These are then immediately followed by the System SGPRs that are
+set up by ADC/SPI and can have different values for each wavefront of the grid
+dispatch.</p>
+<p>SGPR register initial state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table"><span class="std std-ref">SGPR Register Set Up Order</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-sgpr-register-set-up-order-table">
+<caption><span class="caption-text">SGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="13%" />
+<col width="33%" />
+<col width="8%" />
+<col width="46%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">SGPR Order</th>
+<th class="head">Name
+(kernel descriptor enable
+field)</th>
+<th class="head">Number
+of
+SGPRs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>First</td>
+<td>Private Segment Buffer
+(enable_sgpr_private
+_segment_buffer)</td>
+<td>4</td>
+<td><p class="first">V# that can be used, together
+with Scratch Wavefront Offset
+as an offset, to access the
+private memory space using a
+segment address.</p>
+<p class="last">CP uses the value provided by
+the runtime.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Dispatch Ptr
+(enable_sgpr_dispatch_ptr)</td>
+<td>2</td>
+<td>64 bit address of AQL dispatch
+packet for kernel dispatch
+actually executing.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Queue Ptr
+(enable_sgpr_queue_ptr)</td>
+<td>2</td>
+<td>64 bit address of amd_queue_t
+object for AQL queue on which
+the dispatch packet was
+queued.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Kernarg Segment Ptr
+(enable_sgpr_kernarg
+_segment_ptr)</td>
+<td>2</td>
+<td><p class="first">64 bit address of Kernarg
+segment. This is directly
+copied from the
+kernarg_address in the kernel
+dispatch packet.</p>
+<p class="last">Having CP load it once avoids
+loading it at the beginning of
+every wavefront.</p>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Dispatch Id
+(enable_sgpr_dispatch_id)</td>
+<td>2</td>
+<td>64 bit Dispatch ID of the
+dispatch packet being
+executed.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Flat Scratch Init
+(enable_sgpr_flat_scratch
+_init)</td>
+<td>2</td>
+<td><p class="first">This is 2 SGPRs:</p>
+<dl class="last docutils">
+<dt>GFX6</dt>
+<dd>Not supported.</dd>
+<dt>GFX7-GFX8</dt>
+<dd><p class="first">The first SGPR is a 32 bit
+byte offset from
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+to per SPI base of memory
+for scratch for the queue
+executing the kernel
+dispatch. CP obtains this
+from the runtime. (The
+Scratch Segment Buffer base
+address is
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+plus this offset.) The value
+of Scratch Wavefront Offset must
+be added to this offset by
+the kernel machine code,
+right shifted by 8, and
+moved to the FLAT_SCRATCH_HI
+SGPR register.
+FLAT_SCRATCH_HI corresponds
+to SGPRn-4 on GFX7, and
+SGPRn-6 on GFX8 (where SGPRn
+is the highest numbered SGPR
+allocated to the wavefront).
+FLAT_SCRATCH_HI is
+multiplied by 256 (as it is
+in units of 256 bytes) and
+added to
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+to calculate the per wavefront
+FLAT SCRATCH BASE in flat
+memory instructions that
+access the scratch
+apperture.</p>
+<p class="last">The second SGPR is 32 bit
+byte size of a single
+work-itemâs scratch memory
+usage. CP obtains this from
+the runtime, and it is
+always a multiple of DWORD.
+CP checks that the value in
+the kernel dispatch packet
+Private Segment Byte Size is
+not larger, and requests the
+runtime to increase the
+queueâs scratch size if
+necessary. The kernel code
+must move it to
+FLAT_SCRATCH_LO which is
+SGPRn-3 on GFX7 and SGPRn-5
+on GFX8. FLAT_SCRATCH_LO is
+used as the FLAT SCRATCH
+SIZE in flat memory
+instructions. Having CP load
+it once avoids loading it at
+the beginning of every
+wavefront.</p>
+</dd>
+<dt>GFX9</dt>
+<dd>This is the
+64 bit base address of the
+per SPI scratch backing
+memory managed by SPI for
+the queue executing the
+kernel dispatch. CP obtains
+this from the runtime (and
+divides it if there are
+multiple Shader Arrays each
+with its own SPI). The value
+of Scratch Wavefront Offset must
+be added by the kernel
+machine code and the result
+moved to the FLAT_SCRATCH
+SGPR which is SGPRn-6 and
+SGPRn-5. It is used as the
+FLAT SCRATCH BASE in flat
+memory instructions.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Private Segment Size</td>
+<td>1</td>
+<td><p class="first">The 32 bit byte size of a
+(enable_sgpr_private single
+work-itemâs
+scratch_segment_size) memory
+allocation. This is the
+value from the kernel
+dispatch packet Private
+Segment Byte Size rounded up
+by CP to a multiple of
+DWORD.</p>
+<p>Having CP load it once avoids
+loading it at the beginning of
+every wavefront.</p>
+<p class="last">This is not used for
+GFX7-GFX8 since it is the same
+value as the second SGPR of
+Flat Scratch Init. However, it
+may be needed for GFX9 which
+changes the meaning of the
+Flat Scratch Init value.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Grid Work-Group Count X
+(enable_sgpr_grid
+_workgroup_count_X)</td>
+<td>1</td>
+<td>32 bit count of the number of
+work-groups in the X dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.x +
+workgroup_size.x - 1) /
+workgroup_size.x).</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Grid Work-Group Count Y
+(enable_sgpr_grid
+_workgroup_count_Y &&
+less than 16 previous
+SGPRs)</td>
+<td>1</td>
+<td><p class="first">32 bit count of the number of
+work-groups in the Y dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.y +
+workgroup_size.y - 1) /
+workgroupSize.y).</p>
+<p class="last">Only initialized if <16
+previous SGPRs initialized.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Grid Work-Group Count Z
+(enable_sgpr_grid
+_workgroup_count_Z &&
+less than 16 previous
+SGPRs)</td>
+<td>1</td>
+<td><p class="first">32 bit count of the number of
+work-groups in the Z dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.z +
+workgroup_size.z - 1) /
+workgroupSize.z).</p>
+<p class="last">Only initialized if <16
+previous SGPRs initialized.</p>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Group Id X
+(enable_sgpr_workgroup_id
+_X)</td>
+<td>1</td>
+<td>32 bit work-group id in X
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Group Id Y
+(enable_sgpr_workgroup_id
+_Y)</td>
+<td>1</td>
+<td>32 bit work-group id in Y
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Group Id Z
+(enable_sgpr_workgroup_id
+_Z)</td>
+<td>1</td>
+<td>32 bit work-group id in Z
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Group Info
+(enable_sgpr_workgroup
+_info)</td>
+<td>1</td>
+<td>{first_wavefront, 14âb0000,
+ordered_append_term[10:0],
+threadgroup_size_in_wavefronts[5:0]}</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Scratch Wavefront Offset
+(enable_sgpr_private
+_segment_wavefront_offset)</td>
+<td>1</td>
+<td>32 bit byte offset from base
+of scratch base of queue
+executing the kernel
+dispatch. Must be used as an
+offset with Private
+segment address when using
+Scratch Segment Buffer. It
+must be used to set up FLAT
+SCRATCH for flat addressing
+(see
+<a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The order of the VGPR registers is defined, but the compiler can specify which
+ones are actually setup in the kernel descriptor using the <code class="docutils literal notranslate"><span class="pre">enable_vgpr*</span></code> bit
+fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
+for enabled registers are dense starting at VGPR0: the first enabled register is
+VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
+VGPR number.</p>
+<p>VGPR register initial state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table"><span class="std std-ref">VGPR Register Set Up Order</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-vgpr-register-set-up-order-table">
+<caption><span class="caption-text">VGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="14%" />
+<col width="36%" />
+<col width="8%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">VGPR Order</th>
+<th class="head">Name
+(kernel descriptor enable
+field)</th>
+<th class="head">Number
+of
+VGPRs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>First</td>
+<td>Work-Item Id X
+(Always initialized)</td>
+<td>1</td>
+<td>32 bit work item id in X
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Item Id Y
+(enable_vgpr_workitem_id
+> 0)</td>
+<td>1</td>
+<td>32 bit work item id in Y
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Item Id Z
+(enable_vgpr_workitem_id
+> 1)</td>
+<td>1</td>
+<td>32 bit work item id in Z
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The setting of registers is done by GPU CP/ADC/SPI hardware as follows:</p>
+<ol class="arabic simple">
+<li>SGPRs before the Work-Group Ids are set by CP using the 16 User Data
+registers.</li>
+<li>Work-group Id registers X, Y, Z are set by ADC which supports any
+combination including none.</li>
+<li>Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
+its value cannot included with the flat scratch init value which is per queue.</li>
+<li>The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
+or (X, Y, Z).</li>
+</ol>
+<p>Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64 bit
+value to the hardware required SGPRn-3 and SGPRn-4 respectively.</p>
+<p>The global segment can be accessed either using buffer instructions (GFX6 which
+has V# 64 bit address support), flat instructions (GFX7-GFX9), or global
+instructions (GFX9).</p>
+<p>If buffer operations are used then the compiler can generate a V# with the
+following properties:</p>
+<ul class="simple">
+<li>base address of 0</li>
+<li>no swizzle</li>
+<li>ATC: 1 if IOMMU present (such as APU)</li>
+<li>ptr64: 1</li>
+<li>MTYPE set to support memory coherence that matches the runtime (such as CC for
+APU and NC for dGPU).</li>
+</ul>
+</div>
+<div class="section" id="kernel-prolog">
+<span id="amdgpu-amdhsa-kernel-prolog"></span><h4><a class="toc-backref" href="#id81">Kernel Prolog</a><a class="headerlink" href="#kernel-prolog" title="Permalink to this headline">¶</a></h4>
+<div class="section" id="m0">
+<span id="amdgpu-amdhsa-m0"></span><h5><a class="toc-backref" href="#id82">M0</a><a class="headerlink" href="#m0" title="Permalink to this headline">¶</a></h5>
+<dl class="docutils">
+<dt>GFX6-GFX8</dt>
+<dd>The M0 register must be initialized with a value at least the total LDS size
+if the kernel may access LDS via DS or flat operations. Total LDS size is
+available in dispatch packet. For M0, it is also possible to use maximum
+possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for
+GFX7-GFX8).</dd>
+<dt>GFX9</dt>
+<dd>The M0 register is not used for range checking LDS accesses and so does not
+need to be initialized in the prolog.</dd>
+</dl>
+</div>
+<div class="section" id="flat-scratch">
+<span id="amdgpu-amdhsa-flat-scratch"></span><h5><a class="toc-backref" href="#id83">Flat Scratch</a><a class="headerlink" href="#flat-scratch" title="Permalink to this headline">¶</a></h5>
+<p>If the kernel may use flat operations to access scratch memory, the prolog code
+must set up FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which
+are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wavefront
+Offset SGPR registers (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>):</p>
+<dl class="docutils">
+<dt>GFX6</dt>
+<dd>Flat scratch is not supported.</dd>
+<dt>GFX7-GFX8</dt>
+<dd><ol class="first last arabic simple">
+<li>The low word of Flat Scratch Init is 32 bit byte offset from
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code> to the base of scratch backing memory
+being managed by SPI for the queue executing the kernel dispatch. This is
+the same value used in the Scratch Segment Buffer V# base address. The
+prolog must add the value of Scratch Wavefront Offset to get the wavefrontâs byte
+scratch backing memory offset from <code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>. Since
+FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right shifted
+by 8 before moving into FLAT_SCRATCH_LO.</li>
+<li>The second word of Flat Scratch Init is 32 bit byte size of a single
+work-items scratch memory usage. This is directly loaded from the kernel
+dispatch packet Private Segment Byte Size and rounded up to a multiple of
+DWORD. Having CP load it once avoids loading it at the beginning of every
+wavefront. The prolog must move it to FLAT_SCRATCH_LO for use as FLAT SCRATCH
+SIZE.</li>
+</ol>
+</dd>
+<dt>GFX9</dt>
+<dd>The Flat Scratch Init is the 64 bit address of the base of scratch backing
+memory being managed by SPI for the queue executing the kernel dispatch. The
+prolog must add the value of Scratch Wavefront Offset and moved to the FLAT_SCRATCH
+pair for use as the flat scratch base in flat memory instructions.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="memory-model">
+<span id="amdgpu-amdhsa-memory-model"></span><h4><a class="toc-backref" href="#id84">Memory Model</a><a class="headerlink" href="#memory-model" title="Permalink to this headline">¶</a></h4>
+<p>This section describes the mapping of LLVM memory model onto AMDGPU machine code
+(see <a class="reference internal" href="LangRef.html#memmodel"><span class="std std-ref">Memory Model for Concurrent Operations</span></a>). <em>The implementation is WIP.</em></p>
+<p>The AMDGPU backend supports the memory synchronization scopes specified in
+<a class="reference internal" href="#amdgpu-memory-scopes"><span class="std std-ref">Memory Scopes</span></a>.</p>
+<p>The code sequences used to implement the memory model are defined in table
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table"><span class="std std-ref">AMDHSA Memory Model Code Sequences GFX6-GFX9</span></a>.</p>
+<p>The sequences specify the order of instructions that a single thread must
+execute. The <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> and <code class="docutils literal notranslate"><span class="pre">buffer_wbinvl1_vol</span></code> are defined with respect
+to other memory instructions executed by the same thread. This allows them to be
+moved earlier or later which can allow them to be combined with other instances
+of the same instruction, or hoisted/sunk out of loops to improve
+performance. Only the instructions related to the memory model are given;
+additional <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions are required to ensure registers are
+defined before being used. These may be able to be combined with the memory
+model <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions as described above.</p>
+<p>The AMDGPU backend supports the following memory models:</p>
+<blockquote>
+<div><dl class="docutils">
+<dt>HSA Memory Model <a class="reference internal" href="#hsa" id="id34">[HSA]</a></dt>
+<dd>The HSA memory model uses a single happens-before relation for all address
+spaces (see <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a>).</dd>
+<dt>OpenCL Memory Model <a class="reference internal" href="#id45" id="id35">[OpenCL]</a></dt>
+<dd>The OpenCL memory model which has separate happens-before relations for the
+global and local address spaces. Only a fence specifying both global and
+local address space, and seq_cst instructions join the relationships. Since
+the LLVM <code class="docutils literal notranslate"><span class="pre">memfence</span></code> instruction does not allow an address space to be
+specified the OpenCL fence has to convervatively assume both local and
+global address space was specified. However, optimizations can often be
+done to eliminate the additional <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions when there are
+no intervening memory instructions which access the corresponding address
+space. The code sequences in the table indicate what can be omitted for the
+OpenCL memory. The target triple environment is used to determine if the
+source language is OpenCL (see <a class="reference internal" href="#amdgpu-opencl"><span class="std std-ref">OpenCL</span></a>).</dd>
+</dl>
+</div></blockquote>
+<p><code class="docutils literal notranslate"><span class="pre">ds/flat_load/store/atomic</span></code> instructions to local memory are termed LDS
+operations.</p>
+<p><code class="docutils literal notranslate"><span class="pre">buffer/global/flat_load/store/atomic</span></code> instructions to global memory are
+termed vector memory operations.</p>
+<p>For GFX6-GFX9:</p>
+<ul class="simple">
+<li>Each agent has multiple compute units (CU).</li>
+<li>Each CU has multiple SIMDs that execute wavefronts.</li>
+<li>The wavefronts for a single work-group are executed in the same CU but may be
+executed by different SIMDs.</li>
+<li>Each CU has a single LDS memory shared by the wavefronts of the work-groups
+executing on it.</li>
+<li>All LDS operations of a CU are performed as wavefront wide operations in a
+global order and involve no caching. Completion is reported to a wavefront in
+execution order.</li>
+<li>The LDS memory has multiple request queues shared by the SIMDs of a
+CU. Therefore, the LDS operations performed by different wavefronts of a work-group
+can be reordered relative to each other, which can result in reordering the
+visibility of vector memory operations with respect to LDS operations of other
+wavefronts in the same work-group. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">lgkmcnt(0)</span></code> is required to
+ensure synchronization between LDS operations and vector memory operations
+between wavefronts of a work-group, but not between operations performed by the
+same wavefront.</li>
+<li>The vector memory operations are performed as wavefront wide operations and
+completion is reported to a wavefront in execution order. The exception is
+that for GFX7-GFX9 <code class="docutils literal notranslate"><span class="pre">flat_load/store/atomic</span></code> instructions can report out of
+vector memory order if they access LDS memory, and out of LDS operation order
+if they access global memory.</li>
+<li>The vector memory operations access a single vector L1 cache shared by all
+SIMDs a CU. Therefore, no special action is required for coherence between the
+lanes of a single wavefront, or for coherence between wavefronts in the same
+work-group. A <code class="docutils literal notranslate"><span class="pre">buffer_wbinvl1_vol</span></code> is required for coherence between wavefronts
+executing in different work-groups as they may be executing on different CUs.</li>
+<li>The scalar memory operations access a scalar L1 cache shared by all wavefronts
+on a group of CUs. The scalar and vector L1 caches are not coherent. However,
+scalar operations are used in a restricted way so do not impact the memory
+model. See <a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</li>
+<li>The vector and scalar memory operations use an L2 cache shared by all CUs on
+the same agent.</li>
+<li>The L2 cache has independent channels to service disjoint ranges of virtual
+addresses.</li>
+<li>Each CU has a separate request queue per channel. Therefore, the vector and
+scalar memory operations performed by wavefronts executing in different work-groups
+(which may be executing on different CUs) of an agent can be reordered
+relative to each other. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">vmcnt(0)</span></code> is required to ensure
+synchronization between vector memory operations of different CUs. It ensures a
+previous vector memory operation has completed before executing a subsequent
+vector memory or LDS operation and so can be used to meet the requirements of
+acquire and release.</li>
+<li>The L2 cache can be kept coherent with other agents on some targets, or ranges
+of virtual addresses can be set up to bypass it to ensure system coherence.</li>
+</ul>
+<p>Private address space uses <code class="docutils literal notranslate"><span class="pre">buffer_load/store</span></code> using the scratch V# (GFX6-GFX8),
+or <code class="docutils literal notranslate"><span class="pre">scratch_load/store</span></code> (GFX9). Since only a single thread is accessing the
+memory, atomic memory orderings are not meaningful and all accesses are treated
+as non-atomic.</p>
+<p>Constant address space uses <code class="docutils literal notranslate"><span class="pre">buffer/global_load</span></code> instructions (or equivalent
+scalar memory instructions). Since the constant address space contents do not
+change during the execution of a kernel dispatch it is not legal to perform
+stores, and atomic memory orderings are not meaningful and all access are
+treated as non-atomic.</p>
+<p>A memory synchronization scope wider than work-group is not meaningful for the
+group (LDS) address space and is treated as work-group.</p>
+<p>The memory model does not support the region address space which is treated as
+non-atomic.</p>
+<p>Acquire memory ordering is not meaningful on store atomic instructions and is
+treated as non-atomic.</p>
+<p>Release memory ordering is not meaningful on load atomic instructions and is
+treated a non-atomic.</p>
+<p>Acquire-release memory ordering is not meaningful on load or store atomic
+instructions and is treated as acquire and release respectively.</p>
+<p>AMDGPU backend only uses scalar memory operations to access memory that is
+proven to not change during the execution of the kernel dispatch. This includes
+constant address space and global address space for program scope const
+variables. Therefore the kernel machine code does not have to maintain the
+scalar L1 cache to ensure it is coherent with the vector L1 cache. The scalar
+and vector L1 caches are invalidated between kernel dispatches by CP since
+constant address space data may change between kernel dispatch executions. See
+<a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</p>
+<p>The one execption is if scalar writes are used to spill SGPR registers. In this
+case the AMDGPU backend ensures the memory location used to spill is never
+accessed by vector memory operations at the same time. If scalar writes are used
+then a <code class="docutils literal notranslate"><span class="pre">s_dcache_wb</span></code> is inserted before the <code class="docutils literal notranslate"><span class="pre">s_endpgm</span></code> and before a function
+return since the locations may be used for vector memory instructions by a
+future wavefront that uses the same scratch area, or a function call that creates a
+frame at the same address, respectively. There is no need for a <code class="docutils literal notranslate"><span class="pre">s_dcache_inv</span></code>
+as all scalar writes are write-before-read in the same thread.</p>
+<p>Scratch backing memory (which is used for the private address space)
+is accessed with MTYPE NC_NV (non-coherenent non-volatile). Since the private
+address space is only accessed by a single thread, and is always
+write-before-read, there is never a need to invalidate these entries from the L1
+cache. Hence all cache invalidates are done as <code class="docutils literal notranslate"><span class="pre">*_vol</span></code> to only invalidate the
+volatile cache lines.</p>
+<p>On dGPU the kernarg backing memory is accessed as UC (uncached) to avoid needing
+to invalidate the L2 cache. This also causes it to be treated as
+non-volatile and so is not invalidated by <code class="docutils literal notranslate"><span class="pre">*_vol</span></code>. On APU it is accessed as CC
+(cache coherent) and so the L2 cache will coherent with the CPU and other
+agents.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table">
+<caption><span class="caption-text">AMDHSA Memory Model Code Sequences GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="15%" />
+<col width="15%" />
+<col width="18%" />
+<col width="13%" />
+<col width="39%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Instr</th>
+<th class="head">LLVM Memory
+Ordering</th>
+<th class="head">LLVM Memory
+Sync Scope</th>
+<th class="head">AMDGPU
+Address
+Space</th>
+<th class="head">AMDGPU Machine Code</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="5"><strong>Non-Atomic</strong></td>
+</tr>
+<tr class="row-odd"><td>load</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+<li>private</li>
+<li>constant</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>!volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load</li>
+</ol>
+</li>
+<li>volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+glc=1</li>
+</ol>
+</li>
+<li>nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+glc=1 slc=1</li>
+</ol>
+</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>load</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+<li>private</li>
+<li>constant</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>!nontemporal<ol class="arabic">
+<li>buffer/global/flat_store</li>
+</ol>
+</li>
+<li>nontemporal<ol class="arabic">
+<li>buffer/global/flat_stote
+glc=1 slc=1</li>
+</ol>
+</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>store</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Unordered Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as non-atomic</em>.</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as non-atomic</em>.</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as monotonic
+atomic</em>.</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Monotonic Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load
+glc=1</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Acquire Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_load</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global/flat_load
+glc=1</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the load
+has completed
+before invalidating
+the cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following
+loads will not see
+stale global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load glc=1</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the flat_load
+has completed
+before invalidating
+the cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_atomic</li>
+<li>waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global/flat_atomic</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+value read by the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+the following
+buffer_wbinvl1_vol.</li>
+<li>Ensures that the
+fence-paired atomic
+has completed
+before invalidating
+the
+cache. Therefore
+any following
+locations read must
+be no older than
+the value read by
+the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before any
+following global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Release Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to memory have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global and local
+have completed
+before performing
+the atomicrmw that
+is being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Acquire-Release Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_atomic</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However,
+since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Must happen after
+any preceding
+local/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing any
+following global
+memory operations.</li>
+<li>Ensures that the
+preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before following
+global memory
+operations. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+local/generic store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+buffer_wbinvl1_vol.</li>
+<li>Ensures that the
+preceding
+global/local/generic
+load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before invalidating
+the cache. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+global/local/generic
+store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data. This
+satisfies the
+requirements of
+acquire.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Sequential Consistent Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+load atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must
+happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent local
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+load atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0)
+and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>waitcnt lgkmcnt(0)
+must happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vmcnt(0)
+must happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent global
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>Same as corresponding
+fence acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The memory order also adds the single thread optimization constrains defined in
+table
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table"><span class="std std-ref">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX9</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table">
+<caption><span class="caption-text">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Memory</th>
+<th class="head">Optimization Constraints</th>
+</tr>
+<tr class="row-even"><th class="head">Ordering</th>
+<th class="head"> </th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-odd"><td>unordered</td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td>monotonic</td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>acquire</td>
+<td><ul class="first last simple">
+<li>If a load atomic/atomicrmw then no following load/load
+atomic/store/ store atomic/atomicrmw/fence instruction can
+be moved before the acquire.</li>
+<li>If a fence then same as load atomic, plus no preceding
+associated fence-paired-atomic can be moved after the fence.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>release</td>
+<td><ul class="first last simple">
+<li>If a store atomic/atomicrmw then no preceding load/load
+atomic/store/ store atomic/atomicrmw/fence instruction can
+be moved after the release.</li>
+<li>If a fence then same as store atomic, plus no following
+associated fence-paired-atomic can be moved before the
+fence.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>acq_rel</td>
+<td>Same constraints as both acquire and release.</td>
+</tr>
+<tr class="row-even"><td>seq_cst</td>
+<td><ul class="first last simple">
+<li>If a load atomic then same constraints as acquire, plus no
+preceding sequentially consistent load atomic/store
+atomic/atomicrmw/fence instruction can be moved after the
+seq_cst.</li>
+<li>If a store atomic then the same constraints as release, plus
+no following sequentially consistent load atomic/store
+atomic/atomicrmw/fence instruction can be moved before the
+seq_cst.</li>
+<li>If an atomicrmw/fence then same constraints as acq_rel.</li>
+</ul>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="trap-handler-abi">
+<h4><a class="toc-backref" href="#id85">Trap Handler ABI</a><a class="headerlink" href="#trap-handler-abi" title="Permalink to this headline">¶</a></h4>
+<p>For code objects generated by AMDGPU backend for HSA <a class="reference internal" href="#hsa" id="id36">[HSA]</a> compatible runtimes
+(such as ROCm <a class="reference internal" href="#amd-rocm" id="id37">[AMD-ROCm]</a>), the runtime installs a trap handler that supports
+the <code class="docutils literal notranslate"><span class="pre">s_trap</span></code> instruction with the following usage:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-amdhsa-os-table">
+<caption><span class="caption-text">AMDGPU Trap Handler for AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="21%" />
+<col width="21%" />
+<col width="32%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Usage</th>
+<th class="head">Code Sequence</th>
+<th class="head">Trap Handler
+Inputs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x00</span></code></td>
+<td> </td>
+<td>Reserved by hardware.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">debugtrap(arg)</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x01</span></code></td>
+<td><dl class="first last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">SGPR0-1</span></code>:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">queue_ptr</span></code></dd>
+<dt><code class="docutils literal notranslate"><span class="pre">VGPR0</span></code>:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">arg</span></code></dd>
+</dl>
+</td>
+<td>Reserved for HSA
+<code class="docutils literal notranslate"><span class="pre">debugtrap</span></code>
+intrinsic (not
+implemented).</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">llvm.trap</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x02</span></code></td>
+<td><dl class="first last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">SGPR0-1</span></code>:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">queue_ptr</span></code></dd>
+</dl>
+</td>
+<td>Causes dispatch to be
+terminated and its
+associated queue put
+into the error state.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">llvm.debugtrap</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x03</span></code></td>
+<td> </td>
+<td><ul class="first last simple">
+<li>If debugger not
+installed then
+behaves as a
+no-operation. The
+trap handler is
+entered and
+immediately returns
+to continue
+execution of the
+wavefront.</li>
+<li>If the debugger is
+installed, causes
+the debug trap to be
+reported by the
+debugger and the
+wavefront is put in
+the halt state until
+resumed by the
+debugger.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x04</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x05</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x06</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td>debugger breakpoint</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x07</span></code></td>
+<td> </td>
+<td>Reserved for debugger
+breakpoints.</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x08</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0xfe</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0xff</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="amdpal">
+<h3><a class="toc-backref" href="#id86">AMDPAL</a><a class="headerlink" href="#amdpal" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+<code class="docutils literal notranslate"><span class="pre">amdpal</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>) for passing runtime parameters
+from the application/runtime to each invocation of a hardware shader. These
+parameters include both generic, application-controlled parameters called
+<em>user data</em> as well as system-generated parameters that are a product of the
+draw or dispatch execution.</p>
+<div class="section" id="user-data">
+<h4><a class="toc-backref" href="#id87">User Data</a><a class="headerlink" href="#user-data" title="Permalink to this headline">¶</a></h4>
+<p>Each hardware stage has a set of 32-bit <em>user data registers</em> which can be
+written from a command buffer and then loaded into SGPRs when waves are launched
+via a subsequent dispatch or draw operation. This is the way most arguments are
+passed from the application/runtime to a hardware shader.</p>
+</div>
+<div class="section" id="compute-user-data">
+<h4><a class="toc-backref" href="#id88">Compute User Data</a><a class="headerlink" href="#compute-user-data" title="Permalink to this headline">¶</a></h4>
+<p>Compute shader user data mappings are simpler than graphics shaders, and have a
+fixed mapping.</p>
+<p>Note that there are always 10 available <em>user data entries</em> in registers -
+entries beyond that limit must be fetched from memory (via the spill table
+pointer) by the shader.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="pal-compute-user-data-registers">
+<caption><span class="caption-text">PAL Compute Shader User Data Registers</span><a class="headerlink" href="#pal-compute-user-data-registers" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="20%" />
+<col width="80%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">User Register</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Global Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-odd"><td>1</td>
+<td>Per-Shader Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td>2 - 11</td>
+<td>Application-Controlled User Data (10 32-bit values)</td>
+</tr>
+<tr class="row-odd"><td>12</td>
+<td>Spill Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td>13 - 14</td>
+<td>Thread Group Count (64-bit pointer)</td>
+</tr>
+<tr class="row-odd"><td>15</td>
+<td>GDS Range</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="graphics-user-data">
+<h4><a class="toc-backref" href="#id89">Graphics User Data</a><a class="headerlink" href="#graphics-user-data" title="Permalink to this headline">¶</a></h4>
+<p>Graphics pipelines support a much more flexible user data mapping:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="pal-graphics-user-data-registers">
+<caption><span class="caption-text">PAL Graphics Shader User Data Registers</span><a class="headerlink" href="#pal-graphics-user-data-registers" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="23%" />
+<col width="77%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">User Register</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Global Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-odd"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Per-Shader Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td><ul class="first last simple">
+<li>1-15</li>
+</ul>
+</td>
+<td>Application Controlled User Data
+(1-15 Contiguous 32-bit Values in Registers)</td>
+</tr>
+<tr class="row-odd"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Spill Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Draw Index (First Stage Only)</td>
+</tr>
+<tr class="row-odd"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Vertex Offset (First Stage Only)</td>
+</tr>
+<tr class="row-even"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Instance Offset (First Stage Only)</td>
+</tr>
+</tbody>
+</table>
+<p>The placement of the global internal table remains fixed in the first <em>user
+data SGPR register</em>. Otherwise all parameters are optional, and can be mapped
+to any desired <em>user data SGPR register</em>, with the following regstrictions:</p>
+<ul class="simple">
+<li>Draw Index, Vertex Offset, and Instance Offset can only be used by the first
+activehardware stage in a graphics pipeline (i.e. where the API vertex
+shader runs).</li>
+<li>Application-controlled user data must be mapped into a contiguous range of
+user data registers.</li>
+<li>The application-controlled user data range supports compaction remapping, so
+only <em>entries</em> that are actually consumed by the shader must be assigned to
+corresponding <em>registers</em>. Note that in order to support an efficient runtime
+implementation, the remapping must pack <em>registers</em> in the same order as
+<em>entries</em>, with unused <em>entries</em> removed.</li>
+</ul>
+</div></blockquote>
+</div>
+<div class="section" id="global-internal-table">
+<span id="pal-global-internal-table"></span><h4><a class="toc-backref" href="#id90">Global Internal Table</a><a class="headerlink" href="#global-internal-table" title="Permalink to this headline">¶</a></h4>
+<p>The global internal table is a table of <em>shader resource descriptors</em> (SRDs) that
+define how certain engine-wide, runtime-managed resources should be accessed
+from a shader. The majority of these resources have HW-defined formats, and it
+is up to the compiler to write/read data as required by the target hardware.</p>
+<p>The following table illustrates the required format:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="pal-git-table">
+<caption><span class="caption-text">PAL Global Internal Table</span><a class="headerlink" href="#pal-git-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="25%" />
+<col width="75%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Offset</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0-3</td>
+<td>Graphics Scratch SRD</td>
+</tr>
+<tr class="row-odd"><td>4-7</td>
+<td>Compute Scratch SRD</td>
+</tr>
+<tr class="row-even"><td>8-11</td>
+<td>ES/GS Ring Output SRD</td>
+</tr>
+<tr class="row-odd"><td>12-15</td>
+<td>ES/GS Ring Input SRD</td>
+</tr>
+<tr class="row-even"><td>16-19</td>
+<td>GS/VS Ring Output #0</td>
+</tr>
+<tr class="row-odd"><td>20-23</td>
+<td>GS/VS Ring Output #1</td>
+</tr>
+<tr class="row-even"><td>24-27</td>
+<td>GS/VS Ring Output #2</td>
+</tr>
+<tr class="row-odd"><td>28-31</td>
+<td>GS/VS Ring Output #3</td>
+</tr>
+<tr class="row-even"><td>32-35</td>
+<td>GS/VS Ring Input SRD</td>
+</tr>
+<tr class="row-odd"><td>36-39</td>
+<td>Tessellation Factor Buffer SRD</td>
+</tr>
+<tr class="row-even"><td>40-43</td>
+<td>Off-Chip LDS Buffer SRD</td>
+</tr>
+<tr class="row-odd"><td>44-47</td>
+<td>Off-Chip Param Cache Buffer SRD</td>
+</tr>
+<tr class="row-even"><td>48-51</td>
+<td>Sample Position Buffer SRD</td>
+</tr>
+<tr class="row-odd"><td>52</td>
+<td>vaRange::ShadowDescriptorTable High Bits</td>
+</tr>
+</tbody>
+</table>
+<p>The pointer to the global internal table passed to the shader as user data
+is a 32-bit pointer. The top 32 bits should be assumed to be the same as
+the top 32 bits of the pipeline, so the shader may use the program
+counterâs top 32 bits.</p>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="unspecified-os">
+<h3><a class="toc-backref" href="#id91">Unspecified OS</a><a class="headerlink" href="#unspecified-os" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+empty (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="id38">
+<h4><a class="toc-backref" href="#id92">Trap Handler ABI</a><a class="headerlink" href="#id38" title="Permalink to this headline">¶</a></h4>
+<p>For code objects generated by AMDGPU backend for non-amdhsa OS, the runtime does
+not install a trap handler. The <code class="docutils literal notranslate"><span class="pre">llvm.trap</span></code> and <code class="docutils literal notranslate"><span class="pre">llvm.debugtrap</span></code>
+instructions are handled as follows:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-non-amdhsa-os-table">
+<caption><span class="caption-text">AMDGPU Trap Handler for Non-AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-non-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="21%" />
+<col width="21%" />
+<col width="59%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Usage</th>
+<th class="head">Code Sequence</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>llvm.trap</td>
+<td>s_endpgm</td>
+<td>Causes wavefront to be terminated.</td>
+</tr>
+<tr class="row-odd"><td>llvm.debugtrap</td>
+<td><em>none</em></td>
+<td>Compiler warning given that there is no
+trap handler installed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+</div>
+<div class="section" id="source-languages">
+<h2><a class="toc-backref" href="#id93">Source Languages</a><a class="headerlink" href="#source-languages" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="opencl">
+<span id="amdgpu-opencl"></span><h3><a class="toc-backref" href="#id94">OpenCL</a><a class="headerlink" href="#opencl" title="Permalink to this headline">¶</a></h3>
+<p>When the language is OpenCL the following differences occur:</p>
+<ol class="arabic simple">
+<li>The OpenCL memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
+<li>The AMDGPU backend appends additional arguments to the kernelâs explicit
+arguments for the AMDHSA OS (see
+<a class="reference internal" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table"><span class="std std-ref">OpenCL kernel implicit arguments appended for AMDHSA OS</span></a>).</li>
+<li>Additional metadata is generated
+(see <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>).</li>
+</ol>
+<blockquote>
+<div><table border="1" class="docutils" id="opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table">
+<caption><span class="caption-text">OpenCL kernel implicit arguments appended for AMDHSA OS</span><a class="headerlink" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="13%" />
+<col width="6%" />
+<col width="14%" />
+<col width="67%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Position</th>
+<th class="head">Byte
+Size</th>
+<th class="head">Byte
+Alignment</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>1</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL Global Offset X</td>
+</tr>
+<tr class="row-odd"><td>2</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL Global Offset Y</td>
+</tr>
+<tr class="row-even"><td>3</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL Global Offset Z</td>
+</tr>
+<tr class="row-odd"><td>4</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL address of printf buffer</td>
+</tr>
+<tr class="row-even"><td>5</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL address of virtual queue used by
+enqueue_kernel.</td>
+</tr>
+<tr class="row-odd"><td>6</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL address of AqlWrap struct used by
+enqueue_kernel.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="hcc">
+<span id="amdgpu-hcc"></span><h3><a class="toc-backref" href="#id95">HCC</a><a class="headerlink" href="#hcc" title="Permalink to this headline">¶</a></h3>
+<p>When the language is HCC the following differences occur:</p>
+<ol class="arabic simple">
+<li>The HSA memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
+</ol>
+</div>
+<div class="section" id="assembler">
+<span id="amdgpu-assembler"></span><h3><a class="toc-backref" href="#id96">Assembler</a><a class="headerlink" href="#assembler" title="Permalink to this headline">¶</a></h3>
+<p>AMDGPU backend has LLVM-MC based assembler which is currently in development.
+It supports AMDGCN GFX6-GFX9.</p>
+<p>This section describes general syntax for instructions and operands.</p>
+<div class="section" id="instructions">
+<h4><a class="toc-backref" href="#id97">Instructions</a><a class="headerlink" href="#instructions" title="Permalink to this headline">¶</a></h4>
+<div class="toctree-wrapper compound">
+</div>
+<p>An instruction has the following <a class="reference internal" href="AMDGPUInstructionSyntax.html"><span class="doc">syntax</span></a>:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><em>opcode</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>operand0</em><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre"><</span></code><em>operand1</em><code class="docutils literal notranslate"><span class="pre">>,...</span> <span class="pre"><</span></code><em>modifier0</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>modifier1</em><code class="docutils literal notranslate"><span class="pre">>...</span></code></div></blockquote>
+<p><a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">Operands</span></a> are normally comma-separated while
+<a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">modifiers</span></a> are space-separated.</p>
+<p>The order of <em>operands</em> and <em>modifiers</em> is fixed.
+Most <em>modifiers</em> are optional and may be omitted.</p>
+<p>See detailed instruction syntax description for <a class="reference internal" href="AMDGPU/AMDGPUAsmGFX7.html"><span class="doc">GFX7</span></a>,
+<a class="reference internal" href="AMDGPU/AMDGPUAsmGFX8.html"><span class="doc">GFX8</span></a> and <a class="reference internal" href="AMDGPU/AMDGPUAsmGFX9.html"><span class="doc">GFX9</span></a>.</p>
+<p>Note that features under development are not included in this description.</p>
+<p>For more information about instructions, their semantics and supported combinations of
+operands, refer to one of instruction set architecture manuals
+<a class="reference internal" href="#amd-gcn-gfx6" id="id39">[AMD-GCN-GFX6]</a>, <a class="reference internal" href="#amd-gcn-gfx7" id="id40">[AMD-GCN-GFX7]</a>, <a class="reference internal" href="#amd-gcn-gfx8" id="id41">[AMD-GCN-GFX8]</a> and <a class="reference internal" href="#amd-gcn-gfx9" id="id42">[AMD-GCN-GFX9]</a>.</p>
+</div>
+<div class="section" id="operands">
+<h4><a class="toc-backref" href="#id98">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h4>
+<p>Detailed description of operands may be found <a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">here</span></a>.</p>
+</div>
+<div class="section" id="modifiers">
+<h4><a class="toc-backref" href="#id99">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h4>
+<p>Detailed description of modifiers may be found <a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">here</span></a>.</p>
+</div>
+<div class="section" id="instruction-examples">
+<h4><a class="toc-backref" href="#id100">Instruction Examples</a><a class="headerlink" href="#instruction-examples" title="Permalink to this headline">¶</a></h4>
+<div class="section" id="ds">
+<h5><a class="toc-backref" href="#id101">DS</a><a class="headerlink" href="#ds" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">ds_add_u32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">16</span>
+<span class="nf">ds_write_src2_b64</span> <span class="nv">v2</span> <span class="nv">offset0</span><span class="p">:</span><span class="mi">4</span> <span class="nv">offset1</span><span class="p">:</span><span class="mi">8</span>
+<span class="nf">ds_cmpst_f32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span><span class="p">,</span> <span class="nv">v6</span>
+<span class="nf">ds_min_rtn_f64</span> <span class="nv">v</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">9</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âLDS/GDS instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="flat">
+<h5><a class="toc-backref" href="#id102">FLAT</a><a class="headerlink" href="#flat" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">flat_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">]</span>
+<span class="nf">flat_store_dwordx3</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+<span class="nf">flat_atomic_swap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v5</span> <span class="nv">glc</span>
+<span class="nf">flat_atomic_cmpswap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span> <span class="nv">slc</span>
+<span class="nf">flat_atomic_fmax_x2</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âFLAT instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="mubuf">
+<h5><a class="toc-backref" href="#id103">MUBUF</a><a class="headerlink" href="#mubuf" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">buffer_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
+<span class="nf">buffer_store_dwordx4</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">ttmp</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span> <span class="nv">offen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">glc</span> <span class="nv">tfe</span>
+<span class="nf">buffer_store_format_xy</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
+<span class="nf">buffer_wbinvl1</span>
+<span class="nf">buffer_atomic_inc</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">11</span><span class="p">],</span> <span class="nv">s4</span> <span class="nv">idxen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">slc</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âMUBUF Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="smrd-smem">
+<h5><a class="toc-backref" href="#id104">SMRD/SMEM</a><a class="headerlink" href="#smrd-smem" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_load_dword</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="mh">0xfc</span>
+<span class="nf">s_load_dwordx8</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">15</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_load_dwordx16</span> <span class="nv">s</span><span class="p">[</span><span class="mi">88</span><span class="p">:</span><span class="mi">103</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_dcache_inv_vol</span>
+<span class="nf">s_memtime</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âScalar Memory Operationsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sop1">
+<h5><a class="toc-backref" href="#id105">SOP1</a><a class="headerlink" href="#sop1" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_mov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_mov_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0x80000000</span>
+<span class="nf">s_cmov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="mi">200</span>
+<span class="nf">s_wqm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+<span class="nf">s_bcnt0_i32_b64</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="nf">s_swappc_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+<span class="nf">s_cbranch_join</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOP1 Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sop2">
+<h5><a class="toc-backref" href="#id106">SOP2</a><a class="headerlink" href="#sop2" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_add_u32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
+<span class="nf">s_and_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+<span class="nf">s_cselect_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
+<span class="nf">s_andn2_b32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_lshr_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
+<span class="nf">s_ashr_i32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_bfm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_bfe_i64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
+<span class="nf">s_cbranch_g_fork</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOP2 Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sopc">
+<h5><a class="toc-backref" href="#id107">SOPC</a><a class="headerlink" href="#sopc" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_cmp_eq_i32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_bitcmp1_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_bitcmp0_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_setvskip</span> <span class="nv">s3</span><span class="p">,</span> <span class="nv">s5</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOPC Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sopp">
+<h5><a class="toc-backref" href="#id108">SOPP</a><a class="headerlink" href="#sopp" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_barrier</span>
+<span class="nf">s_nop</span> <span class="mi">2</span>
+<span class="nf">s_endpgm</span>
+<span class="nf">s_waitcnt</span> <span class="mi">0</span> <span class="c1">; Wait for all counters to be 0</span>
+<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">expcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">lgkmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="c1">; Equivalent to above</span>
+<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="c1">; Wait for vmcnt counter to be 1.</span>
+<span class="nf">s_sethalt</span> <span class="mi">9</span>
+<span class="nf">s_sleep</span> <span class="mi">10</span>
+<span class="nf">s_sendmsg</span> <span class="mh">0x1</span>
+<span class="nf">s_sendmsg</span> <span class="nv">sendmsg</span><span class="p">(</span><span class="nv">MSG_INTERRUPT</span><span class="p">)</span>
+<span class="nf">s_trap</span> <span class="mi">1</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOPP Instructionsâ in ISA Manual.</p>
+<p>Unless otherwise mentioned, little verification is performed on the operands
+of SOPP Instructions, so it is up to the programmer to be familiar with the
+range or acceptable values.</p>
+</div>
+<div class="section" id="valu">
+<h5><a class="toc-backref" href="#id109">VALU</a><a class="headerlink" href="#valu" title="Permalink to this headline">¶</a></h5>
+<p>For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
+the assembler will automatically use optimal encoding based on its operands.
+To force specific encoding, one can add a suffix to the opcode of the instruction:</p>
+<ul class="simple">
+<li>_e32 for 32-bit VOP1/VOP2/VOPC</li>
+<li>_e64 for 64-bit VOP3</li>
+<li>_dpp for VOP_DPP</li>
+<li>_sdwa for VOP_SDWA</li>
+</ul>
+<p>VOP1/VOP2/VOP3/VOPC examples:</p>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_mov_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_nop</span>
+<span class="nf">v_cvt_f64_i32_e32</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v2</span>
+<span class="nf">v_floor_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_bfrev_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_add_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_mul_i32_i24_e64</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="mi">3</span>
+<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">3</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">100</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_addc_u32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="nf">v_max_f16_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
+</pre></div>
+</div>
+<p>VOP_DPP examples:</p>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">2</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">wave_shl</span><span class="p">:</span><span class="mi">1</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_mirror</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_bcast</span><span class="p">:</span><span class="mi">31</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">3</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_add_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_max_f16</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+</pre></div>
+</div>
+<p>VOP_SDWA examples:</p>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PRESERVE</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">DWORD</span>
+<span class="nf">v_min_u32</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v1</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_1</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">DWORD</span>
+<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
+<span class="nf">v_fract_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">DWORD</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
+<span class="nf">v_cmpx_le_u32</span> <span class="nv">vcc</span><span class="p">,</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_2</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_0</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âVector ALU instructionsâ.</p>
+</div>
+</div>
+<div class="section" id="hsa-code-object-directives">
+<h4><a class="toc-backref" href="#id110">HSA Code Object Directives</a><a class="headerlink" href="#hsa-code-object-directives" title="Permalink to this headline">¶</a></h4>
+<p>AMDGPU ABI defines auxiliary data in output code object. In assembly source,
+one can specify them with assembler directives.</p>
+<div class="section" id="hsa-code-object-version-major-minor">
+<h5><a class="toc-backref" href="#id111">.hsa_code_object_version major, minor</a><a class="headerlink" href="#hsa-code-object-version-major-minor" title="Permalink to this headline">¶</a></h5>
+<p><em>major</em> and <em>minor</em> are integers that specify the version of the HSA code
+object that will be generated by the assembler.</p>
+</div>
+<div class="section" id="hsa-code-object-isa-major-minor-stepping-vendor-arch">
+<h5><a class="toc-backref" href="#id112">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a><a class="headerlink" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" title="Permalink to this headline">¶</a></h5>
+<p><em>major</em>, <em>minor</em>, and <em>stepping</em> are all integers that describe the instruction
+set architecture (ISA) version of the assembly program.</p>
+<p><em>vendor</em> and <em>arch</em> are quoted strings. <em>vendor</em> should always be equal to
+âAMDâ and <em>arch</em> should always be equal to âAMDGPUâ.</p>
+<p>By default, the assembler will derive the ISA version, <em>vendor</em>, and <em>arch</em>
+from the value of the -mcpu option that is passed to the assembler.</p>
+</div>
+<div class="section" id="amdgpu-hsa-kernel-name">
+<h5><a class="toc-backref" href="#id113">.amdgpu_hsa_kernel (name)</a><a class="headerlink" href="#amdgpu-hsa-kernel-name" title="Permalink to this headline">¶</a></h5>
+<p>This directives specifies that the symbol with given name is a kernel entry point
+(label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.</p>
+</div>
+<div class="section" id="amd-kernel-code-t">
+<h5><a class="toc-backref" href="#id114">.amd_kernel_code_t</a><a class="headerlink" href="#amd-kernel-code-t" title="Permalink to this headline">¶</a></h5>
+<p>This directive marks the beginning of a list of key / value pairs that are used
+to specify the amd_kernel_code_t object that will be emitted by the assembler.
+The list must be terminated by the <em>.end_amd_kernel_code_t</em> directive. For
+any amd_kernel_code_t values that are unspecified a default value will be
+used. The default value for all keys is 0, with the following exceptions:</p>
+<ul class="simple">
+<li><em>kernel_code_version_major</em> defaults to 1.</li>
+<li><em>machine_kind</em> defaults to 1.</li>
+<li><em>machine_version_major</em>, <em>machine_version_minor</em>, and
+<em>machine_version_stepping</em> are derived from the value of the -mcpu option
+that is passed to the assembler.</li>
+<li><em>kernel_code_entry_byte_offset</em> defaults to 256.</li>
+<li><em>wavefront_size</em> defaults to 6.</li>
+<li><em>kernarg_segment_alignment</em>, <em>group_segment_alignment</em>, and
+<em>private_segment_alignment</em> default to 4. Note that alignments are specified
+as a power of 2, so a value of <strong>n</strong> means an alignment of 2^ <strong>n</strong>.</li>
+</ul>
+<p>The <em>.amd_kernel_code_t</em> directive must be placed immediately after the
+function label and before any instructions.</p>
+<p>For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
+comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.</p>
+<p>Here is an example of a minimal amd_kernel_code_t specification:</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>.hsa_code_object_version 1,0
+.hsa_code_object_isa
+
+.hsatext
+.globl hello_world
+.p2align 8
+.amdgpu_hsa_kernel hello_world
+
+hello_world:
+
+ .amd_kernel_code_t
+ enable_sgpr_kernarg_segment_ptr = 1
+ is_ptr64 = 1
+ compute_pgm_rsrc1_vgprs = 0
+ compute_pgm_rsrc1_sgprs = 0
+ compute_pgm_rsrc2_user_sgpr = 2
+ kernarg_segment_byte_size = 8
+ wavefront_sgpr_count = 2
+ workitem_vgpr_count = 3
+ .end_amd_kernel_code_t
+
+ s_load_dwordx2 s[0:1], s[0:1] 0x0
+ v_mov_b32 v0, 3.14159
+ s_waitcnt lgkmcnt(0)
+ v_mov_b32 v1, s0
+ v_mov_b32 v2, s1
+ flat_store_dword v[1:2], v0
+ s_endpgm
+.Lfunc_end0:
+ .size hello_world, .Lfunc_end0-hello_world
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="predefined-symbols-mattr-code-object-v3">
+<h4><a class="toc-backref" href="#id115">Predefined Symbols (-mattr=+code-object-v3)</a><a class="headerlink" href="#predefined-symbols-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>The AMDGPU assembler defines and updates some symbols automatically. These
+symbols do not affect code generation.</p>
+<div class="section" id="amdgcn-gfx-generation-number">
+<h5><a class="toc-backref" href="#id116">.amdgcn.gfx_generation_number</a><a class="headerlink" href="#amdgcn-gfx-generation-number" title="Permalink to this headline">¶</a></h5>
+<p>Set to the GFX generation number of the target being assembled for. For
+example, when assembling for a âGFX9â target this will be set to the integer
+value â9â. The possible GFX generation numbers are presented in
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+</div>
+<div class="section" id="amdgcn-next-free-vgpr">
+<h5><a class="toc-backref" href="#id117">.amdgcn.next_free_vgpr</a><a class="headerlink" href="#amdgcn-next-free-vgpr" title="Permalink to this headline">¶</a></h5>
+<p>Set to zero before assembly begins. At each instruction, if the current value
+of this symbol is less than or equal to the maximum VGPR number explicitly
+referenced within that instruction then the symbol value is updated to equal
+that VGPR number plus one.</p>
+<p>May be used to set the <cite>.amdhsa_next_free_vpgr</cite> directive in
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>.</p>
+<p>May be set at any time, e.g. manually set to zero at the start of each kernel.</p>
+</div>
+<div class="section" id="amdgcn-next-free-sgpr">
+<h5><a class="toc-backref" href="#id118">.amdgcn.next_free_sgpr</a><a class="headerlink" href="#amdgcn-next-free-sgpr" title="Permalink to this headline">¶</a></h5>
+<p>Set to zero before assembly begins. At each instruction, if the current value
+of this symbol is less than or equal the maximum SGPR number explicitly
+referenced within that instruction then the symbol value is updated to equal
+that SGPR number plus one.</p>
+<p>May be used to set the <cite>.amdhsa_next_free_spgr</cite> directive in
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>.</p>
+<p>May be set at any time, e.g. manually set to zero at the start of each kernel.</p>
+</div>
+</div>
+<div class="section" id="code-object-directives-mattr-code-object-v3">
+<h4><a class="toc-backref" href="#id119">Code Object Directives (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-directives-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>Directives which begin with <code class="docutils literal notranslate"><span class="pre">.amdgcn</span></code> are valid for all <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code>
+architecture processors, and are not OS-specific. Directives which begin with
+<code class="docutils literal notranslate"><span class="pre">.amdhsa</span></code> are specific to <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architecture processors when the
+<code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS is specified. See <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a> and
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+<div class="section" id="amdgcn-target-target">
+<h5><a class="toc-backref" href="#id120">.amdgcn_target <target></a><a class="headerlink" href="#amdgcn-target-target" title="Permalink to this headline">¶</a></h5>
+<p>Optional directive which declares the target supported by the containing
+assembler source file. Valid values are described in
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-target-identification"><span class="std std-ref">Code Object Target Identification</span></a>. Used by the assembler
+to validate command-line options such as <code class="docutils literal notranslate"><span class="pre">-triple</span></code>, <code class="docutils literal notranslate"><span class="pre">-mcpu</span></code>, and those
+which specify target features.</p>
+</div>
+<div class="section" id="amdhsa-kernel-name">
+<h5><a class="toc-backref" href="#id121">.amdhsa_kernel <name></a><a class="headerlink" href="#amdhsa-kernel-name" title="Permalink to this headline">¶</a></h5>
+<p>Creates a correctly aligned AMDHSA kernel descriptor and a symbol,
+<code class="docutils literal notranslate"><span class="pre"><name>.kd</span></code>, in the current location of the current section. Only valid when
+the OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code>. <code class="docutils literal notranslate"><span class="pre"><name></span></code> must be a symbol that labels the first
+instruction to execute, and does not need to be previously defined.</p>
+<p>Marks the beginning of a list of directives used to generate the bytes of a
+kernel descriptor, as described in <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>.
+Directives which may appear in this list are described in
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>. Directives may appear in any order, must
+be valid for the target being assembled for, and cannot be repeated. Directives
+support the range of values specified by the field they reference in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>. If a directive is not specified, it is
+assumed to have its default value, unless it is marked as âRequiredâ, in which
+case it is an error to omit the directive. This list of directives is
+terminated by an <code class="docutils literal notranslate"><span class="pre">.end_amdhsa_kernel</span></code> directive.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdhsa-kernel-directives-table">
+<caption><span class="caption-text">AMDHSA Kernel Assembler Directives</span><a class="headerlink" href="#amdhsa-kernel-directives-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="35%" />
+<col width="10%" />
+<col width="8%" />
+<col width="47%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Directive</th>
+<th class="head">Default</th>
+<th class="head">Supported On</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_group_segment_fixed_size</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls GROUP_SEGMENT_FIXED_SIZE in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_private_segment_fixed_size</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls PRIVATE_SEGMENT_FIXED_SIZE in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_private_segment_buffer</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_dispatch_ptr</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_DISPATCH_PTR in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_queue_ptr</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_QUEUE_PTR in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_kernarg_segment_ptr</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_dispatch_id</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_DISPATCH_ID in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_flat_scratch_init</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_private_segment_size</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_private_segment_wavefront_offset</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_x</span></code></td>
+<td>1</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_ID_X in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_y</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_ID_Y in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_z</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_ID_Z in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_info</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_INFO in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_vgpr_workitem_id</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_VGPR_WORKITEM_ID in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table"><span class="std std-ref">System VGPR Work-Item ID Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_next_free_vgpr</span></code></td>
+<td>Required</td>
+<td>GFX6-GFX9</td>
+<td>Maximum VGPR number explicitly referenced, plus one.
+Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_next_free_sgpr</span></code></td>
+<td>Required</td>
+<td>GFX6-GFX9</td>
+<td>Maximum SGPR number explicitly referenced, plus one.
+Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_vcc</span></code></td>
+<td>1</td>
+<td>GFX6-GFX9</td>
+<td>Whether the kernel may use the special VCC SGPR.
+Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_flat_scratch</span></code></td>
+<td>1</td>
+<td>GFX7-GFX9</td>
+<td>Whether the kernel may use flat instructions to access
+scratch memory. Used to calculate
+GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_xnack_mask</span></code></td>
+<td>Target
+Feature
+Specific
+(+xnack)</td>
+<td>GFX8-GFX9</td>
+<td>Whether the kernel may trigger XNACK replay.
+Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_round_mode_32</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls FLOAT_ROUND_MODE_32 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_round_mode_16_64</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls FLOAT_ROUND_MODE_16_64 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_denorm_mode_32</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls FLOAT_DENORM_MODE_32 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_denorm_mode_16_64</span></code></td>
+<td>3</td>
+<td>GFX6-GFX9</td>
+<td>Controls FLOAT_DENORM_MODE_16_64 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_dx10_clamp</span></code></td>
+<td>1</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_DX10_CLAMP in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_ieee_mode</span></code></td>
+<td>1</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_IEEE_MODE in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_fp16_overflow</span></code></td>
+<td>0</td>
+<td>GFX9</td>
+<td>Controls FP16_OVFL in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_invalid_op</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_denorm_src</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_div_zero</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_overflow</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_underflow</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_inexact</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_int_div_zero</span></code></td>
+<td>0</td>
+<td>GFX6-GFX9</td>
+<td>Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-metadata">
+<h5><a class="toc-backref" href="#id122">.amdgpu_metadata</a><a class="headerlink" href="#amdgpu-metadata" title="Permalink to this headline">¶</a></h5>
+<p>Optional directive which declares the contents of the <code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code>
+note record (see <a class="reference internal" href="#amdgpu-elf-note-records-table-v3"><span class="std std-ref">AMDGPU Code Object V3 ELF Note Records</span></a>).</p>
+<p>The contents must be in the <a class="reference internal" href="#yaml" id="id43">[YAML]</a> markup format, with the same structure and
+semantics described in <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a>.</p>
+<p>This directive is terminated by an <code class="docutils literal notranslate"><span class="pre">.end_amdgpu_metadata</span></code> directive.</p>
+</div>
+</div>
+<div class="section" id="example-hsa-source-code-mattr-code-object-v3">
+<h4><a class="toc-backref" href="#id123">Example HSA Source Code (-mattr=+code-object-v3)</a><a class="headerlink" href="#example-hsa-source-code-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>Here is an example of a minimal assembly source file, defining one HSA kernel:</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>.amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional
+
+.text
+.globl hello_world
+.p2align 8
+.type hello_world, at function
+hello_world:
+ s_load_dwordx2 s[0:1], s[0:1] 0x0
+ v_mov_b32 v0, 3.14159
+ s_waitcnt lgkmcnt(0)
+ v_mov_b32 v1, s0
+ v_mov_b32 v2, s1
+ flat_store_dword v[1:2], v0
+ s_endpgm
+.Lfunc_end0:
+ .size hello_world, .Lfunc_end0-hello_world
+
+.rodata
+.p2align 6
+.amdhsa_kernel hello_world
+ .amdhsa_user_sgpr_kernarg_segment_ptr 1
+ .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr
+ .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr
+.end_amdhsa_kernel
+
+.amdgpu_metadata
+---
+amdhsa.version:
+ - 1
+ - 0
+amdhsa.kernels:
+ - .name: hello_world
+ .symbol: hello_world.kd
+ .kernarg_segment_size: 48
+ .group_segment_fixed_size: 0
+ .private_segment_fixed_size: 0
+ .kernarg_segment_align: 4
+ .wavefront_size: 64
+ .sgpr_count: 2
+ .vgpr_count: 3
+ .max_flat_workgroup_size: 256
+...
+.end_amdgpu_metadata
+</pre></div>
+</div>
+</div>
+</div>
+</div>
+<div class="section" id="additional-documentation">
+<h2><a class="toc-backref" href="#id124">Additional Documentation</a><a class="headerlink" href="#additional-documentation" title="Permalink to this headline">¶</a></h2>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-2000-3000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id3">[AMD-RADEON-HD-2000-3000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf">AMD R6xx shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-4000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id4">[AMD-RADEON-HD-4000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf">AMD R7xx shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-5000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id5">[AMD-RADEON-HD-5000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf">AMD Evergreen shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-6000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id6">[AMD-RADEON-HD-6000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf">AMD Cayman/Trinity shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx6" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX6]</td><td><em>(<a class="fn-backref" href="#id7">1</a>, <a class="fn-backref" href="#id39">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf">AMD Southern Islands Series ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx7" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX7]</td><td><em>(<a class="fn-backref" href="#id8">1</a>, <a class="fn-backref" href="#id40">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf">AMD Sea Islands Series ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx8" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX8]</td><td><em>(<a class="fn-backref" href="#id9">1</a>, <a class="fn-backref" href="#id41">2</a>)</em> <a class="reference external" href="http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf">AMD GCN3 Instruction Set Architecture</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx9" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX9]</td><td><em>(<a class="fn-backref" href="#id10">1</a>, <a class="fn-backref" href="#id42">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/12/Vega_Shader_ISA_28July2017.pdf">AMD âVegaâ Instruction Set Architecture</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-rocm" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-ROCm]</td><td><em>(<a class="fn-backref" href="#id2">1</a>, <a class="fn-backref" href="#id21">2</a>, <a class="fn-backref" href="#id26">3</a>, <a class="fn-backref" href="#id37">4</a>)</em> <a class="reference external" href="http://gpuopen.com/compute-product/rocm/">ROCm: Open Platform for Development, Discovery and Education Around GPU Computing</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-rocm-github" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-ROCm-github]</td><td><em>(<a class="fn-backref" href="#id32">1</a>, <a class="fn-backref" href="#id33">2</a>)</em> <a class="reference external" href="http://github.com/RadeonOpenCompute">ROCm github</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="hsa" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[HSA]</td><td><em>(<a class="fn-backref" href="#id1">1</a>, <a class="fn-backref" href="#id11">2</a>, <a class="fn-backref" href="#id20">3</a>, <a class="fn-backref" href="#id25">4</a>, <a class="fn-backref" href="#id29">5</a>, <a class="fn-backref" href="#id30">6</a>, <a class="fn-backref" href="#id31">7</a>, <a class="fn-backref" href="#id34">8</a>, <a class="fn-backref" href="#id36">9</a>)</em> <a class="reference external" href="http://www.hsafoundation.com/">Heterogeneous System Architecture (HSA) Foundation</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="elf" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[ELF]</td><td><em>(<a class="fn-backref" href="#id18">1</a>, <a class="fn-backref" href="#id19">2</a>)</em> <a class="reference external" href="http://www.sco.com/developers/gabi/">Executable and Linkable Format (ELF)</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="id44" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id24">[DWARF]</a></td><td><a class="reference external" href="http://dwarfstd.org/">DWARF Debugging Information Format</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="yaml" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[YAML]</td><td><em>(<a class="fn-backref" href="#id27">1</a>, <a class="fn-backref" href="#id43">2</a>)</em> <a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html">YAML Ainât Markup Language (YAMLâ¢) Version 1.2</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="msgpack" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[MsgPack]</td><td><em>(<a class="fn-backref" href="#id22">1</a>, <a class="fn-backref" href="#id23">2</a>, <a class="fn-backref" href="#id28">3</a>)</em> <a class="reference external" href="http://www.msgpack.org/">Message Pack</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="id45" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[OpenCL]</td><td><em>(<a class="fn-backref" href="#id13">1</a>, <a class="fn-backref" href="#id35">2</a>)</em> <a class="reference external" href="http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf">The OpenCL Specification Version 2.0</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="hrf" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id12">[HRF]</a></td><td><a class="reference external" href="http://benedictgaster.org/wp-content/uploads/2014/01/asplos269-FINAL.pdf">Heterogeneous-race-free Memory Models</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="clang-attr" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[CLANG-ATTR]</td><td><em>(<a class="fn-backref" href="#id14">1</a>, <a class="fn-backref" href="#id15">2</a>, <a class="fn-backref" href="#id16">3</a>, <a class="fn-backref" href="#id17">4</a>)</em> <a class="reference external" href="http://clang.llvm.org/docs/AttributeReference.html">Attributes in Clang</a></td></tr>
+</tbody>
+</table>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
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+++ www-releases/trunk/8.0.0/docs/AdvancedBuilds.html Wed Mar 20 02:13:27 2019
@@ -0,0 +1,244 @@
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+
+ <div class="section" id="advanced-build-configurations">
+<h1>Advanced Build Configurations<a class="headerlink" href="#advanced-build-configurations" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#bootstrap-builds" id="id2">Bootstrap Builds</a></li>
+<li><a class="reference internal" href="#apple-clang-builds-a-more-complex-bootstrap" id="id3">Apple Clang Builds (A More Complex Bootstrap)</a></li>
+<li><a class="reference internal" href="#multi-stage-pgo" id="id4">Multi-stage PGO</a></li>
+<li><a class="reference internal" href="#stage-non-determinism" id="id5">3-Stage Non-Determinism</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p><a class="reference external" href="http://www.cmake.org/">CMake</a> is a cross-platform build-generator tool. CMake
+does not build the project, it generates the files needed by your build tool
+(GNU make, Visual Studio, etc.) for building LLVM.</p>
+<p>If <strong>you are a new contributor</strong>, please start with the <a class="reference internal" href="GettingStarted.html"><span class="doc">Getting Started with the LLVM System</span></a> or
+<a class="reference internal" href="CMake.html"><span class="doc">Building LLVM with CMake</span></a> pages. This page is intended for users doing more complex builds.</p>
+<p>Many of the examples below are written assuming specific CMake Generators.
+Unless otherwise explicitly called out these commands should work with any CMake
+generator.</p>
+</div>
+<div class="section" id="bootstrap-builds">
+<h2><a class="toc-backref" href="#id2">Bootstrap Builds</a><a class="headerlink" href="#bootstrap-builds" title="Permalink to this headline">¶</a></h2>
+<p>The Clang CMake build system supports bootstrap (aka multi-stage) builds. At a
+high level a multi-stage build is a chain of builds that pass data from one
+stage into the next. The most common and simple version of this is a traditional
+bootstrap build.</p>
+<p>In a simple two-stage bootstrap build, we build clang using the system compiler,
+then use that just-built clang to build clang again. In CMake this simplest form
+of a bootstrap build can be configured with a single option,
+CLANG_ENABLE_BOOTSTRAP.</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -DCLANG_ENABLE_BOOTSTRAP<span class="o">=</span>On <path to source>
+<span class="gp">$</span> ninja stage2
+</pre></div>
+</div>
+<p>This command itself isnât terribly useful because it assumes default
+configurations for each stage. The next series of examples utilize CMake cache
+scripts to provide more complex options.</p>
+<p>By default, only a few CMake options will be passed between stages.
+The list, called _BOOTSTRAP_DEFAULT_PASSTHROUGH, is defined in clang/CMakeLists.txt.
+To force the passing of the variables between stages, use the -DCLANG_BOOTSTRAP_PASSTHROUGH
+CMake option, each variable separated by a â;â. As example:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -DCLANG_ENABLE_BOOTSTRAP<span class="o">=</span>On -DCLANG_BOOTSTRAP_PASSTHROUGH<span class="o">=</span><span class="s2">"CMAKE_INSTALL_PREFIX;CMAKE_VERBOSE_MAKEFILE"</span> <path to source>
+<span class="gp">$</span> ninja stage2
+</pre></div>
+</div>
+<p>CMake options starting by <code class="docutils literal notranslate"><span class="pre">BOOTSTRAP_</span></code> will be passed only to the stage2 build.
+This gives the opportunity to use Clang specific build flags.
+For example, the following CMake call will enabled â-fno-addrsigâ only during
+the stage2 build for C and C++.</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake <span class="o">[</span>..<span class="o">]</span> -DBOOTSTRAP_CMAKE_CXX_FLAGS<span class="o">=</span><span class="s1">'-fno-addrsig'</span> -DBOOTSTRAP_CMAKE_C_FLAGS<span class="o">=</span><span class="s1">'-fno-addrsig'</span> <span class="o">[</span>..<span class="o">]</span>
+</pre></div>
+</div>
+<p>The clang build system refers to builds as stages. A stage1 build is a standard
+build using the compiler installed on the host, and a stage2 build is built
+using the stage1 compiler. This nomenclature holds up to more stages too. In
+general a stage*n* build is built using the output from stage*n-1*.</p>
+</div>
+<div class="section" id="apple-clang-builds-a-more-complex-bootstrap">
+<h2><a class="toc-backref" href="#id3">Apple Clang Builds (A More Complex Bootstrap)</a><a class="headerlink" href="#apple-clang-builds-a-more-complex-bootstrap" title="Permalink to this headline">¶</a></h2>
+<p>Appleâs Clang builds are a slightly more complicated example of the simple
+bootstrapping scenario. Apple Clang is built using a 2-stage build.</p>
+<p>The stage1 compiler is a host-only compiler with some options set. The stage1
+compiler is a balance of optimization vs build time because it is a throwaway.
+The stage2 compiler is the fully optimized compiler intended to ship to users.</p>
+<p>Setting up these compilers requires a lot of options. To simplify the
+configuration the Apple Clang build settings are contained in CMake Cache files.
+You can build an Apple Clang compiler using the following commands:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path to clang>/cmake/caches/Apple-stage1.cmake <path to source>
+<span class="gp">$</span> ninja stage2-distribution
+</pre></div>
+</div>
+<p>This CMake invocation configures the stage1 host compiler, and sets
+CLANG_BOOTSTRAP_CMAKE_ARGS to pass the Apple-stage2.cmake cache script to the
+stage2 configuration step.</p>
+<p>When you build the stage2-distribution target it builds the minimal stage1
+compiler and required tools, then configures and builds the stage2 compiler
+based on the settings in Apple-stage2.cmake.</p>
+<p>This pattern of using cache scripts to set complex settings, and specifically to
+make later stage builds include cache scripts is common in our more advanced
+build configurations.</p>
+</div>
+<div class="section" id="multi-stage-pgo">
+<h2><a class="toc-backref" href="#id4">Multi-stage PGO</a><a class="headerlink" href="#multi-stage-pgo" title="Permalink to this headline">¶</a></h2>
+<p>Profile-Guided Optimizations (PGO) is a really great way to optimize the code
+clang generates. Our multi-stage PGO builds are a workflow for generating PGO
+profiles that can be used to optimize clang.</p>
+<p>At a high level, the way PGO works is that you build an instrumented compiler,
+then you run the instrumented compiler against sample source files. While the
+instrumented compiler runs it will output a bunch of files containing
+performance counters (.profraw files). After generating all the profraw files
+you use llvm-profdata to merge the files into a single profdata file that you
+can feed into the LLVM_PROFDATA_FILE option.</p>
+<p>Our PGO.cmake cache script automates that whole process. You can use it by
+running:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path_to_clang>/cmake/caches/PGO.cmake <<span class="nb">source</span> dir>
+<span class="gp">$</span> ninja stage2-instrumented-generate-profdata
+</pre></div>
+</div>
+<p>If you let that run for a few hours or so, it will place a profdata file in your
+build directory. This takes a really long time because it builds clang twice,
+and you <em>must</em> have compiler-rt in your build tree.</p>
+<p>This process uses any source files under the perf-training directory as training
+data as long as the source files are marked up with LIT-style RUN lines.</p>
+<p>After it finishes you can use âfind . -name clang.profdataâ to find it, but it
+should be at a path something like:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="go"><build dir>/tools/clang/stage2-instrumented-bins/utils/perf-training/clang.profdata</span>
+</pre></div>
+</div>
+<p>You can feed that file into the LLVM_PROFDATA_FILE option when you build your
+optimized compiler.</p>
+<p>The PGO came cache has a slightly different stage naming scheme than other
+multi-stage builds. It generates three stages; stage1, stage2-instrumented, and
+stage2. Both of the stage2 builds are built using the stage1 compiler.</p>
+<p>The PGO came cache generates the following additional targets:</p>
+<dl class="docutils">
+<dt><strong>stage2-instrumented</strong></dt>
+<dd>Builds a stage1 x86 compiler, runtime, and required tools (llvm-config,
+llvm-profdata) then uses that compiler to build an instrumented stage2 compiler.</dd>
+<dt><strong>stage2-instrumented-generate-profdata</strong></dt>
+<dd>Depends on âstage2-instrumentedâ and will use the instrumented compiler to
+generate profdata based on the training files in <clang>/utils/perf-training</dd>
+<dt><strong>stage2</strong></dt>
+<dd>Depends of âstage2-instrumented-generate-profdataâ and will use the stage1
+compiler with the stage2 profdata to build a PGO-optimized compiler.</dd>
+<dt><strong>stage2-check-llvm</strong></dt>
+<dd>Depends on stage2 and runs check-llvm using the stage2 compiler.</dd>
+<dt><strong>stage2-check-clang</strong></dt>
+<dd>Depends on stage2 and runs check-clang using the stage2 compiler.</dd>
+<dt><strong>stage2-check-all</strong></dt>
+<dd>Depends on stage2 and runs check-all using the stage2 compiler.</dd>
+<dt><strong>stage2-test-suite</strong></dt>
+<dd>Depends on stage2 and runs the test-suite using the stage3 compiler (requires
+in-tree test-suite).</dd>
+</dl>
+</div>
+<div class="section" id="stage-non-determinism">
+<h2><a class="toc-backref" href="#id5">3-Stage Non-Determinism</a><a class="headerlink" href="#stage-non-determinism" title="Permalink to this headline">¶</a></h2>
+<p>In the ancient lore of compilers non-determinism is like the multi-headed hydra.
+Whenever its head pops up, terror and chaos ensue.</p>
+<p>Historically one of the tests to verify that a compiler was deterministic would
+be a three stage build. The idea of a three stage build is you take your sources
+and build a compiler (stage1), then use that compiler to rebuild the sources
+(stage2), then you use that compiler to rebuild the sources a third time
+(stage3) with an identical configuration to the stage2 build. At the end of
+this, you have a stage2 and stage3 compiler that should be bit-for-bit
+identical.</p>
+<p>You can perform one of these 3-stage builds with LLVM & clang using the
+following commands:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path_to_clang>/cmake/caches/3-stage.cmake <<span class="nb">source</span> dir>
+<span class="gp">$</span> ninja stage3
+</pre></div>
+</div>
+<p>After the build you can compare the stage2 & stage3 compilers. We have a bot
+setup <a class="reference external" href="http://lab.llvm.org:8011/builders/clang-3stage-ubuntu">here</a> that runs
+this build and compare configuration.</p>
+</div>
+</div>
+
+
+ </div>
+ </div>
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+ </div>
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