[llvm] r356411 - [GlobalISel] Include missing change from r356396

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Mon Mar 18 14:29:21 2019
New Revision: 356411

URL: http://llvm.org/viewvc/llvm-project?rev=356411&view=rev
Log:
[GlobalISel] Include missing change from r356396

Forgot to add a change to relax some asserts in r356396.

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=356411&r1=356410&r2=356411&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Mon Mar 18 14:29:21 2019
@@ -912,10 +912,8 @@ MachineInstrBuilder MachineIRBuilder::bu
   }
   case TargetOpcode::COPY:
     assert(DstOps.size() == 1 && "Invalid Dst");
-    assert(SrcOps.size() == 1 && "Invalid Srcs");
-    assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||
-           SrcOps[0].getLLTTy(*getMRI()) == LLT() ||
-           DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));
+    // If the caller wants to add a subreg source it has to be done separately
+    // so we may not have any SrcOps at this point yet.
     break;
   case TargetOpcode::G_FCMP:
   case TargetOpcode::G_ICMP: {