[PATCH] D58927: [ARM] Fixed an assumption of power-of-2 vector MVT

[Tim Renouf via Phabricator via llvm-commits]

tpr marked 3 inline comments as done.
tpr added inline comments.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:12215
   unsigned NumLanes = Op.getValueType().getVectorNumElements();
-  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
+  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4 || NumLanes == 3) {
     // These instructions only exist converting from i32 to f32. We can handle
----------------
RKSimon wrote:
> dnsampaio wrote:
> > Replicate it here?
> if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)
> 
> Update comment below as well please.
Oops, sorry, forgot the second one.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58927/new/

https://reviews.llvm.org/D58927