[llvm] r355825 - [MIPS][microMIPS] Add a pattern to match TruncIntFP
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 13 14:40:22 PDT 2019
> On Mar 11, 2019, at 07:13, Petar Jovanovic via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Author: petarj
> Date: Mon Mar 11 07:13:31 2019
> New Revision: 355825
>
> URL: http://llvm.org/viewvc/llvm-project?rev=355825&view=rev
> Log:
> [MIPS][microMIPS] Add a pattern to match TruncIntFP
>
> A pattern needed to match TruncIntFP was missing. This was causing multiple
> tests from llvm test suite to fail during compilation for micromips.
>
> Patch by Mirko Brkusanin.
>
> Differential Revision: https://reviews.llvm.org/D58722
>
>
> Added:
> llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll
> Modified:
> llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
> llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=355825&r1=355824&r2=355825&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Mon Mar 11 07:13:31 2019
> @@ -1039,7 +1039,7 @@ class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6
> class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
> FGR32Opnd, II_TRUNC>;
> class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
> - AFGR64Opnd, II_TRUNC>;
> + FGR64Opnd, II_TRUNC>;
> class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
> II_SQRT_S, fsqrt>;
> class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
> @@ -1749,6 +1749,8 @@ def : MipsPat<(f32 fpimm0), (MTC1_MMR6 Z
> def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
> def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
> (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
> +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
> + (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;
>
> def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
> (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=355825&r1=355824&r2=355825&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Mon Mar 11 07:13:31 2019
> @@ -424,6 +424,11 @@ def : MipsPat<(f64 (fpextend FGR32Opnd:$
> def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
> (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
> FGR_32;
> +def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
> + (CVT_W_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
> + FGR_64;
> +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
> + (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6;
>
> // Selects
> defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
>
> Added: llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll?rev=355825&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll Mon Mar 11 07:13:31 2019
> @@ -0,0 +1,418 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M32
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M32
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M32R2-FP64
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M32R2-SF
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M32R3R5
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M32R3R5
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M32R6
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M64
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M64
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M64
> +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=M64R6
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=MMR2-FP32
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=MMR2-FP64
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=MMR2-SF
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=MMR6
> +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\
> +; RUN: FileCheck %s -check-prefixes=MMR6-SF
> +
> +; Test that fptosi can be matched for MIPS targets for various FPU
> +; configurations
> +
> +define i32 @test1(float %t) {
> +; M32-LABEL: test1:
> +; M32: # %bb.0: # %entry
> +; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
Hi Petar,
The instruction numbers this test is checking for (#2637 in this instance) are tablegen-erated and can change as people add more records to tablegen. In particular, if someone adds a TargetOpcode or a GlobalISel generic opcode then this number will change. Could you change the #2637 to {{.*}} and similarly for the other instances below?
> +; M32-NEXT: # <MCOperand Reg:147>
Register numbers are potentially unstable too but as far as I know the only source of instability is the target itself.
> +; M32-NEXT: # <MCOperand Reg:159>>
> +; M32-NEXT: jr $ra # <MCInst #1628 JR
> +; M32-NEXT: # <MCOperand Reg:19>>
> +; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32-NEXT: # <MCOperand Reg:321>
> +; M32-NEXT: # <MCOperand Reg:147>>
> +;
> +; M32R2-FP64-LABEL: test1:
> +; M32R2-FP64: # %bb.0: # %entry
> +; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:159>>
> +; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR
> +; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
> +; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32R2-FP64-NEXT: # <MCOperand Reg:321>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
> +;
> +; M32R2-SF-LABEL: test1:
> +; M32R2-SF: # %bb.0: # %entry
> +; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
> +; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
> +; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
> +; M32R2-SF-NEXT: # <MCInst #2519 SW
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>>
> +; M32R2-SF-NEXT: .cfi_offset 31, -4
> +; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #1606 JAL
> +; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
> +; M32R2-SF-NEXT: nop # <MCInst #2370 SLL
> +; M32R2-SF-NEXT: # <MCOperand Reg:21>
> +; M32R2-SF-NEXT: # <MCOperand Reg:21>
> +; M32R2-SF-NEXT: # <MCOperand Imm:0>>
> +; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
> +; M32R2-SF-NEXT: # <MCInst #1722 LW
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>>
> +; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>>
> +; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:24>>
> +;
> +; M32R3R5-LABEL: test1:
> +; M32R3R5: # %bb.0: # %entry
> +; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
> +; M32R3R5-NEXT: # <MCOperand Reg:147>
> +; M32R3R5-NEXT: # <MCOperand Reg:159>>
> +; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR
> +; M32R3R5-NEXT: # <MCOperand Reg:19>>
> +; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32R3R5-NEXT: # <MCOperand Reg:321>
> +; M32R3R5-NEXT: # <MCOperand Reg:147>>
> +;
> +; M32R6-LABEL: test1:
> +; M32R6: # %bb.0: # %entry
> +; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
> +; M32R6-NEXT: # <MCOperand Reg:147>
> +; M32R6-NEXT: # <MCOperand Reg:159>>
> +; M32R6-NEXT: jr $ra # <MCInst #1607 JALR
> +; M32R6-NEXT: # <MCOperand Reg:21>
> +; M32R6-NEXT: # <MCOperand Reg:19>>
> +; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32R6-NEXT: # <MCOperand Reg:321>
> +; M32R6-NEXT: # <MCOperand Reg:147>>
> +;
> +; M64-LABEL: test1:
> +; M64: # %bb.0: # %entry
> +; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
> +; M64-NEXT: # <MCOperand Reg:147>
> +; M64-NEXT: # <MCOperand Reg:159>>
> +; M64-NEXT: jr $ra # <MCInst #1628 JR
> +; M64-NEXT: # <MCOperand Reg:301>>
> +; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M64-NEXT: # <MCOperand Reg:321>
> +; M64-NEXT: # <MCOperand Reg:147>>
> +;
> +; M64R6-LABEL: test1:
> +; M64R6: # %bb.0: # %entry
> +; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
> +; M64R6-NEXT: # <MCOperand Reg:147>
> +; M64R6-NEXT: # <MCOperand Reg:159>>
> +; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64
> +; M64R6-NEXT: # <MCOperand Reg:355>
> +; M64R6-NEXT: # <MCOperand Reg:301>>
> +; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M64R6-NEXT: # <MCOperand Reg:321>
> +; M64R6-NEXT: # <MCOperand Reg:147>>
> +;
> +; MMR2-FP32-LABEL: test1:
> +; MMR2-FP32: # %bb.0: # %entry
> +; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:159>>
> +; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM
> +; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
> +; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
> +; MMR2-FP32-NEXT: # <MCOperand Reg:321>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
> +;
> +; MMR2-FP64-LABEL: test1:
> +; MMR2-FP64: # %bb.0: # %entry
> +; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:159>>
> +; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM
> +; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
> +; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
> +; MMR2-FP64-NEXT: # <MCOperand Reg:321>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
> +;
> +; MMR2-SF-LABEL: test1:
> +; MMR2-SF: # %bb.0: # %entry
> +; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
> +; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
> +; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
> +; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR2-SF-NEXT: .cfi_offset 31, -4
> +; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #1621 JAL_MM
> +; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
> +; MMR2-SF-NEXT: nop # <MCInst #2370 SLL
> +; MMR2-SF-NEXT: # <MCOperand Reg:21>
> +; MMR2-SF-NEXT: # <MCOperand Reg:21>
> +; MMR2-SF-NEXT: # <MCOperand Imm:0>>
> +; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
> +; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Imm:24>>
> +; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>>
> +;
> +; MMR6-LABEL: test1:
> +; MMR6: # %bb.0: # %entry
> +; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MMR6
> +; MMR6-NEXT: # <MCOperand Reg:147>
> +; MMR6-NEXT: # <MCOperand Reg:159>>
> +; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
> +; MMR6-NEXT: # <MCOperand Reg:321>
> +; MMR6-NEXT: # <MCOperand Reg:147>>
> +; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
> +; MMR6-NEXT: # <MCOperand Reg:19>>
> +;
> +; MMR6-SF-LABEL: test1:
> +; MMR6-SF: # %bb.0: # %entry
> +; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
> +; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
> +; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
> +; MMR6-SF-NEXT: # <MCInst #2519 SW
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR6-SF-NEXT: .cfi_offset 31, -4
> +; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #1610 JALRC16_MMR6
> +; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
> +; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
> +; MMR6-SF-NEXT: # <MCInst #1722 LW
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:24>>
> +; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>>
> +entry:
> + %conv = fptosi float %t to i32
> + ret i32 %conv
> +}
> +
> +define i32 @test2(double %t) {
> +; M32-LABEL: test2:
> +; M32: # %bb.0: # %entry
> +; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32
> +; M32-NEXT: # <MCOperand Reg:147>
> +; M32-NEXT: # <MCOperand Reg:133>>
> +; M32-NEXT: jr $ra # <MCInst #1628 JR
> +; M32-NEXT: # <MCOperand Reg:19>>
> +; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32-NEXT: # <MCOperand Reg:321>
> +; M32-NEXT: # <MCOperand Reg:147>>
> +;
> +; M32R2-FP64-LABEL: test2:
> +; M32R2-FP64: # %bb.0: # %entry
> +; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:373>>
> +; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR
> +; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
> +; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32R2-FP64-NEXT: # <MCOperand Reg:321>
> +; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
> +;
> +; M32R2-SF-LABEL: test2:
> +; M32R2-SF: # %bb.0: # %entry
> +; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
> +; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
> +; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
> +; M32R2-SF-NEXT: # <MCInst #2519 SW
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>>
> +; M32R2-SF-NEXT: .cfi_offset 31, -4
> +; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #1606 JAL
> +; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
> +; M32R2-SF-NEXT: nop # <MCInst #2370 SLL
> +; M32R2-SF-NEXT: # <MCOperand Reg:21>
> +; M32R2-SF-NEXT: # <MCOperand Reg:21>
> +; M32R2-SF-NEXT: # <MCOperand Imm:0>>
> +; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
> +; M32R2-SF-NEXT: # <MCInst #1722 LW
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:20>>
> +; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR
> +; M32R2-SF-NEXT: # <MCOperand Reg:19>>
> +; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Reg:20>
> +; M32R2-SF-NEXT: # <MCOperand Imm:24>>
> +;
> +; M32R3R5-LABEL: test2:
> +; M32R3R5: # %bb.0: # %entry
> +; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32
> +; M32R3R5-NEXT: # <MCOperand Reg:147>
> +; M32R3R5-NEXT: # <MCOperand Reg:133>>
> +; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR
> +; M32R3R5-NEXT: # <MCOperand Reg:19>>
> +; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32R3R5-NEXT: # <MCOperand Reg:321>
> +; M32R3R5-NEXT: # <MCOperand Reg:147>>
> +;
> +; M32R6-LABEL: test2:
> +; M32R6: # %bb.0: # %entry
> +; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
> +; M32R6-NEXT: # <MCOperand Reg:147>
> +; M32R6-NEXT: # <MCOperand Reg:373>>
> +; M32R6-NEXT: jr $ra # <MCInst #1607 JALR
> +; M32R6-NEXT: # <MCOperand Reg:21>
> +; M32R6-NEXT: # <MCOperand Reg:19>>
> +; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M32R6-NEXT: # <MCOperand Reg:321>
> +; M32R6-NEXT: # <MCOperand Reg:147>>
> +;
> +; M64-LABEL: test2:
> +; M64: # %bb.0: # %entry
> +; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
> +; M64-NEXT: # <MCOperand Reg:147>
> +; M64-NEXT: # <MCOperand Reg:373>>
> +; M64-NEXT: jr $ra # <MCInst #1628 JR
> +; M64-NEXT: # <MCOperand Reg:301>>
> +; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M64-NEXT: # <MCOperand Reg:321>
> +; M64-NEXT: # <MCOperand Reg:147>>
> +;
> +; M64R6-LABEL: test2:
> +; M64R6: # %bb.0: # %entry
> +; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
> +; M64R6-NEXT: # <MCOperand Reg:147>
> +; M64R6-NEXT: # <MCOperand Reg:373>>
> +; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64
> +; M64R6-NEXT: # <MCOperand Reg:355>
> +; M64R6-NEXT: # <MCOperand Reg:301>>
> +; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1
> +; M64R6-NEXT: # <MCOperand Reg:321>
> +; M64R6-NEXT: # <MCOperand Reg:147>>
> +;
> +; MMR2-FP32-LABEL: test2:
> +; MMR2-FP32: # %bb.0: # %entry
> +; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_MM
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:133>>
> +; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM
> +; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
> +; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
> +; MMR2-FP32-NEXT: # <MCOperand Reg:321>
> +; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
> +;
> +; MMR2-FP64-LABEL: test2:
> +; MMR2-FP64: # %bb.0: # %entry
> +; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #1097 CVT_W_D64_MM
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:373>>
> +; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM
> +; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
> +; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
> +; MMR2-FP64-NEXT: # <MCOperand Reg:321>
> +; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
> +;
> +; MMR2-SF-LABEL: test2:
> +; MMR2-SF: # %bb.0: # %entry
> +; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
> +; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
> +; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
> +; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR2-SF-NEXT: .cfi_offset 31, -4
> +; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #1621 JAL_MM
> +; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
> +; MMR2-SF-NEXT: nop # <MCInst #2370 SLL
> +; MMR2-SF-NEXT: # <MCOperand Reg:21>
> +; MMR2-SF-NEXT: # <MCOperand Reg:21>
> +; MMR2-SF-NEXT: # <MCOperand Imm:0>>
> +; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
> +; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>
> +; MMR2-SF-NEXT: # <MCOperand Reg:20>
> +; MMR2-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM
> +; MMR2-SF-NEXT: # <MCOperand Imm:24>>
> +; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
> +; MMR2-SF-NEXT: # <MCOperand Reg:19>>
> +;
> +; MMR6-LABEL: test2:
> +; MMR6: # %bb.0: # %entry
> +; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D_MMR6
> +; MMR6-NEXT: # <MCOperand Reg:147>
> +; MMR6-NEXT: # <MCOperand Reg:373>>
> +; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
> +; MMR6-NEXT: # <MCOperand Reg:321>
> +; MMR6-NEXT: # <MCOperand Reg:147>>
> +; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
> +; MMR6-NEXT: # <MCOperand Reg:19>>
> +;
> +; MMR6-SF-LABEL: test2:
> +; MMR6-SF: # %bb.0: # %entry
> +; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
> +; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
> +; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
> +; MMR6-SF-NEXT: # <MCInst #2519 SW
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR6-SF-NEXT: .cfi_offset 31, -4
> +; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #1610 JALRC16_MMR6
> +; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
> +; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
> +; MMR6-SF-NEXT: # <MCInst #1722 LW
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:20>>
> +; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Reg:20>
> +; MMR6-SF-NEXT: # <MCOperand Imm:24>>
> +; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM
> +; MMR6-SF-NEXT: # <MCOperand Reg:19>>
> +entry:
> + %conv = fptosi double %t to i32
> + ret i32 %conv
> +}
>
>
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