[PATCH] D59295: [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.

Wed Mar 13 11:33:39 PDT 2019

arsenm added a comment.

In D59295#1427826 <https://reviews.llvm.org/D59295#1427826>, @cwabbott wrote:

> One idea would be to add a way to tell RA that a certain live range absolutely cannot be split (and probably boost its priority as well, lest we fail to allocate it), pre-allocate one or more of these unsplittable registers for WWM, make every definition in the WWM sequence a partial definition, and add fake definitions of the WWM registers in the closest block with uniform control flow that dominates the WWM sequence in order to prevent definitions whose invalid lanes could be clobbered from using the WWM registers. This gives RA a little more flexibility and means that potentially some other operations could use the WWM registers, but you still basically wind up preallocating them.

Declaring a certain live range unsplittable is impossible. LiveIntervals sort of supports it, but not all the allocators use it. Particularly, FastRegAlloc doesn't really track liveness and spills all values live out of a block. It's important that anything works correctly without LIveIntervals. If you can express the constraints with some series of uses and defs, that would be preferable.

My main concerns are making sure this works with:

1. -O0/fastregalloc
2. Presence of calls
3. Inline asm or any other physical register constraints

================
Comment at: test/CodeGen/AMDGPU/wwm-reserved.ll:2
+; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+
+define amdgpu_cs void @main(<4 x i32> inreg %tmp14) {
----------------
Needs a -O0 run line

================
Comment at: test/CodeGen/AMDGPU/wwm-reserved.ll:57
+}
+
+declare i32 @llvm.amdgcn.wwm.i32(i32)
----------------
Needs some cases with control flow

Repository:
  rL LLVM

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https://reviews.llvm.org/D59295