[PATCH] D59271: MIR: Allow targets to serialize MachineFunctionInfo

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: arphaman, thegameg, MatzeB, t.p.northover, qcolombet.
Herald added subscribers: tpr, nhaehnle, wdng, jvesely.

This has been a very painful missing feature that has made producing
reduced testcases difficult. In particular the various registers
determined for stack access during function lowering were necessary to
avoid undefined register errors in a large percentage of
cases. Implement a subset of the important fields that need to be
preserved for AMDGPU.

      

Most of the changes are to support targets parsing register fields and
properly reporting errors. The biggest sort-of bug remaining is for
fields that can be initialized from the IR section will be overwritten
by a default initialized machineFunctionInfo section. Another
remaining bug is the machineFunctionInfo section is still printed even
if empty.


https://reviews.llvm.org/D59271

Files:
  include/llvm/CodeGen/MIRParser/MIParser.h
  include/llvm/CodeGen/MIRYamlMapping.h
  include/llvm/CodeGen/MachineModuleInfo.h
  include/llvm/Target/TargetMachine.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRParser/MIParser.h
  lib/CodeGen/MIRParser/MIRParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/AMDGPUTargetMachine.h
  lib/Target/AMDGPU/LLVMBuild.txt
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.h
  test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
  test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
  test/CodeGen/AMDGPU/spill-before-exec.mir
  test/CodeGen/AMDGPU/spill-empty-live-interval.mir
  test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
  test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
  test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
  test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
  test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
  test/CodeGen/MIR/AMDGPU/machine-function-info.ll
  test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
  test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
  test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
  test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir
  test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
  test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
  test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir
  test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir

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