[PATCH] D59256: [ARM] Disable LDM with offset for thumb2 cortex-m cpus

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: efriedma, samparker, fhahn, t.p.northover.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

When not optimising for codesize, the extra ADD that can be inserted for the base of an LDM will lead to an extra cycle of latency. Just using LDR's, which are usually pipelined, means fewer total cycles. On Thumb1 cpus, the loads are not pipelined and so it will still be profitable.

This started out as "just turn off the load store optimiser", but has become a little more refined since then. The test case is new, I'm just showing the diff here for clarity.


https://reviews.llvm.org/D59256

Files:
  llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  llvm/test/CodeGen/Thumb2/ldstopt-addm.ll


Index: llvm/test/CodeGen/Thumb2/ldstopt-addm.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/ldstopt-addm.ll
+++ llvm/test/CodeGen/Thumb2/ldstopt-addm.ll
@@ -22,8 +22,9 @@
 ;
 ; CHECK-LABEL: test:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r3, r0, #48
-; CHECK-NEXT:    ldm r3, {r1, r2, r3}
+; CHECK-NEXT:    ldr r1, [r0, #48]
+; CHECK-NEXT:    ldr r2, [r0, #52]
+; CHECK-NEXT:    ldr r3, [r0, #56]
 ; CHECK-NEXT:    ldr r0, [r0, #60]
 ; CHECK-NEXT:    add r0, r3
 ; CHECK-NEXT:    add r1, r2
Index: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -673,6 +673,10 @@
     if (!SafeToClobberCPSR)
       return nullptr;
 
+    // On M class cores, the extra add will only increase latency
+    if (STI->isMClass() && !isThumb1 && !MF->getFunction().optForSize())
+      return nullptr;
+
     unsigned NewBase;
     if (isi32Load(Opcode)) {
       // If it is a load, then just use one of the destination registers


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